release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-pxa/include/mach/balloon3.h

   1 /*
   2  *  linux/include/asm-arm/arch-pxa/balloon3.h
   3  *
   4  *  Authors:    Nick Bane and Wookey
   5  *  Created:    Oct, 2005
   6  *  Copyright:  Toby Churchill Ltd
   7  *  Cribbed from mainstone.c, by Nicholas Pitre
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13
  14 #ifndef ASM_ARCH_BALLOON3_H
  15 #define ASM_ARCH_BALLOON3_H
  16
  17 enum balloon3_features {
  18         BALLOON3_FEATURE_OHCI,
  19         BALLOON3_FEATURE_MMC,
  20         BALLOON3_FEATURE_CF,
  21         BALLOON3_FEATURE_AUDIO,
  22         BALLOON3_FEATURE_TOPPOLY,
  23 };
  24
  25 #define BALLOON3_FPGA_PHYS      PXA_CS4_PHYS
  26 #define BALLOON3_FPGA_VIRT      (0xf1000000)    /* as per balloon2 */
  27 #define BALLOON3_FPGA_LENGTH    0x01000000
  28
  29 /* FPGA / CPLD registers for CF socket */
  30 #define BALLOON3_CF_STATUS_REG          (BALLOON3_FPGA_VIRT + 0x00e00008)
  31 #define BALLOON3_CF_CONTROL_REG         (BALLOON3_FPGA_VIRT + 0x00e00008)
  32 /* FPGA / CPLD version register */
  33 #define BALLOON3_FPGA_VER               (BALLOON3_FPGA_VIRT + 0x00e0001c)
  34 /* FPGA / CPLD registers for NAND flash */
  35 #define BALLOON3_NAND_BASE              (PXA_CS4_PHYS + 0x00e00000)
  36 #define BALLOON3_NAND_IO_REG            (BALLOON3_FPGA_VIRT + 0x00e00000)
  37 #define BALLOON3_NAND_CONTROL2_REG      (BALLOON3_FPGA_VIRT + 0x00e00010)
  38 #define BALLOON3_NAND_STAT_REG          (BALLOON3_FPGA_VIRT + 0x00e00010)
  39 #define BALLOON3_NAND_CONTROL_REG       (BALLOON3_FPGA_VIRT + 0x00e00014)
  40
  41 /* fpga/cpld interrupt control register */
  42 #define BALLOON3_INT_CONTROL_REG        (BALLOON3_FPGA_VIRT + 0x00e0000C)
  43 #define BALLOON3_VERSION_REG            (BALLOON3_FPGA_VIRT + 0x00e0001c)
  44
  45 #define BALLOON3_SAMOSA_ADDR_REG        (BALLOON3_FPGA_VIRT + 0x00c00000)
  46 #define BALLOON3_SAMOSA_DATA_REG        (BALLOON3_FPGA_VIRT + 0x00c00004)
  47 #define BALLOON3_SAMOSA_STATUS_REG      (BALLOON3_FPGA_VIRT + 0x00c0001c)
  48
  49 /* CF Status Register bits (read-only) bits */
  50 #define BALLOON3_CF_nIRQ                (1 << 0)
  51 #define BALLOON3_CF_nSTSCHG_BVD1        (1 << 1)
  52
  53 /* CF Control Set Register bits / CF Control Clear Register bits (write-only) */
  54 #define BALLOON3_CF_RESET               (1 << 0)
  55 #define BALLOON3_CF_ENABLE              (1 << 1)
  56 #define BALLOON3_CF_ADD_ENABLE          (1 << 2)
  57
  58 /* CF Interrupt sources */
  59 #define BALLOON3_BP_CF_NRDY_IRQ         BALLOON3_IRQ(0)
  60 #define BALLOON3_BP_NSTSCHG_IRQ         BALLOON3_IRQ(1)
  61
  62 /* NAND Control register */
  63 #define BALLOON3_NAND_CONTROL_FLWP      (1 << 7)
  64 #define BALLOON3_NAND_CONTROL_FLSE      (1 << 6)
  65 #define BALLOON3_NAND_CONTROL_FLCE3     (1 << 5)
  66 #define BALLOON3_NAND_CONTROL_FLCE2     (1 << 4)
  67 #define BALLOON3_NAND_CONTROL_FLCE1     (1 << 3)
  68 #define BALLOON3_NAND_CONTROL_FLCE0     (1 << 2)
  69 #define BALLOON3_NAND_CONTROL_FLALE     (1 << 1)
  70 #define BALLOON3_NAND_CONTROL_FLCLE     (1 << 0)
  71
  72 /* NAND Status register */
  73 #define BALLOON3_NAND_STAT_RNB          (1 << 0)
  74
  75 /* NAND Control2 register */
  76 #define BALLOON3_NAND_CONTROL2_16BIT    (1 << 0)
  77
  78 /* GPIOs for irqs */
  79 #define BALLOON3_GPIO_AUX_NIRQ          (94)
  80 #define BALLOON3_GPIO_CODEC_IRQ         (95)
  81
  82 /* Timer and Idle LED locations */
  83 #define BALLOON3_GPIO_LED_NAND          (9)
  84 #define BALLOON3_GPIO_LED_IDLE          (10)
  85
  86 /* backlight control */
  87 #define BALLOON3_GPIO_RUN_BACKLIGHT     (99)
  88
  89 #define BALLOON3_GPIO_S0_CD             (105)
  90
  91 /* NAND */
  92 #define BALLOON3_GPIO_RUN_NAND          (102)
  93
  94 /* PCF8574A Leds */
  95 #define BALLOON3_PCF_GPIO_BASE          160
  96 #define BALLOON3_PCF_GPIO_LED0          (BALLOON3_PCF_GPIO_BASE + 0)
  97 #define BALLOON3_PCF_GPIO_LED1          (BALLOON3_PCF_GPIO_BASE + 1)
  98 #define BALLOON3_PCF_GPIO_LED2          (BALLOON3_PCF_GPIO_BASE + 2)
  99 #define BALLOON3_PCF_GPIO_LED3          (BALLOON3_PCF_GPIO_BASE + 3)
 100 #define BALLOON3_PCF_GPIO_LED4          (BALLOON3_PCF_GPIO_BASE + 4)
 101 #define BALLOON3_PCF_GPIO_LED5          (BALLOON3_PCF_GPIO_BASE + 5)
 102 #define BALLOON3_PCF_GPIO_LED6          (BALLOON3_PCF_GPIO_BASE + 6)
 103 #define BALLOON3_PCF_GPIO_LED7          (BALLOON3_PCF_GPIO_BASE + 7)
 104
 105 /* FPGA Interrupt Mask/Acknowledge Register */
 106 #define BALLOON3_INT_S0_IRQ             (1 << 0)  /* PCMCIA 0 IRQ */
 107 #define BALLOON3_INT_S0_STSCHG          (1 << 1)  /* PCMCIA 0 status changed */
 108
 109 /* CPLD (and FPGA) interface definitions */
 110 #define CPLD_LCD0_DATA_SET             0x00
 111 #define CPLD_LCD0_DATA_CLR             0x10
 112 #define CPLD_LCD0_COMMAND_SET          0x01
 113 #define CPLD_LCD0_COMMAND_CLR          0x11
 114 #define CPLD_LCD1_DATA_SET             0x02
 115 #define CPLD_LCD1_DATA_CLR             0x12
 116 #define CPLD_LCD1_COMMAND_SET          0x03
 117 #define CPLD_LCD1_COMMAND_CLR          0x13
 118
 119 #define CPLD_MISC_SET                  0x07
 120 #define CPLD_MISC_CLR                  0x17
 121 #define CPLD_MISC_LOON_NRESET_BIT      0
 122 #define CPLD_MISC_LOON_UNSUSP_BIT      1
 123 #define CPLD_MISC_RUN_5V_BIT           2
 124 #define CPLD_MISC_CHG_D0_BIT           3
 125 #define CPLD_MISC_CHG_D1_BIT           4
 126 #define CPLD_MISC_DAC_NCS_BIT          5
 127
 128 #define CPLD_LCD_SET                   0x08
 129 #define CPLD_LCD_CLR                   0x18
 130 #define CPLD_LCD_BACKLIGHT_EN_0_BIT    0
 131 #define CPLD_LCD_BACKLIGHT_EN_1_BIT    1
 132 #define CPLD_LCD_LED_RED_BIT           4
 133 #define CPLD_LCD_LED_GREEN_BIT         5
 134 #define CPLD_LCD_NRESET_BIT            7
 135
 136 #define CPLD_LCD_RO_SET                0x09
 137 #define CPLD_LCD_RO_CLR                0x19
 138 #define CPLD_LCD_RO_LCD0_nWAIT_BIT     0
 139 #define CPLD_LCD_RO_LCD1_nWAIT_BIT     1
 140
 141 #define CPLD_SERIAL_SET                0x0a
 142 #define CPLD_SERIAL_CLR                0x1a
 143 #define CPLD_SERIAL_GSM_RI_BIT         0
 144 #define CPLD_SERIAL_GSM_CTS_BIT        1
 145 #define CPLD_SERIAL_GSM_DTR_BIT        2
 146 #define CPLD_SERIAL_LPR_CTS_BIT        3
 147 #define CPLD_SERIAL_TC232_CTS_BIT      4
 148 #define CPLD_SERIAL_TC232_DSR_BIT      5
 149
 150 #define CPLD_SROUTING_SET              0x0b
 151 #define CPLD_SROUTING_CLR              0x1b
 152 #define CPLD_SROUTING_MSP430_LPR       0
 153 #define CPLD_SROUTING_MSP430_TC232     1
 154 #define CPLD_SROUTING_MSP430_GSM       2
 155 #define CPLD_SROUTING_LOON_LPR         (0 << 4)
 156 #define CPLD_SROUTING_LOON_TC232       (1 << 4)
 157 #define CPLD_SROUTING_LOON_GSM         (2 << 4)
 158
 159 #define CPLD_AROUTING_SET              0x0c
 160 #define CPLD_AROUTING_CLR              0x1c
 161 #define CPLD_AROUTING_MIC2PHONE_BIT    0
 162 #define CPLD_AROUTING_PHONE2INT_BIT    1
 163 #define CPLD_AROUTING_PHONE2EXT_BIT    2
 164 #define CPLD_AROUTING_LOONL2INT_BIT    3
 165 #define CPLD_AROUTING_LOONL2EXT_BIT    4
 166 #define CPLD_AROUTING_LOONR2PHONE_BIT  5
 167 #define CPLD_AROUTING_LOONR2INT_BIT    6
 168 #define CPLD_AROUTING_LOONR2EXT_BIT    7
 169
 170 /* Balloon3 Interrupts */
 171 #define BALLOON3_IRQ(x)         (IRQ_BOARD_START + (x))
 172
 173 #define BALLOON3_AUX_NIRQ       IRQ_GPIO(BALLOON3_GPIO_AUX_NIRQ)
 174 #define BALLOON3_CODEC_IRQ      IRQ_GPIO(BALLOON3_GPIO_CODEC_IRQ)
 175 #define BALLOON3_S0_CD_IRQ      IRQ_GPIO(BALLOON3_GPIO_S0_CD)
 176
 177 extern int balloon3_has(enum balloon3_features feature);
 178
 179 #endif