| blob | f68552518389fdccf69e1833728dc8f439df0c40 |
1 /*
2 * linux/arch/arm/mach-omap2/prcm.c
3 *
4 * OMAP 24xx Power Reset and Clock Management (PRCM) functions
5 *
6 * Copyright (C) 2005 Nokia Corporation
7 *
8 * Written by Tony Lindgren <tony.lindgren@nokia.com>
9 *
10 * Copyright (C) 2007 Texas Instruments, Inc.
11 * Rajendra Nayak <rnayak@ti.com>
12 *
13 * Some pieces of code Copyright (C) 2005 Texas Instruments, Inc.
14 * Upgraded with OMAP4 support by Abhijit Pagare <abhijitpagare@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
19 */
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/clk.h>
23 #include <linux/io.h>
24 #include <linux/delay.h>
26 #include <plat/common.h>
27 #include <plat/prcm.h>
28 #include <plat/irqs.h>
29 #include <plat/control.h>
41 #define MAX_MODULE_ENABLE_WAIT 100000
44 u32 control_padconf_sys_nirq;
45 u32 iva2_cm_clksel1;
46 u32 iva2_cm_clksel2;
47 u32 cm_sysconfig;
48 u32 sgx_cm_clksel;
49 u32 dss_cm_clksel;
50 u32 cam_cm_clksel;
51 u32 per_cm_clksel;
52 u32 emu_cm_clksel;
53 u32 emu_cm_clkstctrl;
54 u32 pll_cm_autoidle2;
55 u32 pll_cm_clksel4;
56 u32 pll_cm_clksel5;
57 u32 pll_cm_clken2;
58 u32 cm_polctrl;
59 u32 iva2_cm_fclken;
60 u32 iva2_cm_clken_pll;
61 u32 core_cm_fclken1;
62 u32 core_cm_fclken3;
63 u32 sgx_cm_fclken;
64 u32 wkup_cm_fclken;
65 u32 dss_cm_fclken;
66 u32 cam_cm_fclken;
67 u32 per_cm_fclken;
68 u32 usbhost_cm_fclken;
69 u32 core_cm_iclken1;
70 u32 core_cm_iclken2;
71 u32 core_cm_iclken3;
72 u32 sgx_cm_iclken;
73 u32 wkup_cm_iclken;
74 u32 dss_cm_iclken;
75 u32 cam_cm_iclken;
76 u32 per_cm_iclken;
77 u32 usbhost_cm_iclken;
78 u32 iva2_cm_autiidle2;
79 u32 mpu_cm_autoidle2;
80 u32 iva2_cm_clkstctrl;
81 u32 mpu_cm_clkstctrl;
82 u32 core_cm_clkstctrl;
83 u32 sgx_cm_clkstctrl;
84 u32 dss_cm_clkstctrl;
85 u32 cam_cm_clkstctrl;
86 u32 per_cm_clkstctrl;
87 u32 neon_cm_clkstctrl;
88 u32 usbhost_cm_clkstctrl;
89 u32 core_cm_autoidle1;
90 u32 core_cm_autoidle2;
91 u32 core_cm_autoidle3;
92 u32 wkup_cm_autoidle;
93 u32 dss_cm_autoidle;
94 u32 cam_cm_autoidle;
95 u32 per_cm_autoidle;
96 u32 usbhost_cm_autoidle;
97 u32 sgx_cm_sleepdep;
98 u32 dss_cm_sleepdep;
99 u32 cam_cm_sleepdep;
100 u32 per_cm_sleepdep;
101 u32 usbhost_cm_sleepdep;
102 u32 cm_clkout_ctrl;
103 u32 prm_clkout_ctrl;
104 u32 sgx_pm_wkdep;
105 u32 dss_pm_wkdep;
106 u32 cam_pm_wkdep;
107 u32 per_pm_wkdep;
108 u32 neon_pm_wkdep;
109 u32 usbhost_pm_wkdep;
110 u32 core_pm_mpugrpsel1;
111 u32 iva2_pm_ivagrpsel1;
112 u32 core_pm_mpugrpsel3;
113 u32 core_pm_ivagrpsel3;
114 u32 wkup_pm_mpugrpsel;
115 u32 wkup_pm_ivagrpsel;
116 u32 per_pm_mpugrpsel;
117 u32 per_pm_ivagrpsel;
118 u32 wkup_pm_wken;
119 };
124 {
131 }
134 /* Resets clock rates and reboots the system. Only called from system.h */
136 {
144 u32 l;
148 /* Reserve the first word in scratchpad for communicating
149 * with the boot ROM. A pointer to a data structure
150 * describing the boot process can be stored there,
151 * cf. OMAP34xx TRM, Initialization / Software Booting
152 * Configuration. */
156 else
161 OMAP2_RM_RSTCTRL);
164 OMAP4_RM_RSTCTRL);
165 }
168 {
171 }
175 {
178 }
180 /* Read a register in a PRM module */
182 {
184 }
186 /* Write into a register in a PRM module */
188 {
190 }
192 /* Read-modify-write a register in a PRM module. Caller must lock */
194 {
195 u32 v;
203 }
205 /* Read a PRM register, AND it, and shift the result down to bit 0 */
207 {
208 u32 v;
215 }
217 /* Read a register in a CM module */
219 {
221 }
223 /* Write into a register in a CM module */
225 {
227 }
229 /* Read-modify-write a register in a CM module. Caller must lock */
231 {
232 u32 v;
240 }
242 /**
243 * omap2_cm_wait_idlest - wait for IDLEST bit to indicate module readiness
244 * @reg: physical address of module IDLEST register
245 * @mask: value to mask against to determine if the module is active
246 * @idlest: idle state indicator (0 or 1) for the clock
247 * @name: name of the clock (for printk)
248 *
249 * Returns 1 if the module indicated readiness in time, or 0 if it
250 * failed to enable in roughly MAX_MODULE_ENABLE_WAIT microseconds.
251 */
254 {
260 else
263 /* Wait for lock */
270 else
275 };
278 {
279 /* Static mapping, never released */
283 }
287 }
291 }
292 }
294 #ifdef CONFIG_ARCH_OMAP3
296 {
328 OMAP3430_CM_CLKEN_PLL);
375 OMAP2_CM_CLKSTCTRL);
386 OMAP2_CM_CLKSTCTRL);
414 OMAP3_CM_CLKOUT_CTRL_OFFSET);
416 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
447 }
450 {
452 OMAP343X_CONTROL_PADCONF_SYSNIRQ);
454 CM_CLKSEL1);
456 CM_CLKSEL2);
459 CM_CLKSEL);
461 CM_CLKSEL);
463 CM_CLKSEL);
465 CM_CLKSEL);
467 CM_CLKSEL1);
469 OMAP2_CM_CLKSTCTRL);
471 CM_AUTOIDLE2);
473 OMAP3430ES2_CM_CLKSEL4);
475 OMAP3430ES2_CM_CLKSEL5);
477 OMAP3430ES2_CM_CLKEN2);
480 CM_FCLKEN);
482 OMAP3430_CM_CLKEN_PLL);
485 OMAP3430ES2_CM_FCLKEN3);
487 CM_FCLKEN);
490 CM_FCLKEN);
492 CM_FCLKEN);
494 CM_FCLKEN);
501 CM_ICLKEN);
504 CM_ICLKEN);
506 CM_ICLKEN);
508 CM_ICLKEN);
512 CM_AUTOIDLE2);
515 OMAP2_CM_CLKSTCTRL);
517 OMAP2_CM_CLKSTCTRL);
519 OMAP2_CM_CLKSTCTRL);
521 OMAP2_CM_CLKSTCTRL);
523 OMAP2_CM_CLKSTCTRL);
525 OMAP2_CM_CLKSTCTRL);
527 OMAP2_CM_CLKSTCTRL);
529 OMAP2_CM_CLKSTCTRL);
533 CM_AUTOIDLE1);
535 CM_AUTOIDLE2);
537 CM_AUTOIDLE3);
540 CM_AUTOIDLE);
542 CM_AUTOIDLE);
544 CM_AUTOIDLE);
548 OMAP3430_CM_SLEEPDEP);
550 OMAP3430_CM_SLEEPDEP);
552 OMAP3430_CM_SLEEPDEP);
554 OMAP3430_CM_SLEEPDEP);
558 OMAP3_CM_CLKOUT_CTRL_OFFSET);
560 OMAP3_PRM_CLKOUT_CTRL_OFFSET);
562 PM_WKDEP);
564 PM_WKDEP);
566 PM_WKDEP);
568 PM_WKDEP);
570 PM_WKDEP);
574 OMAP3430_PM_MPUGRPSEL1);
576 OMAP3430_PM_IVAGRPSEL1);
578 OMAP3430ES2_PM_MPUGRPSEL3);
580 OMAP3430ES2_PM_IVAGRPSEL3);
582 OMAP3430_PM_MPUGRPSEL);
584 OMAP3430_PM_IVAGRPSEL);
586 OMAP3430_PM_MPUGRPSEL);
588 OMAP3430_PM_IVAGRPSEL);
591 }
592 #endif