release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-omap2/clockdomains.h

   1
   2
   3 /*
   4  * To-Do List
   5  * -> Port the Sleep/Wakeup dependencies for the domains
   6  *    from the Power domain framework
   7  */
   8
   9 #ifndef __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
  10 #define __ARCH_ARM_MACH_OMAP2_CLOCKDOMAINS_H
  11
  12 #include <plat/clockdomain.h>
  13 #include "cm.h"
  14 #include "prm.h"
  15
  16
  17 /* OMAP2/3-common wakeup dependencies */
  18
  19 /*
  20  * 2420/2430 PM_WKDEP_GFX: CORE, MPU, WKUP
  21  * 3430ES1 PM_WKDEP_GFX: adds IVA2, removes CORE
  22  * 3430ES2 PM_WKDEP_SGX: adds IVA2, removes CORE
  23  * These can share data since they will never be present simultaneously
  24  * on the same device.
  25  */
  26 static struct clkdm_dep gfx_sgx_wkdeps[] = {
  27         {
  28                 .clkdm_name = "core_l3_clkdm",
  29                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  30         },
  31         {
  32                 .clkdm_name = "core_l4_clkdm",
  33                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  34         },
  35         {
  36                 .clkdm_name = "iva2_clkdm",
  37                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
  38         },
  39         {
  40                 .clkdm_name = "mpu_clkdm",
  41                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
  42                                             CHIP_IS_OMAP3430)
  43         },
  44         {
  45                 .clkdm_name = "wkup_clkdm",
  46                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX |
  47                                             CHIP_IS_OMAP3430)
  48         },
  49         { NULL },
  50 };
  51
  52
  53 /* 24XX-specific possible dependencies */
  54
  55 #ifdef CONFIG_ARCH_OMAP2
  56
  57 /* Wakeup dependency source arrays */
  58
  59 /* 2420/2430 PM_WKDEP_DSP: CORE, MPU, WKUP */
  60 static struct clkdm_dep dsp_24xx_wkdeps[] = {
  61         {
  62                 .clkdm_name = "core_l3_clkdm",
  63                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  64         },
  65         {
  66                 .clkdm_name = "core_l4_clkdm",
  67                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  68         },
  69         {
  70                 .clkdm_name = "mpu_clkdm",
  71                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  72         },
  73         {
  74                 .clkdm_name = "wkup_clkdm",
  75                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  76         },
  77         { NULL },
  78 };
  79
  80 /*
  81  * 2420 PM_WKDEP_MPU: CORE, DSP, WKUP
  82  * 2430 adds MDM
  83  */
  84 static struct clkdm_dep mpu_24xx_wkdeps[] = {
  85         {
  86                 .clkdm_name = "core_l3_clkdm",
  87                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  88         },
  89         {
  90                 .clkdm_name = "core_l4_clkdm",
  91                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  92         },
  93         {
  94                 .clkdm_name = "dsp_clkdm",
  95                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
  96         },
  97         {
  98                 .clkdm_name = "wkup_clkdm",
  99                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 100         },
 101         {
 102                 .clkdm_name = "mdm_clkdm",
 103                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 104         },
 105         { NULL },
 106 };
 107
 108 /*
 109  * 2420 PM_WKDEP_CORE: DSP, GFX, MPU, WKUP
 110  * 2430 adds MDM
 111  */
 112 static struct clkdm_dep core_24xx_wkdeps[] = {
 113         {
 114                 .clkdm_name = "dsp_clkdm",
 115                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 116         },
 117         {
 118                 .clkdm_name = "gfx_clkdm",
 119                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 120         },
 121         {
 122                 .clkdm_name = "mpu_clkdm",
 123                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 124         },
 125         {
 126                 .clkdm_name = "wkup_clkdm",
 127                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 128         },
 129         {
 130                 .clkdm_name = "mdm_clkdm",
 131                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP2430)
 132         },
 133         { NULL },
 134 };
 135
 136 #endif
 137
 138
 139 /* 2430-specific possible wakeup dependencies */
 140
 141 #ifdef CONFIG_ARCH_OMAP2430
 142
 143 /* 2430 PM_WKDEP_MDM: CORE, MPU, WKUP */
 144 static struct clkdm_dep mdm_2430_wkdeps[] = {
 145         {
 146                 .clkdm_name = "core_l3_clkdm",
 147                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 148         },
 149         {
 150                 .clkdm_name = "core_l4_clkdm",
 151                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 152         },
 153         {
 154                 .clkdm_name = "mpu_clkdm",
 155                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 156         },
 157         {
 158                 .clkdm_name = "wkup_clkdm",
 159                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX)
 160         },
 161         { NULL },
 162 };
 163
 164 #endif /* CONFIG_ARCH_OMAP2430 */
 165
 166
 167 /* OMAP3-specific possible dependencies */
 168
 169 #ifdef CONFIG_ARCH_OMAP3
 170
 171 /* 3430: PM_WKDEP_PER: CORE, IVA2, MPU, WKUP */
 172 static struct clkdm_dep per_wkdeps[] = {
 173         {
 174                 .clkdm_name = "core_l3_clkdm",
 175                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 176         },
 177         {
 178                 .clkdm_name = "core_l4_clkdm",
 179                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 180         },
 181         {
 182                 .clkdm_name = "iva2_clkdm",
 183                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 184         },
 185         {
 186                 .clkdm_name = "mpu_clkdm",
 187                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 188         },
 189         {
 190                 .clkdm_name = "wkup_clkdm",
 191                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 192         },
 193         { NULL },
 194 };
 195
 196 /* 3430ES2: PM_WKDEP_USBHOST: CORE, IVA2, MPU, WKUP */
 197 static struct clkdm_dep usbhost_wkdeps[] = {
 198         {
 199                 .clkdm_name = "core_l3_clkdm",
 200                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 201         },
 202         {
 203                 .clkdm_name = "core_l4_clkdm",
 204                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 205         },
 206         {
 207                 .clkdm_name = "iva2_clkdm",
 208                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 209         },
 210         {
 211                 .clkdm_name = "mpu_clkdm",
 212                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 213         },
 214         {
 215                 .clkdm_name = "wkup_clkdm",
 216                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 217         },
 218         { NULL },
 219 };
 220
 221 /* 3430 PM_WKDEP_MPU: CORE, IVA2, DSS, PER */
 222 static struct clkdm_dep mpu_3xxx_wkdeps[] = {
 223         {
 224                 .clkdm_name = "core_l3_clkdm",
 225                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 226         },
 227         {
 228                 .clkdm_name = "core_l4_clkdm",
 229                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 230         },
 231         {
 232                 .clkdm_name = "iva2_clkdm",
 233                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 234         },
 235         {
 236                 .clkdm_name = "dss_clkdm",
 237                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 238         },
 239         {
 240                 .clkdm_name = "per_clkdm",
 241                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 242         },
 243         { NULL },
 244 };
 245
 246 /* 3430 PM_WKDEP_IVA2: CORE, MPU, WKUP, DSS, PER */
 247 static struct clkdm_dep iva2_wkdeps[] = {
 248         {
 249                 .clkdm_name = "core_l3_clkdm",
 250                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 251         },
 252         {
 253                 .clkdm_name = "core_l4_clkdm",
 254                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 255         },
 256         {
 257                 .clkdm_name = "mpu_clkdm",
 258                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 259         },
 260         {
 261                 .clkdm_name = "wkup_clkdm",
 262                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 263         },
 264         {
 265                 .clkdm_name = "dss_clkdm",
 266                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 267         },
 268         {
 269                 .clkdm_name = "per_clkdm",
 270                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 271         },
 272         { NULL },
 273 };
 274
 275
 276 /* 3430 PM_WKDEP_CAM: IVA2, MPU, WKUP */
 277 static struct clkdm_dep cam_wkdeps[] = {
 278         {
 279                 .clkdm_name = "iva2_clkdm",
 280                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 281         },
 282         {
 283                 .clkdm_name = "mpu_clkdm",
 284                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 285         },
 286         {
 287                 .clkdm_name = "wkup_clkdm",
 288                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 289         },
 290         { NULL },
 291 };
 292
 293 /* 3430 PM_WKDEP_DSS: IVA2, MPU, WKUP */
 294 static struct clkdm_dep dss_wkdeps[] = {
 295         {
 296                 .clkdm_name = "iva2_clkdm",
 297                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 298         },
 299         {
 300                 .clkdm_name = "mpu_clkdm",
 301                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 302         },
 303         {
 304                 .clkdm_name = "wkup_clkdm",
 305                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 306         },
 307         { NULL },
 308 };
 309
 310 /* 3430: PM_WKDEP_NEON: MPU */
 311 static struct clkdm_dep neon_wkdeps[] = {
 312         {
 313                 .clkdm_name = "mpu_clkdm",
 314                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 315         },
 316         { NULL },
 317 };
 318
 319
 320 /* Sleep dependency source arrays for OMAP3-specific clkdms */
 321
 322 /* 3430: CM_SLEEPDEP_DSS: MPU, IVA */
 323 static struct clkdm_dep dss_sleepdeps[] = {
 324         {
 325                 .clkdm_name = "mpu_clkdm",
 326                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 327         },
 328         {
 329                 .clkdm_name = "iva2_clkdm",
 330                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 331         },
 332         { NULL },
 333 };
 334
 335 /* 3430: CM_SLEEPDEP_PER: MPU, IVA */
 336 static struct clkdm_dep per_sleepdeps[] = {
 337         {
 338                 .clkdm_name = "mpu_clkdm",
 339                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 340         },
 341         {
 342                 .clkdm_name = "iva2_clkdm",
 343                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 344         },
 345         { NULL },
 346 };
 347
 348 /* 3430ES2: CM_SLEEPDEP_USBHOST: MPU, IVA */
 349 static struct clkdm_dep usbhost_sleepdeps[] = {
 350         {
 351                 .clkdm_name = "mpu_clkdm",
 352                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 353         },
 354         {
 355                 .clkdm_name = "iva2_clkdm",
 356                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 357         },
 358         { NULL },
 359 };
 360
 361 /* 3430: CM_SLEEPDEP_CAM: MPU */
 362 static struct clkdm_dep cam_sleepdeps[] = {
 363         {
 364                 .clkdm_name = "mpu_clkdm",
 365                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 366         },
 367         { NULL },
 368 };
 369
 370 /*
 371  * 3430ES1: CM_SLEEPDEP_GFX: MPU
 372  * 3430ES2: CM_SLEEPDEP_SGX: MPU
 373  * These can share data since they will never be present simultaneously
 374  * on the same device.
 375  */
 376 static struct clkdm_dep gfx_sgx_sleepdeps[] = {
 377         {
 378                 .clkdm_name = "mpu_clkdm",
 379                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 380         },
 381         { NULL },
 382 };
 383
 384 #endif /* CONFIG_ARCH_OMAP3 */
 385
 386
 387 /*
 388  * OMAP2/3-common clockdomains
 389  *
 390  * Even though the 2420 has a single PRCM module from the
 391  * interconnect's perspective, internally it does appear to have
 392  * separate PRM and CM clockdomains.  The usual test case is
 393  * sys_clkout/sys_clkout2.
 394  */
 395
 396 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 397
 398 /* This is an implicit clockdomain - it is never defined as such in TRM */
 399 static struct clockdomain wkup_clkdm = {
 400         .name           = "wkup_clkdm",
 401         .pwrdm          = { .name = "wkup_pwrdm" },
 402         .dep_bit        = OMAP_EN_WKUP_SHIFT,
 403         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 404 };
 405
 406 static struct clockdomain prm_clkdm = {
 407         .name           = "prm_clkdm",
 408         .pwrdm          = { .name = "wkup_pwrdm" },
 409         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 410 };
 411
 412 static struct clockdomain cm_clkdm = {
 413         .name           = "cm_clkdm",
 414         .pwrdm          = { .name = "core_pwrdm" },
 415         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP24XX | CHIP_IS_OMAP3430),
 416 };
 417
 418 #endif
 419
 420 /*
 421  * 2420-only clockdomains
 422  */
 423
 424 #if defined(CONFIG_ARCH_OMAP2420)
 425
 426 static struct clockdomain mpu_2420_clkdm = {
 427         .name           = "mpu_clkdm",
 428         .pwrdm          = { .name = "mpu_pwrdm" },
 429         .flags          = CLKDM_CAN_HWSUP,
 430         .clkstctrl_reg  = OMAP2420_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
 431         .wkdep_srcs     = mpu_24xx_wkdeps,
 432         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
 433         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 434 };
 435
 436 static struct clockdomain iva1_2420_clkdm = {
 437         .name           = "iva1_clkdm",
 438         .pwrdm          = { .name = "dsp_pwrdm" },
 439         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 440         .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
 441                                                  OMAP2_CM_CLKSTCTRL),
 442         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
 443         .wkdep_srcs     = dsp_24xx_wkdeps,
 444         .clktrctrl_mask = OMAP2420_AUTOSTATE_IVA_MASK,
 445         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 446 };
 447
 448 static struct clockdomain dsp_2420_clkdm = {
 449         .name           = "dsp_clkdm",
 450         .pwrdm          = { .name = "dsp_pwrdm" },
 451         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 452         .clkstctrl_reg  = OMAP2420_CM_REGADDR(OMAP24XX_DSP_MOD,
 453                                                  OMAP2_CM_CLKSTCTRL),
 454         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
 455         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 456 };
 457
 458 static struct clockdomain gfx_2420_clkdm = {
 459         .name           = "gfx_clkdm",
 460         .pwrdm          = { .name = "gfx_pwrdm" },
 461         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 462         .clkstctrl_reg  = OMAP2420_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
 463         .wkdep_srcs     = gfx_sgx_wkdeps,
 464         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
 465         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 466 };
 467
 468 static struct clockdomain core_l3_2420_clkdm = {
 469         .name           = "core_l3_clkdm",
 470         .pwrdm          = { .name = "core_pwrdm" },
 471         .flags          = CLKDM_CAN_HWSUP,
 472         .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 473         .wkdep_srcs     = core_24xx_wkdeps,
 474         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
 475         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 476 };
 477
 478 static struct clockdomain core_l4_2420_clkdm = {
 479         .name           = "core_l4_clkdm",
 480         .pwrdm          = { .name = "core_pwrdm" },
 481         .flags          = CLKDM_CAN_HWSUP,
 482         .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 483         .wkdep_srcs     = core_24xx_wkdeps,
 484         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
 485         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 486 };
 487
 488 static struct clockdomain dss_2420_clkdm = {
 489         .name           = "dss_clkdm",
 490         .pwrdm          = { .name = "core_pwrdm" },
 491         .flags          = CLKDM_CAN_HWSUP,
 492         .clkstctrl_reg  = OMAP2420_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 493         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
 494         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2420),
 495 };
 496
 497 #endif   /* CONFIG_ARCH_OMAP2420 */
 498
 499
 500 /*
 501  * 2430-only clockdomains
 502  */
 503
 504 #if defined(CONFIG_ARCH_OMAP2430)
 505
 506 static struct clockdomain mpu_2430_clkdm = {
 507         .name           = "mpu_clkdm",
 508         .pwrdm          = { .name = "mpu_pwrdm" },
 509         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 510         .clkstctrl_reg  = OMAP2430_CM_REGADDR(MPU_MOD,
 511                                                  OMAP2_CM_CLKSTCTRL),
 512         .wkdep_srcs     = mpu_24xx_wkdeps,
 513         .clktrctrl_mask = OMAP24XX_AUTOSTATE_MPU_MASK,
 514         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 515 };
 516
 517 /* Another case of bit name collisions between several registers: EN_MDM */
 518 static struct clockdomain mdm_clkdm = {
 519         .name           = "mdm_clkdm",
 520         .pwrdm          = { .name = "mdm_pwrdm" },
 521         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 522         .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP2430_MDM_MOD,
 523                                                  OMAP2_CM_CLKSTCTRL),
 524         .dep_bit        = OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT,
 525         .wkdep_srcs     = mdm_2430_wkdeps,
 526         .clktrctrl_mask = OMAP2430_AUTOSTATE_MDM_MASK,
 527         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 528 };
 529
 530 static struct clockdomain dsp_2430_clkdm = {
 531         .name           = "dsp_clkdm",
 532         .pwrdm          = { .name = "dsp_pwrdm" },
 533         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 534         .clkstctrl_reg  = OMAP2430_CM_REGADDR(OMAP24XX_DSP_MOD,
 535                                                  OMAP2_CM_CLKSTCTRL),
 536         .dep_bit        = OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT,
 537         .wkdep_srcs     = dsp_24xx_wkdeps,
 538         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSP_MASK,
 539         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 540 };
 541
 542 static struct clockdomain gfx_2430_clkdm = {
 543         .name           = "gfx_clkdm",
 544         .pwrdm          = { .name = "gfx_pwrdm" },
 545         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 546         .clkstctrl_reg  = OMAP2430_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
 547         .wkdep_srcs     = gfx_sgx_wkdeps,
 548         .clktrctrl_mask = OMAP24XX_AUTOSTATE_GFX_MASK,
 549         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 550 };
 551
 552 static struct clockdomain core_l3_2430_clkdm = {
 553         .name           = "core_l3_clkdm",
 554         .pwrdm          = { .name = "core_pwrdm" },
 555         .flags          = CLKDM_CAN_HWSUP,
 556         .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 557         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
 558         .wkdep_srcs     = core_24xx_wkdeps,
 559         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L3_MASK,
 560         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 561 };
 562
 563 static struct clockdomain core_l4_2430_clkdm = {
 564         .name           = "core_l4_clkdm",
 565         .pwrdm          = { .name = "core_pwrdm" },
 566         .flags          = CLKDM_CAN_HWSUP,
 567         .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 568         .dep_bit        = OMAP24XX_EN_CORE_SHIFT,
 569         .wkdep_srcs     = core_24xx_wkdeps,
 570         .clktrctrl_mask = OMAP24XX_AUTOSTATE_L4_MASK,
 571         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 572 };
 573
 574 static struct clockdomain dss_2430_clkdm = {
 575         .name           = "dss_clkdm",
 576         .pwrdm          = { .name = "core_pwrdm" },
 577         .flags          = CLKDM_CAN_HWSUP,
 578         .clkstctrl_reg  = OMAP2430_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 579         .clktrctrl_mask = OMAP24XX_AUTOSTATE_DSS_MASK,
 580         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP2430),
 581 };
 582
 583 #endif    /* CONFIG_ARCH_OMAP2430 */
 584
 585
 586 /*
 587  * OMAP3 clockdomains
 588  */
 589
 590 #if defined(CONFIG_ARCH_OMAP3)
 591
 592 static struct clockdomain mpu_3xxx_clkdm = {
 593         .name           = "mpu_clkdm",
 594         .pwrdm          = { .name = "mpu_pwrdm" },
 595         .flags          = CLKDM_CAN_HWSUP | CLKDM_CAN_FORCE_WAKEUP,
 596         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(MPU_MOD, OMAP2_CM_CLKSTCTRL),
 597         .dep_bit        = OMAP3430_EN_MPU_SHIFT,
 598         .wkdep_srcs     = mpu_3xxx_wkdeps,
 599         .clktrctrl_mask = OMAP3430_CLKTRCTRL_MPU_MASK,
 600         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 601 };
 602
 603 static struct clockdomain neon_clkdm = {
 604         .name           = "neon_clkdm",
 605         .pwrdm          = { .name = "neon_pwrdm" },
 606         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 607         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_NEON_MOD,
 608                                                  OMAP2_CM_CLKSTCTRL),
 609         .wkdep_srcs     = neon_wkdeps,
 610         .clktrctrl_mask = OMAP3430_CLKTRCTRL_NEON_MASK,
 611         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 612 };
 613
 614 static struct clockdomain iva2_clkdm = {
 615         .name           = "iva2_clkdm",
 616         .pwrdm          = { .name = "iva2_pwrdm" },
 617         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 618         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_IVA2_MOD,
 619                                                  OMAP2_CM_CLKSTCTRL),
 620         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_IVA2_SHIFT,
 621         .wkdep_srcs     = iva2_wkdeps,
 622         .clktrctrl_mask = OMAP3430_CLKTRCTRL_IVA2_MASK,
 623         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 624 };
 625
 626 static struct clockdomain gfx_3430es1_clkdm = {
 627         .name           = "gfx_clkdm",
 628         .pwrdm          = { .name = "gfx_pwrdm" },
 629         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 630         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(GFX_MOD, OMAP2_CM_CLKSTCTRL),
 631         .wkdep_srcs     = gfx_sgx_wkdeps,
 632         .sleepdep_srcs  = gfx_sgx_sleepdeps,
 633         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_GFX_MASK,
 634         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1),
 635 };
 636
 637 static struct clockdomain sgx_clkdm = {
 638         .name           = "sgx_clkdm",
 639         .pwrdm          = { .name = "sgx_pwrdm" },
 640         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 641         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_SGX_MOD,
 642                                                  OMAP2_CM_CLKSTCTRL),
 643         .wkdep_srcs     = gfx_sgx_wkdeps,
 644         .sleepdep_srcs  = gfx_sgx_sleepdeps,
 645         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_SGX_MASK,
 646         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 647 };
 648
 649 /*
 650  * The die-to-die clockdomain was documented in the 34xx ES1 TRM, but
 651  * then that information was removed from the 34xx ES2+ TRM.  It is
 652  * unclear whether the core is still there, but the clockdomain logic
 653  * is there, and must be programmed to an appropriate state if the
 654  * CORE clockdomain is to become inactive.
 655  */
 656 static struct clockdomain d2d_clkdm = {
 657         .name           = "d2d_clkdm",
 658         .pwrdm          = { .name = "core_pwrdm" },
 659         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 660         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 661         .clktrctrl_mask = OMAP3430ES1_CLKTRCTRL_D2D_MASK,
 662         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 663 };
 664
 665 static struct clockdomain core_l3_3xxx_clkdm = {
 666         .name           = "core_l3_clkdm",
 667         .pwrdm          = { .name = "core_pwrdm" },
 668         .flags          = CLKDM_CAN_HWSUP,
 669         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 670         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
 671         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L3_MASK,
 672         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 673 };
 674
 675 static struct clockdomain core_l4_3xxx_clkdm = {
 676         .name           = "core_l4_clkdm",
 677         .pwrdm          = { .name = "core_pwrdm" },
 678         .flags          = CLKDM_CAN_HWSUP,
 679         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(CORE_MOD, OMAP2_CM_CLKSTCTRL),
 680         .dep_bit        = OMAP3430_EN_CORE_SHIFT,
 681         .clktrctrl_mask = OMAP3430_CLKTRCTRL_L4_MASK,
 682         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 683 };
 684
 685 /* Another case of bit name collisions between several registers: EN_DSS */
 686 static struct clockdomain dss_3xxx_clkdm = {
 687         .name           = "dss_clkdm",
 688         .pwrdm          = { .name = "dss_pwrdm" },
 689         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 690         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_DSS_MOD,
 691                                                  OMAP2_CM_CLKSTCTRL),
 692         .dep_bit        = OMAP3430_PM_WKDEP_MPU_EN_DSS_SHIFT,
 693         .wkdep_srcs     = dss_wkdeps,
 694         .sleepdep_srcs  = dss_sleepdeps,
 695         .clktrctrl_mask = OMAP3430_CLKTRCTRL_DSS_MASK,
 696         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 697 };
 698
 699 static struct clockdomain cam_clkdm = {
 700         .name           = "cam_clkdm",
 701         .pwrdm          = { .name = "cam_pwrdm" },
 702         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 703         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_CAM_MOD,
 704                                                  OMAP2_CM_CLKSTCTRL),
 705         .wkdep_srcs     = cam_wkdeps,
 706         .sleepdep_srcs  = cam_sleepdeps,
 707         .clktrctrl_mask = OMAP3430_CLKTRCTRL_CAM_MASK,
 708         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 709 };
 710
 711 static struct clockdomain usbhost_clkdm = {
 712         .name           = "usbhost_clkdm",
 713         .pwrdm          = { .name = "usbhost_pwrdm" },
 714         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 715         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430ES2_USBHOST_MOD,
 716                                                  OMAP2_CM_CLKSTCTRL),
 717         .wkdep_srcs     = usbhost_wkdeps,
 718         .sleepdep_srcs  = usbhost_sleepdeps,
 719         .clktrctrl_mask = OMAP3430ES2_CLKTRCTRL_USBHOST_MASK,
 720         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 721 };
 722
 723 static struct clockdomain per_clkdm = {
 724         .name           = "per_clkdm",
 725         .pwrdm          = { .name = "per_pwrdm" },
 726         .flags          = CLKDM_CAN_HWSUP_SWSUP,
 727         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_PER_MOD,
 728                                                  OMAP2_CM_CLKSTCTRL),
 729         .dep_bit        = OMAP3430_EN_PER_SHIFT,
 730         .wkdep_srcs     = per_wkdeps,
 731         .sleepdep_srcs  = per_sleepdeps,
 732         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 733         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 734 };
 735
 736 /*
 737  * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
 738  * switched of even if sdti is in use
 739  */
 740 static struct clockdomain emu_clkdm = {
 741         .name           = "emu_clkdm",
 742         .pwrdm          = { .name = "emu_pwrdm" },
 743         .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
 744         .clkstctrl_reg  = OMAP34XX_CM_REGADDR(OMAP3430_EMU_MOD,
 745                                                  OMAP2_CM_CLKSTCTRL),
 746         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 747         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 748 };
 749
 750 static struct clockdomain dpll1_clkdm = {
 751         .name           = "dpll1_clkdm",
 752         .pwrdm          = { .name = "dpll1_pwrdm" },
 753         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 754 };
 755
 756 static struct clockdomain dpll2_clkdm = {
 757         .name           = "dpll2_clkdm",
 758         .pwrdm          = { .name = "dpll2_pwrdm" },
 759         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 760 };
 761
 762 static struct clockdomain dpll3_clkdm = {
 763         .name           = "dpll3_clkdm",
 764         .pwrdm          = { .name = "dpll3_pwrdm" },
 765         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 766 };
 767
 768 static struct clockdomain dpll4_clkdm = {
 769         .name           = "dpll4_clkdm",
 770         .pwrdm          = { .name = "dpll4_pwrdm" },
 771         .omap_chip      = OMAP_CHIP_INIT(CHIP_IS_OMAP3430),
 772 };
 773
 774 static struct clockdomain dpll5_clkdm = {
 775         .name           = "dpll5_clkdm",
 776         .pwrdm          = { .name = "dpll5_pwrdm" },
 777         .omap_chip      = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES2),
 778 };
 779
 780 #endif   /* CONFIG_ARCH_OMAP3 */
 781
 782 #include "clockdomains44xx.h"
 783
 784 /*
 785  * Clockdomain hwsup dependencies (OMAP3 only)
 786  */
 787
 788 static struct clkdm_autodep clkdm_autodeps[] = {
 789         {
 790                 .clkdm     = { .name = "mpu_clkdm" },
 791                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 792         },
 793         {
 794                 .clkdm     = { .name = "iva2_clkdm" },
 795                 .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430)
 796         },
 797         {
 798                 .clkdm     = { .name = NULL },
 799         }
 800 };
 801
 802 /*
 803  * List of clockdomain pointers per platform
 804  */
 805
 806 static struct clockdomain *clockdomains_omap[] = {
 807
 808 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
 809         &wkup_clkdm,
 810         &cm_clkdm,
 811         &prm_clkdm,
 812 #endif
 813
 814 #ifdef CONFIG_ARCH_OMAP2420
 815         &mpu_2420_clkdm,
 816         &iva1_2420_clkdm,
 817         &dsp_2420_clkdm,
 818         &gfx_2420_clkdm,
 819         &core_l3_2420_clkdm,
 820         &core_l4_2420_clkdm,
 821         &dss_2420_clkdm,
 822 #endif
 823
 824 #ifdef CONFIG_ARCH_OMAP2430
 825         &mpu_2430_clkdm,
 826         &mdm_clkdm,
 827         &dsp_2430_clkdm,
 828         &gfx_2430_clkdm,
 829         &core_l3_2430_clkdm,
 830         &core_l4_2430_clkdm,
 831         &dss_2430_clkdm,
 832 #endif
 833
 834 #ifdef CONFIG_ARCH_OMAP3
 835         &mpu_3xxx_clkdm,
 836         &neon_clkdm,
 837         &iva2_clkdm,
 838         &gfx_3430es1_clkdm,
 839         &sgx_clkdm,
 840         &d2d_clkdm,
 841         &core_l3_3xxx_clkdm,
 842         &core_l4_3xxx_clkdm,
 843         &dss_3xxx_clkdm,
 844         &cam_clkdm,
 845         &usbhost_clkdm,
 846         &per_clkdm,
 847         &emu_clkdm,
 848         &dpll1_clkdm,
 849         &dpll2_clkdm,
 850         &dpll3_clkdm,
 851         &dpll4_clkdm,
 852         &dpll5_clkdm,
 853 #endif
 854
 855 #ifdef CONFIG_ARCH_OMAP4
 856         &l4_cefuse_44xx_clkdm,
 857         &l4_cfg_44xx_clkdm,
 858         &tesla_44xx_clkdm,
 859         &l3_gfx_44xx_clkdm,
 860         &ivahd_44xx_clkdm,
 861         &l4_secure_44xx_clkdm,
 862         &l4_per_44xx_clkdm,
 863         &abe_44xx_clkdm,
 864         &l3_instr_44xx_clkdm,
 865         &l3_init_44xx_clkdm,
 866         &mpuss_44xx_clkdm,
 867         &mpu0_44xx_clkdm,
 868         &mpu1_44xx_clkdm,
 869         &l3_emif_44xx_clkdm,
 870         &l4_ao_44xx_clkdm,
 871         &ducati_44xx_clkdm,
 872         &l3_2_44xx_clkdm,
 873         &l3_1_44xx_clkdm,
 874         &l3_d2d_44xx_clkdm,
 875         &iss_44xx_clkdm,
 876         &l3_dss_44xx_clkdm,
 877         &l4_wkup_44xx_clkdm,
 878         &emu_sys_44xx_clkdm,
 879         &l3_dma_44xx_clkdm,
 880 #endif
 881
 882         NULL,
 883 };
 884
 885 #endif