2 * OMAP34xx M2 divider clock code
4 * Copyright (C) 2007-2008 Texas Instruments, Inc.
5 * Copyright (C) 2007-2010 Nokia Corporation
10 * Parts of this code are based on code written by
11 * Richard Woodruff, Tony Lindgren, Tuukka Tikkanen, Karthik Dasu
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
19 #include <linux/kernel.h>
20 #include <linux/errno.h>
21 #include <linux/clk.h>
24 #include <plat/clock.h>
25 #include <plat/sram.h>
26 #include <plat/sdrc.h>
29 #include "clock3xxx.h"
30 #include "clock34xx.h"
33 #define CYCLES_PER_MHZ 1000000
36 * CORE DPLL (DPLL3) M2 divider rate programming functions
38 * These call into SRAM code to do the actual CM writes, since the SDRAM
39 * is clocked from DPLL3.
43 * omap3_core_dpll_m2_set_rate - set CORE DPLL M2 divider
44 * @clk: struct clk * of DPLL to set
45 * @rate: rounded target rate
47 * Program the DPLL M2 divider with the rounded target rate. Returns
48 * -EINVAL upon error, or 0 upon success.
50 int omap3_core_dpll_m2_set_rate(struct clk
*clk
, unsigned long rate
)
55 unsigned long validrate
, sdrcrate
, _mpurate
;
56 struct omap_sdrc_params
*sdrc_cs0
;
57 struct omap_sdrc_params
*sdrc_cs1
;
63 validrate
= omap2_clksel_round_rate_div(clk
, rate
, &new_div
);
64 if (validrate
!= rate
)
67 sdrcrate
= sdrc_ick_p
->rate
;
69 sdrcrate
<<= ((rate
/ clk
->rate
) >> 1);
71 sdrcrate
>>= ((clk
->rate
/ rate
) >> 1);
73 ret
= omap2_sdrc_get_params(sdrcrate
, &sdrc_cs0
, &sdrc_cs1
);
77 if (sdrcrate
< MIN_SDRC_DLL_LOCK_FREQ
) {
78 pr_debug("clock: will unlock SDRC DLL\n");
82 _mpurate
= arm_fck_p
->rate
/ CYCLES_PER_MHZ
;
83 c
= (_mpurate
<< SDRC_MPURATE_SCALE
) >> SDRC_MPURATE_BASE_SHIFT
;
84 c
+= 1; /* for safety */
85 c
*= SDRC_MPURATE_LOOPS
;
86 c
>>= SDRC_MPURATE_SCALE
;
90 pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk
->rate
,
92 pr_debug("clock: SDRC CS0 timing params used:"
93 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
94 sdrc_cs0
->rfr_ctrl
, sdrc_cs0
->actim_ctrla
,
95 sdrc_cs0
->actim_ctrlb
, sdrc_cs0
->mr
);
97 pr_debug("clock: SDRC CS1 timing params used: "
98 " RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
99 sdrc_cs1
->rfr_ctrl
, sdrc_cs1
->actim_ctrla
,
100 sdrc_cs1
->actim_ctrlb
, sdrc_cs1
->mr
);
103 omap3_configure_core_dpll(
104 new_div
, unlock_dll
, c
, rate
> clk
->rate
,
105 sdrc_cs0
->rfr_ctrl
, sdrc_cs0
->actim_ctrla
,
106 sdrc_cs0
->actim_ctrlb
, sdrc_cs0
->mr
,
107 sdrc_cs1
->rfr_ctrl
, sdrc_cs1
->actim_ctrla
,
108 sdrc_cs1
->actim_ctrlb
, sdrc_cs1
->mr
);
110 omap3_configure_core_dpll(
111 new_div
, unlock_dll
, c
, rate
> clk
->rate
,
112 sdrc_cs0
->rfr_ctrl
, sdrc_cs0
->actim_ctrla
,
113 sdrc_cs0
->actim_ctrlb
, sdrc_cs0
->mr
,