release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-kirkwood/mpp.h

   1 /*
   2  * linux/arch/arm/mach-kirkwood/mpp.h -- Multi Purpose Pins
   3  *
   4  * Copyright 2009: Marvell Technology Group Ltd.
   5  *
   6  * This file is licensed under the terms of the GNU General Public
   7  * License version 2.  This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11 #ifndef __KIRKWOOD_MPP_H
  12 #define __KIRKWOOD_MPP_H
  13
  14 #define MPP(_num, _sel, _in, _out, _F6180, _F6190, _F6192, _F6281, _F6282) ( \
  15         /* MPP number */                ((_num) & 0xff) | \
  16         /* MPP select value */          (((_sel) & 0xf) << 8) | \
  17         /* may be input signal */       ((!!(_in)) << 12) | \
  18         /* may be output signal */      ((!!(_out)) << 13) | \
  19         /* available on F6180 */        ((!!(_F6180)) << 14) | \
  20         /* available on F6190 */        ((!!(_F6190)) << 15) | \
  21         /* available on F6192 */        ((!!(_F6192)) << 16) | \
  22         /* available on F6281 */        ((!!(_F6281)) << 17) | \
  23         /* available on F6282 */        ((!!(_F6282)) << 18))
  24
  25 #define MPP_NUM(x)      ((x) & 0xff)
  26 #define MPP_SEL(x)      (((x) >> 8) & 0xf)
  27
  28                                 /*   num sel  i  o  6180 6190 6192 6281 6282 */
  29
  30 #define MPP_INPUT_MASK          MPP(  0, 0x0, 1, 0, 0,   0,   0,   0,   0 )
  31 #define MPP_OUTPUT_MASK         MPP(  0, 0x0, 0, 1, 0,   0,   0,   0,   0 )
  32
  33 #define MPP_F6180_MASK          MPP(  0, 0x0, 0, 0, 1,   0,   0,   0,   0 )
  34 #define MPP_F6190_MASK          MPP(  0, 0x0, 0, 0, 0,   1,   0,   0,   0 )
  35 #define MPP_F6192_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   1,   0,   0 )
  36 #define MPP_F6281_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   1,   0 )
  37 #define MPP_F6282_MASK          MPP(  0, 0x0, 0, 0, 0,   0,   0,   0,   1 )
  38
  39 #define MPP0_GPIO               MPP(  0, 0x0, 1, 1, 1,   1,   1,   1,   1 )
  40 #define MPP0_NF_IO2             MPP(  0, 0x1, 1, 1, 1,   1,   1,   1,   1 )
  41 #define MPP0_SPI_SCn            MPP(  0, 0x2, 0, 1, 1,   1,   1,   1,   1 )
  42
  43 #define MPP1_GPO                MPP(  1, 0x0, 0, 1, 1,   1,   1,   1,   1 )
  44 #define MPP1_NF_IO3             MPP(  1, 0x1, 1, 1, 1,   1,   1,   1,   1 )
  45 #define MPP1_SPI_MOSI           MPP(  1, 0x2, 0, 1, 1,   1,   1,   1,   1 )
  46
  47 #define MPP2_GPO                MPP(  2, 0x0, 0, 1, 1,   1,   1,   1,   1 )
  48 #define MPP2_NF_IO4             MPP(  2, 0x1, 1, 1, 1,   1,   1,   1,   1 )
  49 #define MPP2_SPI_SCK            MPP(  2, 0x2, 0, 1, 1,   1,   1,   1,   1 )
  50
  51 #define MPP3_GPO                MPP(  3, 0x0, 0, 1, 1,   1,   1,   1,   1 )
  52 #define MPP3_NF_IO5             MPP(  3, 0x1, 1, 1, 1,   1,   1,   1,   1 )
  53 #define MPP3_SPI_MISO           MPP(  3, 0x2, 1, 0, 1,   1,   1,   1,   1 )
  54
  55 #define MPP4_GPIO               MPP(  4, 0x0, 1, 1, 1,   1,   1,   1,   1 )
  56 #define MPP4_NF_IO6             MPP(  4, 0x1, 1, 1, 1,   1,   1,   1,   1 )
  57 #define MPP4_UART0_RXD          MPP(  4, 0x2, 1, 0, 1,   1,   1,   1,   1 )
  58 #define MPP4_SATA1_ACTn         MPP(  4, 0x5, 0, 1, 0,   0,   1,   1,   1 )
  59 #define MPP4_LCD_VGA_HSYNC      MPP(  4, 0xb, 0, 0, 0,   0,   0,   0,   1 )
  60 #define MPP4_PTP_CLK            MPP(  4, 0xd, 1, 0, 1,   1,   1,   1,   0 )
  61
  62 #define MPP5_GPO                MPP(  5, 0x0, 0, 1, 1,   1,   1,   1,   1 )
  63 #define MPP5_NF_IO7             MPP(  5, 0x1, 1, 1, 1,   1,   1,   1,   1 )
  64 #define MPP5_UART0_TXD          MPP(  5, 0x2, 0, 1, 1,   1,   1,   1,   1 )
  65 #define MPP5_PTP_TRIG_GEN       MPP(  5, 0x4, 0, 1, 1,   1,   1,   1,   0 )
  66 #define MPP5_SATA0_ACTn         MPP(  5, 0x5, 0, 1, 0,   1,   1,   1,   1 )
  67 #define MPP5_LCD_VGA_VSYNC      MPP(  5, 0xb, 0, 0, 0,   0,   0,   0,   1 )
  68
  69 #define MPP6_SYSRST_OUTn        MPP(  6, 0x1, 0, 1, 1,   1,   1,   1,   1 )
  70 #define MPP6_SPI_MOSI           MPP(  6, 0x2, 0, 1, 1,   1,   1,   1,   1 )
  71 #define MPP6_PTP_TRIG_GEN       MPP(  6, 0x3, 0, 1, 1,   1,   1,   1,   0 )
  72
  73 #define MPP7_GPO                MPP(  7, 0x0, 0, 1, 1,   1,   1,   1,   1 )
  74 #define MPP7_PEX_RST_OUTn       MPP(  7, 0x1, 0, 1, 1,   1,   1,   1,   0 )
  75 #define MPP7_SPI_SCn            MPP(  7, 0x2, 0, 1, 1,   1,   1,   1,   1 )
  76 #define MPP7_PTP_TRIG_GEN       MPP(  7, 0x3, 0, 1, 1,   1,   1,   1,   0 )
  77 #define MPP7_LCD_PWM            MPP(  7, 0xb, 0, 1, 0,   0,   0,   0,   1 )
  78
  79 #define MPP8_GPIO               MPP(  8, 0x0, 1, 1, 1,   1,   1,   1,   1 )
  80 #define MPP8_TW0_SDA            MPP(  8, 0x1, 1, 1, 1,   1,   1,   1,   1 )
  81 #define MPP8_UART0_RTS          MPP(  8, 0x2, 0, 1, 1,   1,   1,   1,   1 )
  82 #define MPP8_UART1_RTS          MPP(  8, 0x3, 0, 1, 1,   1,   1,   1,   1 )
  83 #define MPP8_MII0_RXERR         MPP(  8, 0x4, 1, 0, 0,   1,   1,   1,   1 )
  84 #define MPP8_SATA1_PRESENTn     MPP(  8, 0x5, 0, 1, 0,   0,   1,   1,   1 )
  85 #define MPP8_PTP_CLK            MPP(  8, 0xc, 1, 0, 1,   1,   1,   1,   0 )
  86 #define MPP8_MII0_COL           MPP(  8, 0xd, 1, 0, 1,   1,   1,   1,   1 )
  87
  88 #define MPP9_GPIO               MPP(  9, 0x0, 1, 1, 1,   1,   1,   1,   1 )
  89 #define MPP9_TW0_SCK            MPP(  9, 0x1, 1, 1, 1,   1,   1,   1,   1 )
  90 #define MPP9_UART0_CTS          MPP(  9, 0x2, 1, 0, 1,   1,   1,   1,   1 )
  91 #define MPP9_UART1_CTS          MPP(  9, 0x3, 1, 0, 1,   1,   1,   1,   1 )
  92 #define MPP9_SATA0_PRESENTn     MPP(  9, 0x5, 0, 1, 0,   1,   1,   1,   1 )
  93 #define MPP9_PTP_EVENT_REQ      MPP(  9, 0xc, 1, 0, 1,   1,   1,   1,   0 )
  94 #define MPP9_MII0_CRS           MPP(  9, 0xd, 1, 0, 1,   1,   1,   1,   1 )
  95
  96 #define MPP10_GPO               MPP( 10, 0x0, 0, 1, 1,   1,   1,   1,   1 )
  97 #define MPP10_SPI_SCK           MPP( 10, 0x2, 0, 1, 1,   1,   1,   1,   1 )
  98 #define MPP10_UART0_TXD         MPP( 10, 0X3, 0, 1, 1,   1,   1,   1,   1 )
  99 #define MPP10_SATA1_ACTn        MPP( 10, 0x5, 0, 1, 0,   0,   1,   1,   1 )
 100 #define MPP10_PTP_TRIG_GEN      MPP( 10, 0xc, 0, 1, 1,   1,   1,   1,   0 )
 101
 102 #define MPP11_GPIO              MPP( 11, 0x0, 1, 1, 1,   1,   1,   1,   1 )
 103 #define MPP11_SPI_MISO          MPP( 11, 0x2, 1, 0, 1,   1,   1,   1,   1 )
 104 #define MPP11_UART0_RXD         MPP( 11, 0x3, 1, 0, 1,   1,   1,   1,   1 )
 105 #define MPP11_PTP_EVENT_REQ     MPP( 11, 0x4, 1, 0, 1,   1,   1,   1,   0 )
 106 #define MPP11_PTP_TRIG_GEN      MPP( 11, 0xc, 0, 1, 1,   1,   1,   1,   0 )
 107 #define MPP11_PTP_CLK           MPP( 11, 0xd, 1, 0, 1,   1,   1,   1,   0 )
 108 #define MPP11_SATA0_ACTn        MPP( 11, 0x5, 0, 1, 0,   1,   1,   1,   1 )
 109
 110 #define MPP12_GPO               MPP( 12, 0x0, 0, 1, 1,   1,   1,   1,   1 )
 111 #define MPP12_SD_CLK            MPP( 12, 0x1, 0, 1, 1,   1,   1,   1,   1 )
 112 #define MPP12_AU_SPDIF0         MPP( 12, 0xa, 0, 1, 0,   0,   0,   0,   1 )
 113 #define MPP12_SPI_MOSI          MPP( 12, 0xb, 0, 1, 0,   0,   0,   0,   1 )
 114 #define MPP12_TW1_SDA           MPP( 12, 0xd, 1, 0, 0,   0,   0,   0,   1 )
 115
 116 #define MPP13_GPIO              MPP( 13, 0x0, 1, 1, 1,   1,   1,   1,   1 )
 117 #define MPP13_SD_CMD            MPP( 13, 0x1, 1, 1, 1,   1,   1,   1,   1 )
 118 #define MPP13_UART1_TXD         MPP( 13, 0x3, 0, 1, 1,   1,   1,   1,   1 )
 119 #define MPP13_AU_SPDIFRMCLK     MPP( 13, 0xa, 0, 1, 0,   0,   0,   0,   1 )
 120 #define MPP13_LCDPWM            MPP( 13, 0xb, 0, 1, 0,   0,   0,   0,   1 )
 121
 122 #define MPP14_GPIO              MPP( 14, 0x0, 1, 1, 1,   1,   1,   1,   1 )
 123 #define MPP14_SD_D0             MPP( 14, 0x1, 1, 1, 1,   1,   1,   1,   1 )
 124 #define MPP14_UART1_RXD         MPP( 14, 0x3, 1, 0, 1,   1,   1,   1,   1 )
 125 #define MPP14_SATA1_PRESENTn    MPP( 14, 0x4, 0, 1, 0,   0,   1,   1,   1 )
 126 #define MPP14_AU_SPDIFI         MPP( 14, 0xa, 1, 0, 0,   0,   0,   0,   1 )
 127 #define MPP14_AU_I2SDI          MPP( 14, 0xb, 1, 0, 0,   0,   0,   0,   1 )
 128 #define MPP14_MII0_COL          MPP( 14, 0xd, 1, 0, 1,   1,   1,   1,   1 )
 129
 130 #define MPP15_GPIO              MPP( 15, 0x0, 1, 1, 1,   1,   1,   1,   1 )
 131 #define MPP15_SD_D1             MPP( 15, 0x1, 1, 1, 1,   1,   1,   1,   1 )
 132 #define MPP15_UART0_RTS         MPP( 15, 0x2, 0, 1, 1,   1,   1,   1,   1 )
 133 #define MPP15_UART1_TXD         MPP( 15, 0x3, 0, 1, 1,   1,   1,   1,   1 )
 134 #define MPP15_SATA0_ACTn        MPP( 15, 0x4, 0, 1, 0,   1,   1,   1,   1 )
 135 #define MPP15_SPI_CSn           MPP( 15, 0xb, 0, 1, 0,   0,   0,   0,   1 )
 136
 137 #define MPP16_GPIO              MPP( 16, 0x0, 1, 1, 1,   1,   1,   1,   1 )
 138 #define MPP16_SD_D2             MPP( 16, 0x1, 1, 1, 1,   1,   1,   1,   1 )
 139 #define MPP16_UART0_CTS         MPP( 16, 0x2, 1, 0, 1,   1,   1,   1,   1 )
 140 #define MPP16_UART1_RXD         MPP( 16, 0x3, 1, 0, 1,   1,   1,   1,   1 )
 141 #define MPP16_SATA1_ACTn        MPP( 16, 0x4, 0, 1, 0,   0,   1,   1,   1 )
 142 #define MPP16_LCD_EXT_REF_CLK   MPP( 16, 0xb, 1, 0, 0,   0,   0,   0,   1 )
 143 #define MPP16_MII0_CRS          MPP( 16, 0xd, 1, 0, 1,   1,   1,   1,   1 )
 144
 145 #define MPP17_GPIO              MPP( 17, 0x0, 1, 1, 1,   1,   1,   1,   1 )
 146 #define MPP17_SD_D3             MPP( 17, 0x1, 1, 1, 1,   1,   1,   1,   1 )
 147 #define MPP17_SATA0_PRESENTn    MPP( 17, 0x4, 0, 1, 0,   1,   1,   1,   1 )
 148 #define MPP17_SATA1_ACTn        MPP( 17, 0xa, 0, 1, 0,   0,   0,   0,   1 )
 149 #define MPP17_TW1_SCK           MPP( 17, 0xd, 1, 1, 0,   0,   0,   0,   1 )
 150
 151 #define MPP18_GPO               MPP( 18, 0x0, 0, 1, 1,   1,   1,   1,   1 )
 152 #define MPP18_NF_IO0            MPP( 18, 0x1, 1, 1, 1,   1,   1,   1,   1 )
 153 #define MPP18_PEX0_CLKREQ       MPP( 18, 0x2, 0, 1, 0,   0,   0,   0,   1 )
 154
 155 #define MPP19_GPO               MPP( 19, 0x0, 0, 1, 1,   1,   1,   1,   1 )
 156 #define MPP19_NF_IO1            MPP( 19, 0x1, 1, 1, 1,   1,   1,   1,   1 )
 157
 158 #define MPP20_GPIO              MPP( 20, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 159 #define MPP20_TSMP0             MPP( 20, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 160 #define MPP20_TDM_CH0_TX_QL     MPP( 20, 0x2, 0, 1, 0,   0,   1,   1,   1 )
 161 #define MPP20_GE1_TXD0          MPP( 20, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 162 #define MPP20_AU_SPDIFI         MPP( 20, 0x4, 1, 0, 0,   0,   1,   1,   1 )
 163 #define MPP20_SATA1_ACTn        MPP( 20, 0x5, 0, 1, 0,   0,   1,   1,   1 )
 164 #define MPP20_LCD_D0            MPP( 20, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 165
 166 #define MPP21_GPIO              MPP( 21, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 167 #define MPP21_TSMP1             MPP( 21, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 168 #define MPP21_TDM_CH0_RX_QL     MPP( 21, 0x2, 0, 1, 0,   0,   1,   1,   1 )
 169 #define MPP21_GE1_TXD1          MPP( 21, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 170 #define MPP21_AU_SPDIFO         MPP( 21, 0x4, 0, 1, 0,   0,   1,   1,   1 )
 171 #define MPP21_SATA0_ACTn        MPP( 21, 0x5, 0, 1, 0,   1,   1,   1,   1 )
 172 #define MPP21_LCD_D1            MPP( 21, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 173
 174 #define MPP22_GPIO              MPP( 22, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 175 #define MPP22_TSMP2             MPP( 22, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 176 #define MPP22_TDM_CH2_TX_QL     MPP( 22, 0x2, 0, 1, 0,   0,   1,   1,   1 )
 177 #define MPP22_GE1_TXD2          MPP( 22, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 178 #define MPP22_AU_SPDIFRMKCLK    MPP( 22, 0x4, 0, 1, 0,   0,   1,   1,   1 )
 179 #define MPP22_SATA1_PRESENTn    MPP( 22, 0x5, 0, 1, 0,   0,   1,   1,   1 )
 180 #define MPP22_LCD_D2            MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 181
 182 #define MPP23_GPIO              MPP( 23, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 183 #define MPP23_TSMP3             MPP( 23, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 184 #define MPP23_TDM_CH2_RX_QL     MPP( 23, 0x2, 1, 0, 0,   0,   1,   1,   1 )
 185 #define MPP23_GE1_TXD3          MPP( 23, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 186 #define MPP23_AU_I2SBCLK        MPP( 23, 0x4, 0, 1, 0,   0,   1,   1,   1 )
 187 #define MPP23_SATA0_PRESENTn    MPP( 23, 0x5, 0, 1, 0,   1,   1,   1,   1 )
 188 #define MPP23_LCD_D3            MPP( 23, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 189
 190 #define MPP24_GPIO              MPP( 24, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 191 #define MPP24_TSMP4             MPP( 24, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 192 #define MPP24_TDM_SPI_CS0       MPP( 24, 0x2, 0, 1, 0,   0,   1,   1,   1 )
 193 #define MPP24_GE1_RXD0          MPP( 24, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 194 #define MPP24_AU_I2SDO          MPP( 24, 0x4, 0, 1, 0,   0,   1,   1,   1 )
 195 #define MPP24_LCD_D4            MPP( 24, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 196
 197 #define MPP25_GPIO              MPP( 25, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 198 #define MPP25_TSMP5             MPP( 25, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 199 #define MPP25_TDM_SPI_SCK       MPP( 25, 0x2, 0, 1, 0,   0,   1,   1,   1 )
 200 #define MPP25_GE1_RXD1          MPP( 25, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 201 #define MPP25_AU_I2SLRCLK       MPP( 25, 0x4, 0, 1, 0,   0,   1,   1,   1 )
 202 #define MPP25_LCD_D5            MPP( 25, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 203
 204 #define MPP26_GPIO              MPP( 26, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 205 #define MPP26_TSMP6             MPP( 26, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 206 #define MPP26_TDM_SPI_MISO      MPP( 26, 0x2, 1, 0, 0,   0,   1,   1,   1 )
 207 #define MPP26_GE1_RXD2          MPP( 26, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 208 #define MPP26_AU_I2SMCLK        MPP( 26, 0x4, 0, 1, 0,   0,   1,   1,   1 )
 209 #define MPP26_LCD_D6            MPP( 26, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 210
 211 #define MPP27_GPIO              MPP( 27, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 212 #define MPP27_TSMP7             MPP( 27, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 213 #define MPP27_TDM_SPI_MOSI      MPP( 27, 0x2, 0, 1, 0,   0,   1,   1,   1 )
 214 #define MPP27_GE1_RXD3          MPP( 27, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 215 #define MPP27_AU_I2SDI          MPP( 27, 0x4, 1, 0, 0,   0,   1,   1,   1 )
 216 #define MPP27_LCD_D7            MPP( 27, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 217
 218 #define MPP28_GPIO              MPP( 28, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 219 #define MPP28_TSMP8             MPP( 28, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 220 #define MPP28_TDM_CODEC_INTn    MPP( 28, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 221 #define MPP28_GE1_COL           MPP( 28, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 222 #define MPP28_AU_EXTCLK         MPP( 28, 0x4, 1, 0, 0,   0,   1,   1,   1 )
 223 #define MPP28_LCD_D8            MPP( 28, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 224
 225 #define MPP29_GPIO              MPP( 29, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 226 #define MPP29_TSMP9             MPP( 29, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 227 #define MPP29_TDM_CODEC_RSTn    MPP( 29, 0x2, 0, 0, 0,   0,   1,   1,   1 )
 228 #define MPP29_GE1_TCLK          MPP( 29, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 229 #define MPP29_LCD_D9            MPP( 29, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 230
 231 #define MPP30_GPIO              MPP( 30, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 232 #define MPP30_TSMP10            MPP( 30, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 233 #define MPP30_TDM_PCLK          MPP( 30, 0x2, 1, 1, 0,   0,   1,   1,   1 )
 234 #define MPP30_GE1_RXCTL         MPP( 30, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 235 #define MPP30_LCD_D10           MPP( 30, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 236
 237 #define MPP31_GPIO              MPP( 31, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 238 #define MPP31_TSMP11            MPP( 31, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 239 #define MPP31_TDM_FS            MPP( 31, 0x2, 1, 1, 0,   0,   1,   1,   1 )
 240 #define MPP31_GE1_RXCLK         MPP( 31, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 241 #define MPP31_LCD_D11           MPP( 31, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 242
 243 #define MPP32_GPIO              MPP( 32, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 244 #define MPP32_TSMP12            MPP( 32, 0x1, 1, 1, 0,   0,   1,   1,   1 )
 245 #define MPP32_TDM_DRX           MPP( 32, 0x2, 1, 0, 0,   0,   1,   1,   1 )
 246 #define MPP32_GE1_TCLKOUT       MPP( 32, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 247 #define MPP32_LCD_D12           MPP( 32, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 248
 249 #define MPP33_GPO               MPP( 33, 0x0, 0, 1, 0,   1,   1,   1,   1 )
 250 #define MPP33_TDM_DTX           MPP( 33, 0x2, 0, 1, 0,   0,   1,   1,   1 )
 251 #define MPP33_GE1_TXCTL         MPP( 33, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 252 #define MPP33_LCD_D13           MPP( 33, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 253
 254 #define MPP34_GPIO              MPP( 34, 0x0, 1, 1, 0,   1,   1,   1,   1 )
 255 #define MPP34_TDM_SPI_CS1       MPP( 34, 0x2, 0, 1, 0,   0,   1,   1,   1 )
 256 #define MPP34_GE1_TXEN          MPP( 34, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 257 #define MPP34_SATA1_ACTn        MPP( 34, 0x5, 0, 1, 0,   0,   0,   1,   1 )
 258 #define MPP34_LCD_D14           MPP( 34, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 259
 260 #define MPP35_GPIO              MPP( 35, 0x0, 1, 1, 1,   1,   1,   1,   1 )
 261 #define MPP35_TDM_CH0_TX_QL     MPP( 35, 0x2, 0, 1, 0,   0,   1,   1,   1 )
 262 #define MPP35_GE1_RXERR         MPP( 35, 0x3, 0, 0, 0,   1,   1,   1,   1 )
 263 #define MPP35_SATA0_ACTn        MPP( 35, 0x5, 0, 1, 0,   1,   1,   1,   1 )
 264 #define MPP35_LCD_D15           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 265 #define MPP35_MII0_RXERR        MPP( 35, 0xc, 1, 0, 1,   1,   1,   1,   1 )
 266
 267 #define MPP36_GPIO              MPP( 36, 0x0, 1, 1, 1,   0,   0,   1,   1 )
 268 #define MPP36_TSMP0             MPP( 36, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 269 #define MPP36_TDM_SPI_CS1       MPP( 36, 0x2, 0, 1, 0,   0,   0,   1,   1 )
 270 #define MPP36_AU_SPDIFI         MPP( 36, 0x4, 1, 0, 1,   0,   0,   1,   1 )
 271 #define MPP36_TW1_SDA           MPP( 36, 0xb, 1, 1, 0,   0,   0,   0,   1 )
 272
 273 #define MPP37_GPIO              MPP( 37, 0x0, 1, 1, 1,   0,   0,   1,   1 )
 274 #define MPP37_TSMP1             MPP( 37, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 275 #define MPP37_TDM_CH2_TX_QL     MPP( 37, 0x2, 0, 1, 0,   0,   0,   1,   1 )
 276 #define MPP37_AU_SPDIFO         MPP( 37, 0x4, 0, 1, 1,   0,   0,   1,   1 )
 277 #define MPP37_TW1_SCK           MPP( 37, 0xb, 1, 1, 0,   0,   0,   0,   1 )
 278
 279 #define MPP38_GPIO              MPP( 38, 0x0, 1, 1, 1,   0,   0,   1,   1 )
 280 #define MPP38_TSMP2             MPP( 38, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 281 #define MPP38_TDM_CH2_RX_QL     MPP( 38, 0x2, 0, 1, 0,   0,   0,   1,   1 )
 282 #define MPP38_AU_SPDIFRMLCLK    MPP( 38, 0x4, 0, 1, 1,   0,   0,   1,   1 )
 283 #define MPP38_LCD_D18           MPP( 38, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 284
 285 #define MPP39_GPIO              MPP( 39, 0x0, 1, 1, 1,   0,   0,   1,   1 )
 286 #define MPP39_TSMP3             MPP( 39, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 287 #define MPP39_TDM_SPI_CS0       MPP( 39, 0x2, 0, 1, 0,   0,   0,   1,   1 )
 288 #define MPP39_AU_I2SBCLK        MPP( 39, 0x4, 0, 1, 1,   0,   0,   1,   1 )
 289 #define MPP39_LCD_D19           MPP( 39, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 290
 291 #define MPP40_GPIO              MPP( 40, 0x0, 1, 1, 1,   0,   0,   1,   1 )
 292 #define MPP40_TSMP4             MPP( 40, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 293 #define MPP40_TDM_SPI_SCK       MPP( 40, 0x2, 0, 1, 0,   0,   0,   1,   1 )
 294 #define MPP40_AU_I2SDO          MPP( 40, 0x4, 0, 1, 1,   0,   0,   1,   1 )
 295 #define MPP40_LCD_D20           MPP( 40, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 296
 297 #define MPP41_GPIO              MPP( 41, 0x0, 1, 1, 1,   0,   0,   1,   1 )
 298 #define MPP41_TSMP5             MPP( 41, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 299 #define MPP41_TDM_SPI_MISO      MPP( 41, 0x2, 1, 0, 0,   0,   0,   1,   1 )
 300 #define MPP41_AU_I2SLRCLK       MPP( 41, 0x4, 0, 1, 1,   0,   0,   1,   1 )
 301 #define MPP41_LCD_D21           MPP( 41, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 302
 303 #define MPP42_GPIO              MPP( 42, 0x0, 1, 1, 1,   0,   0,   1,   1 )
 304 #define MPP42_TSMP6             MPP( 42, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 305 #define MPP42_TDM_SPI_MOSI      MPP( 42, 0x2, 0, 1, 0,   0,   0,   1,   1 )
 306 #define MPP42_AU_I2SMCLK        MPP( 42, 0x4, 0, 1, 1,   0,   0,   1,   1 )
 307 #define MPP42_LCD_D22           MPP( 42, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 308
 309 #define MPP43_GPIO              MPP( 43, 0x0, 1, 1, 1,   0,   0,   1,   1 )
 310 #define MPP43_TSMP7             MPP( 43, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 311 #define MPP43_TDM_CODEC_INTn    MPP( 43, 0x2, 0, 0, 0,   0,   0,   1,   1 )
 312 #define MPP43_AU_I2SDI          MPP( 43, 0x4, 1, 0, 1,   0,   0,   1,   1 )
 313 #define MPP43_LCD_D23           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 314
 315 #define MPP44_GPIO              MPP( 44, 0x0, 1, 1, 1,   0,   0,   1,   1 )
 316 #define MPP44_TSMP8             MPP( 44, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 317 #define MPP44_TDM_CODEC_RSTn    MPP( 44, 0x2, 0, 0, 0,   0,   0,   1,   1 )
 318 #define MPP44_AU_EXTCLK         MPP( 44, 0x4, 1, 0, 1,   0,   0,   1,   1 )
 319 #define MPP44_LCD_CLK           MPP( 44, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 320
 321 #define MPP45_GPIO              MPP( 45, 0x0, 1, 1, 0,   0,   0,   1,   1 )
 322 #define MPP45_TSMP9             MPP( 45, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 323 #define MPP45_TDM_PCLK          MPP( 45, 0x2, 1, 1, 0,   0,   0,   1,   1 )
 324 #define MPP245_LCD_E            MPP( 45, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 325
 326 #define MPP46_GPIO              MPP( 46, 0x0, 1, 1, 0,   0,   0,   1,   1 )
 327 #define MPP46_TSMP10            MPP( 46, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 328 #define MPP46_TDM_FS            MPP( 46, 0x2, 1, 1, 0,   0,   0,   1,   1 )
 329 #define MPP46_LCD_HSYNC         MPP( 46, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 330
 331 #define MPP47_GPIO              MPP( 47, 0x0, 1, 1, 0,   0,   0,   1,   1 )
 332 #define MPP47_TSMP11            MPP( 47, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 333 #define MPP47_TDM_DRX           MPP( 47, 0x2, 1, 0, 0,   0,   0,   1,   1 )
 334 #define MPP47_LCD_VSYNC         MPP( 47, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 335
 336 #define MPP48_GPIO              MPP( 48, 0x0, 1, 1, 0,   0,   0,   1,   1 )
 337 #define MPP48_TSMP12            MPP( 48, 0x1, 1, 1, 0,   0,   0,   1,   1 )
 338 #define MPP48_TDM_DTX           MPP( 48, 0x2, 0, 1, 0,   0,   0,   1,   1 )
 339 #define MPP48_LCD_D16           MPP( 22, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 340
 341 #define MPP49_GPIO              MPP( 49, 0x0, 1, 1, 0,   0,   0,   1,   0 )
 342 #define MPP49_GPO               MPP( 49, 0x0, 0, 1, 0,   0,   0,   0,   1 )
 343 #define MPP49_TSMP9             MPP( 49, 0x1, 1, 1, 0,   0,   0,   1,   0 )
 344 #define MPP49_TDM_CH0_RX_QL     MPP( 49, 0x2, 0, 1, 0,   0,   0,   1,   1 )
 345 #define MPP49_PTP_CLK           MPP( 49, 0x5, 1, 0, 0,   0,   0,   1,   0 )
 346 #define MPP49_PEX0_CLKREQ       MPP( 49, 0xa, 0, 1, 0,   0,   0,   0,   1 )
 347 #define MPP49_LCD_D17           MPP( 49, 0xb, 0, 0, 0,   0,   0,   0,   1 )
 348
 349 #define MPP_MAX                 49
 350
 351 void kirkwood_mpp_conf(unsigned int *mpp_list);
 352
 353 #endif