release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-cns3xxx/pm.c

   1 /*
   2  * Copyright 2008 Cavium Networks
   3  *
   4  * This file is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License, Version 2, as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/io.h>
  10 #include <linux/delay.h>
  11 #include <mach/system.h>
  12 #include <mach/cns3xxx.h>
  13
  14 void cns3xxx_pwr_clk_en(unsigned int block)
  15 {
  16         u32 reg = __raw_readl(PM_CLK_GATE_REG);
  17
  18         reg |= (block & PM_CLK_GATE_REG_MASK);
  19         __raw_writel(reg, PM_CLK_GATE_REG);
  20 }
  21
  22 void cns3xxx_pwr_power_up(unsigned int block)
  23 {
  24         u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
  25
  26         reg &= ~(block & CNS3XXX_PWR_PLL_ALL);
  27         __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
  28
  29         /* Wait for 300us for the PLL output clock locked. */
  30         udelay(300);
  31 };
  32
  33 void cns3xxx_pwr_power_down(unsigned int block)
  34 {
  35         u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG);
  36
  37         /* write '1' to power down */
  38         reg |= (block & CNS3XXX_PWR_PLL_ALL);
  39         __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG);
  40 };
  41
  42 static void cns3xxx_pwr_soft_rst_force(unsigned int block)
  43 {
  44         u32 reg = __raw_readl(PM_SOFT_RST_REG);
  45
  46         /*
  47          * bit 0, 28, 29 => program low to reset,
  48          * the other else program low and then high
  49          */
  50         if (block & 0x30000001) {
  51                 reg &= ~(block & PM_SOFT_RST_REG_MASK);
  52         } else {
  53                 reg &= ~(block & PM_SOFT_RST_REG_MASK);
  54                 reg |= (block & PM_SOFT_RST_REG_MASK);
  55         }
  56
  57         __raw_writel(reg, PM_SOFT_RST_REG);
  58 }
  59
  60 void cns3xxx_pwr_soft_rst(unsigned int block)
  61 {
  62         static unsigned int soft_reset;
  63
  64         if (soft_reset & block) {
  65                 /* SPI/I2C/GPIO use the same block, reset once. */
  66                 return;
  67         } else {
  68                 soft_reset |= block;
  69         }
  70         cns3xxx_pwr_soft_rst_force(block);
  71 }
  72
  73 void arch_reset(char mode, const char *cmd)
  74 {
  75         /*
  76          * To reset, we hit the on-board reset register
  77          * in the system FPGA.
  78          */
  79         cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL));
  80 }
  81
  82 /*
  83  * cns3xxx_cpu_clock - return CPU/L2 clock
  84  *  aclk: cpu clock/2
  85  *  hclk: cpu clock/4
  86  *  pclk: cpu clock/8
  87  */
  88 int cns3xxx_cpu_clock(void)
  89 {
  90         u32 reg = __raw_readl(PM_CLK_CTRL_REG);
  91         int cpu;
  92         int cpu_sel;
  93         int div_sel;
  94
  95         cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf;
  96         div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3;
  97
  98         cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel;
  99
 100         return cpu;
 101 }