release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/mach-at91/clock.c

   1 /*
   2  * linux/arch/arm/mach-at91/clock.c
   3  *
   4  * Copyright (C) 2005 David Brownell
   5  * Copyright (C) 2005 Ivan Kokshaysky
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  */
  12
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/fs.h>
  17 #include <linux/debugfs.h>
  18 #include <linux/seq_file.h>
  19 #include <linux/list.h>
  20 #include <linux/errno.h>
  21 #include <linux/err.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/delay.h>
  24 #include <linux/clk.h>
  25 #include <linux/io.h>
  26
  27 #include <mach/hardware.h>
  28 #include <mach/at91_pmc.h>
  29 #include <mach/cpu.h>
  30
  31 #include "clock.h"
  32 #include "generic.h"
  33
  34
  35 /*
  36  * There's a lot more which can be done with clocks, including cpufreq
  37  * integration, slow clock mode support (for system suspend), letting
  38  * PLLB be used at other rates (on boards that don't need USB), etc.
  39  */
  40
  41 #define clk_is_primary(x)       ((x)->type & CLK_TYPE_PRIMARY)
  42 #define clk_is_programmable(x)  ((x)->type & CLK_TYPE_PROGRAMMABLE)
  43 #define clk_is_peripheral(x)    ((x)->type & CLK_TYPE_PERIPHERAL)
  44 #define clk_is_sys(x)           ((x)->type & CLK_TYPE_SYSTEM)
  45
  46
  47 /*
  48  * Chips have some kind of clocks : group them by functionality
  49  */
  50 #define cpu_has_utmi()          (  cpu_is_at91cap9() \
  51                                 || cpu_is_at91sam9rl() \
  52                                 || cpu_is_at91sam9g45())
  53
  54 #define cpu_has_800M_plla()     (  cpu_is_at91sam9g20() \
  55                                 || cpu_is_at91sam9g45())
  56
  57 #define cpu_has_300M_plla()     (cpu_is_at91sam9g10())
  58
  59 #define cpu_has_pllb()          (!(cpu_is_at91sam9rl() \
  60                                 || cpu_is_at91sam9g45()))
  61
  62 #define cpu_has_upll()          (cpu_is_at91sam9g45())
  63
  64 /* USB host HS & FS */
  65 #define cpu_has_uhp()           (!cpu_is_at91sam9rl())
  66
  67 /* USB device FS only */
  68 #define cpu_has_udpfs()         (!(cpu_is_at91sam9rl() \
  69                                 || cpu_is_at91sam9g45()))
  70
  71 static LIST_HEAD(clocks);
  72 static DEFINE_SPINLOCK(clk_lock);
  73
  74 static u32 at91_pllb_usb_init;
  75
  76 /*
  77  * Four primary clock sources:  two crystal oscillators (32K, main), and
  78  * two PLLs.  PLLA usually runs the master clock; and PLLB must run at
  79  * 48 MHz (unless no USB function clocks are needed).  The main clock and
  80  * both PLLs are turned off to run in "slow clock mode" (system suspend).
  81  */
  82 static struct clk clk32k = {
  83         .name           = "clk32k",
  84         .rate_hz        = AT91_SLOW_CLOCK,
  85         .users          = 1,            /* always on */
  86         .id             = 0,
  87         .type           = CLK_TYPE_PRIMARY,
  88 };
  89 static struct clk main_clk = {
  90         .name           = "main",
  91         .pmc_mask       = AT91_PMC_MOSCS,       /* in PMC_SR */
  92         .id             = 1,
  93         .type           = CLK_TYPE_PRIMARY,
  94 };
  95 static struct clk plla = {
  96         .name           = "plla",
  97         .parent         = &main_clk,
  98         .pmc_mask       = AT91_PMC_LOCKA,       /* in PMC_SR */
  99         .id             = 2,
 100         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 101 };
 102
 103 static void pllb_mode(struct clk *clk, int is_on)
 104 {
 105         u32     value;
 106
 107         if (is_on) {
 108                 is_on = AT91_PMC_LOCKB;
 109                 value = at91_pllb_usb_init;
 110         } else
 111                 value = 0;
 112
 113         at91_sys_write(AT91_CKGR_PLLBR, value);
 114
 115         do {
 116                 cpu_relax();
 117         } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKB) != is_on);
 118 }
 119
 120 static struct clk pllb = {
 121         .name           = "pllb",
 122         .parent         = &main_clk,
 123         .pmc_mask       = AT91_PMC_LOCKB,       /* in PMC_SR */
 124         .mode           = pllb_mode,
 125         .id             = 3,
 126         .type           = CLK_TYPE_PRIMARY | CLK_TYPE_PLL,
 127 };
 128
 129 static void pmc_sys_mode(struct clk *clk, int is_on)
 130 {
 131         if (is_on)
 132                 at91_sys_write(AT91_PMC_SCER, clk->pmc_mask);
 133         else
 134                 at91_sys_write(AT91_PMC_SCDR, clk->pmc_mask);
 135 }
 136
 137 static void pmc_uckr_mode(struct clk *clk, int is_on)
 138 {
 139         unsigned int uckr = at91_sys_read(AT91_CKGR_UCKR);
 140
 141         if (cpu_is_at91sam9g45()) {
 142                 if (is_on)
 143                         uckr |= AT91_PMC_BIASEN;
 144                 else
 145                         uckr &= ~AT91_PMC_BIASEN;
 146         }
 147
 148         if (is_on) {
 149                 is_on = AT91_PMC_LOCKU;
 150                 at91_sys_write(AT91_CKGR_UCKR, uckr | clk->pmc_mask);
 151         } else
 152                 at91_sys_write(AT91_CKGR_UCKR, uckr & ~(clk->pmc_mask));
 153
 154         do {
 155                 cpu_relax();
 156         } while ((at91_sys_read(AT91_PMC_SR) & AT91_PMC_LOCKU) != is_on);
 157 }
 158
 159 /* USB function clocks (PLLB must be 48 MHz) */
 160 static struct clk udpck = {
 161         .name           = "udpck",
 162         .parent         = &pllb,
 163         .mode           = pmc_sys_mode,
 164 };
 165 static struct clk utmi_clk = {
 166         .name           = "utmi_clk",
 167         .parent         = &main_clk,
 168         .pmc_mask       = AT91_PMC_UPLLEN,      /* in CKGR_UCKR */
 169         .mode           = pmc_uckr_mode,
 170         .type           = CLK_TYPE_PLL,
 171 };
 172 static struct clk uhpck = {
 173         .name           = "uhpck",
 174         /*.parent               = ... we choose parent at runtime */
 175         .mode           = pmc_sys_mode,
 176 };
 177
 178
 179 /*
 180  * The master clock is divided from the CPU clock (by 1-4).  It's used for
 181  * memory, interfaces to on-chip peripherals, the AIC, and sometimes more
 182  * (e.g baud rate generation).  It's sourced from one of the primary clocks.
 183  */
 184 static struct clk mck = {
 185         .name           = "mck",
 186         .pmc_mask       = AT91_PMC_MCKRDY,      /* in PMC_SR */
 187 };
 188
 189 static void pmc_periph_mode(struct clk *clk, int is_on)
 190 {
 191         if (is_on)
 192                 at91_sys_write(AT91_PMC_PCER, clk->pmc_mask);
 193         else
 194                 at91_sys_write(AT91_PMC_PCDR, clk->pmc_mask);
 195 }
 196
 197 static struct clk __init *at91_css_to_clk(unsigned long css)
 198 {
 199         switch (css) {
 200                 case AT91_PMC_CSS_SLOW:
 201                         return &clk32k;
 202                 case AT91_PMC_CSS_MAIN:
 203                         return &main_clk;
 204                 case AT91_PMC_CSS_PLLA:
 205                         return &plla;
 206                 case AT91_PMC_CSS_PLLB:
 207                         if (cpu_has_upll())
 208                                 /* CSS_PLLB == CSS_UPLL */
 209                                 return &utmi_clk;
 210                         else if (cpu_has_pllb())
 211                                 return &pllb;
 212         }
 213
 214         return NULL;
 215 }
 216
 217 /*
 218  * Associate a particular clock with a function (eg, "uart") and device.
 219  * The drivers can then request the same 'function' with several different
 220  * devices and not care about which clock name to use.
 221  */
 222 void __init at91_clock_associate(const char *id, struct device *dev, const char *func)
 223 {
 224         struct clk *clk = clk_get(NULL, id);
 225
 226         if (!dev || !clk || !IS_ERR(clk_get(dev, func)))
 227                 return;
 228
 229         clk->function = func;
 230         clk->dev = dev;
 231 }
 232
 233 /* clocks cannot be de-registered no refcounting necessary */
 234 struct clk *clk_get(struct device *dev, const char *id)
 235 {
 236         struct clk *clk;
 237
 238         list_for_each_entry(clk, &clocks, node) {
 239                 if (strcmp(id, clk->name) == 0)
 240                         return clk;
 241                 if (clk->function && (dev == clk->dev) && strcmp(id, clk->function) == 0)
 242                         return clk;
 243         }
 244
 245         return ERR_PTR(-ENOENT);
 246 }
 247 EXPORT_SYMBOL(clk_get);
 248
 249 void clk_put(struct clk *clk)
 250 {
 251 }
 252 EXPORT_SYMBOL(clk_put);
 253
 254 static void __clk_enable(struct clk *clk)
 255 {
 256         if (clk->parent)
 257                 __clk_enable(clk->parent);
 258         if (clk->users++ == 0 && clk->mode)
 259                 clk->mode(clk, 1);
 260 }
 261
 262 int clk_enable(struct clk *clk)
 263 {
 264         unsigned long   flags;
 265
 266         spin_lock_irqsave(&clk_lock, flags);
 267         __clk_enable(clk);
 268         spin_unlock_irqrestore(&clk_lock, flags);
 269         return 0;
 270 }
 271 EXPORT_SYMBOL(clk_enable);
 272
 273 static void __clk_disable(struct clk *clk)
 274 {
 275         BUG_ON(clk->users == 0);
 276         if (--clk->users == 0 && clk->mode)
 277                 clk->mode(clk, 0);
 278         if (clk->parent)
 279                 __clk_disable(clk->parent);
 280 }
 281
 282 void clk_disable(struct clk *clk)
 283 {
 284         unsigned long   flags;
 285
 286         spin_lock_irqsave(&clk_lock, flags);
 287         __clk_disable(clk);
 288         spin_unlock_irqrestore(&clk_lock, flags);
 289 }
 290 EXPORT_SYMBOL(clk_disable);
 291
 292 unsigned long clk_get_rate(struct clk *clk)
 293 {
 294         unsigned long   flags;
 295         unsigned long   rate;
 296
 297         spin_lock_irqsave(&clk_lock, flags);
 298         for (;;) {
 299                 rate = clk->rate_hz;
 300                 if (rate || !clk->parent)
 301                         break;
 302                 clk = clk->parent;
 303         }
 304         spin_unlock_irqrestore(&clk_lock, flags);
 305         return rate;
 306 }
 307 EXPORT_SYMBOL(clk_get_rate);
 308
 309 /*------------------------------------------------------------------------*/
 310
 311 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 312
 313 /*
 314  * For now, only the programmable clocks support reparenting (MCK could
 315  * do this too, with care) or rate changing (the PLLs could do this too,
 316  * ditto MCK but that's more for cpufreq).  Drivers may reparent to get
 317  * a better rate match; we don't.
 318  */
 319
 320 long clk_round_rate(struct clk *clk, unsigned long rate)
 321 {
 322         unsigned long   flags;
 323         unsigned        prescale;
 324         unsigned long   actual;
 325         unsigned long   prev = ULONG_MAX;
 326
 327         if (!clk_is_programmable(clk))
 328                 return -EINVAL;
 329         spin_lock_irqsave(&clk_lock, flags);
 330
 331         actual = clk->parent->rate_hz;
 332         for (prescale = 0; prescale < 7; prescale++) {
 333                 if (actual > rate)
 334                         prev = actual;
 335
 336                 if (actual && actual <= rate) {
 337                         if ((prev - rate) < (rate - actual)) {
 338                                 actual = prev;
 339                                 prescale--;
 340                         }
 341                         break;
 342                 }
 343                 actual >>= 1;
 344         }
 345
 346         spin_unlock_irqrestore(&clk_lock, flags);
 347         return (prescale < 7) ? actual : -ENOENT;
 348 }
 349 EXPORT_SYMBOL(clk_round_rate);
 350
 351 int clk_set_rate(struct clk *clk, unsigned long rate)
 352 {
 353         unsigned long   flags;
 354         unsigned        prescale;
 355         unsigned long   actual;
 356
 357         if (!clk_is_programmable(clk))
 358                 return -EINVAL;
 359         if (clk->users)
 360                 return -EBUSY;
 361         spin_lock_irqsave(&clk_lock, flags);
 362
 363         actual = clk->parent->rate_hz;
 364         for (prescale = 0; prescale < 7; prescale++) {
 365                 if (actual && actual <= rate) {
 366                         u32     pckr;
 367
 368                         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 369                         pckr &= AT91_PMC_CSS;   /* clock selection */
 370                         pckr |= prescale << 2;
 371                         at91_sys_write(AT91_PMC_PCKR(clk->id), pckr);
 372                         clk->rate_hz = actual;
 373                         break;
 374                 }
 375                 actual >>= 1;
 376         }
 377
 378         spin_unlock_irqrestore(&clk_lock, flags);
 379         return (prescale < 7) ? actual : -ENOENT;
 380 }
 381 EXPORT_SYMBOL(clk_set_rate);
 382
 383 struct clk *clk_get_parent(struct clk *clk)
 384 {
 385         return clk->parent;
 386 }
 387 EXPORT_SYMBOL(clk_get_parent);
 388
 389 int clk_set_parent(struct clk *clk, struct clk *parent)
 390 {
 391         unsigned long   flags;
 392
 393         if (clk->users)
 394                 return -EBUSY;
 395         if (!clk_is_primary(parent) || !clk_is_programmable(clk))
 396                 return -EINVAL;
 397
 398         if (cpu_is_at91sam9rl() && parent->id == AT91_PMC_CSS_PLLB)
 399                 return -EINVAL;
 400
 401         spin_lock_irqsave(&clk_lock, flags);
 402
 403         clk->rate_hz = parent->rate_hz;
 404         clk->parent = parent;
 405         at91_sys_write(AT91_PMC_PCKR(clk->id), parent->id);
 406
 407         spin_unlock_irqrestore(&clk_lock, flags);
 408         return 0;
 409 }
 410 EXPORT_SYMBOL(clk_set_parent);
 411
 412 /* establish PCK0..PCKN parentage and rate */
 413 static void __init init_programmable_clock(struct clk *clk)
 414 {
 415         struct clk      *parent;
 416         u32             pckr;
 417
 418         pckr = at91_sys_read(AT91_PMC_PCKR(clk->id));
 419         parent = at91_css_to_clk(pckr & AT91_PMC_CSS);
 420         clk->parent = parent;
 421         clk->rate_hz = parent->rate_hz / (1 << ((pckr & AT91_PMC_PRES) >> 2));
 422 }
 423
 424 #endif  /* CONFIG_AT91_PROGRAMMABLE_CLOCKS */
 425
 426 /*------------------------------------------------------------------------*/
 427
 428 #ifdef CONFIG_DEBUG_FS
 429
 430 static int at91_clk_show(struct seq_file *s, void *unused)
 431 {
 432         u32             scsr, pcsr, uckr = 0, sr;
 433         struct clk      *clk;
 434
 435         seq_printf(s, "SCSR = %8x\n", scsr = at91_sys_read(AT91_PMC_SCSR));
 436         seq_printf(s, "PCSR = %8x\n", pcsr = at91_sys_read(AT91_PMC_PCSR));
 437         seq_printf(s, "MOR  = %8x\n", at91_sys_read(AT91_CKGR_MOR));
 438         seq_printf(s, "MCFR = %8x\n", at91_sys_read(AT91_CKGR_MCFR));
 439         seq_printf(s, "PLLA = %8x\n", at91_sys_read(AT91_CKGR_PLLAR));
 440         if (cpu_has_pllb())
 441                 seq_printf(s, "PLLB = %8x\n", at91_sys_read(AT91_CKGR_PLLBR));
 442         if (cpu_has_utmi())
 443                 seq_printf(s, "UCKR = %8x\n", uckr = at91_sys_read(AT91_CKGR_UCKR));
 444         seq_printf(s, "MCKR = %8x\n", at91_sys_read(AT91_PMC_MCKR));
 445         if (cpu_has_upll())
 446                 seq_printf(s, "USB  = %8x\n", at91_sys_read(AT91_PMC_USB));
 447         seq_printf(s, "SR   = %8x\n", sr = at91_sys_read(AT91_PMC_SR));
 448
 449         seq_printf(s, "\n");
 450
 451         list_for_each_entry(clk, &clocks, node) {
 452                 char    *state;
 453
 454                 if (clk->mode == pmc_sys_mode)
 455                         state = (scsr & clk->pmc_mask) ? "on" : "off";
 456                 else if (clk->mode == pmc_periph_mode)
 457                         state = (pcsr & clk->pmc_mask) ? "on" : "off";
 458                 else if (clk->mode == pmc_uckr_mode)
 459                         state = (uckr & clk->pmc_mask) ? "on" : "off";
 460                 else if (clk->pmc_mask)
 461                         state = (sr & clk->pmc_mask) ? "on" : "off";
 462                 else if (clk == &clk32k || clk == &main_clk)
 463                         state = "on";
 464                 else
 465                         state = "";
 466
 467                 seq_printf(s, "%-10s users=%2d %-3s %9ld Hz %s\n",
 468                         clk->name, clk->users, state, clk_get_rate(clk),
 469                         clk->parent ? clk->parent->name : "");
 470         }
 471         return 0;
 472 }
 473
 474 static int at91_clk_open(struct inode *inode, struct file *file)
 475 {
 476         return single_open(file, at91_clk_show, NULL);
 477 }
 478
 479 static const struct file_operations at91_clk_operations = {
 480         .open           = at91_clk_open,
 481         .read           = seq_read,
 482         .llseek         = seq_lseek,
 483         .release        = single_release,
 484 };
 485
 486 static int __init at91_clk_debugfs_init(void)
 487 {
 488         /* /sys/kernel/debug/at91_clk */
 489         (void) debugfs_create_file("at91_clk", S_IFREG | S_IRUGO, NULL, NULL, &at91_clk_operations);
 490
 491         return 0;
 492 }
 493 postcore_initcall(at91_clk_debugfs_init);
 494
 495 #endif
 496
 497 /*------------------------------------------------------------------------*/
 498
 499 /* Register a new clock */
 500 int __init clk_register(struct clk *clk)
 501 {
 502         if (clk_is_peripheral(clk)) {
 503                 if (!clk->parent)
 504                         clk->parent = &mck;
 505                 clk->mode = pmc_periph_mode;
 506                 list_add_tail(&clk->node, &clocks);
 507         }
 508         else if (clk_is_sys(clk)) {
 509                 clk->parent = &mck;
 510                 clk->mode = pmc_sys_mode;
 511
 512                 list_add_tail(&clk->node, &clocks);
 513         }
 514 #ifdef CONFIG_AT91_PROGRAMMABLE_CLOCKS
 515         else if (clk_is_programmable(clk)) {
 516                 clk->mode = pmc_sys_mode;
 517                 init_programmable_clock(clk);
 518                 list_add_tail(&clk->node, &clocks);
 519         }
 520 #endif
 521
 522         return 0;
 523 }
 524
 525
 526 /*------------------------------------------------------------------------*/
 527
 528 static u32 __init at91_pll_rate(struct clk *pll, u32 freq, u32 reg)
 529 {
 530         unsigned mul, div;
 531
 532         div = reg & 0xff;
 533         mul = (reg >> 16) & 0x7ff;
 534         if (div && mul) {
 535                 freq /= div;
 536                 freq *= mul + 1;
 537         } else
 538                 freq = 0;
 539
 540         return freq;
 541 }
 542
 543 static u32 __init at91_usb_rate(struct clk *pll, u32 freq, u32 reg)
 544 {
 545         if (pll == &pllb && (reg & AT91_PMC_USB96M))
 546                 return freq / 2;
 547         else
 548                 return freq;
 549 }
 550
 551 static unsigned __init at91_pll_calc(unsigned main_freq, unsigned out_freq)
 552 {
 553         unsigned i, div = 0, mul = 0, diff = 1 << 30;
 554         unsigned ret = (out_freq > 155000000) ? 0xbe00 : 0x3e00;
 555
 556         /* PLL output max 240 MHz (or 180 MHz per errata) */
 557         if (out_freq > 240000000)
 558                 goto fail;
 559
 560         for (i = 1; i < 256; i++) {
 561                 int diff1;
 562                 unsigned input, mul1;
 563
 564                 /*
 565                  * PLL input between 1MHz and 32MHz per spec, but lower
 566                  * frequences seem necessary in some cases so allow 100K.
 567                  * Warning: some newer products need 2MHz min.
 568                  */
 569                 input = main_freq / i;
 570                 if (cpu_is_at91sam9g20() && input < 2000000)
 571                         continue;
 572                 if (input < 100000)
 573                         continue;
 574                 if (input > 32000000)
 575                         continue;
 576
 577                 mul1 = out_freq / input;
 578                 if (cpu_is_at91sam9g20() && mul > 63)
 579                         continue;
 580                 if (mul1 > 2048)
 581                         continue;
 582                 if (mul1 < 2)
 583                         goto fail;
 584
 585                 diff1 = out_freq - input * mul1;
 586                 if (diff1 < 0)
 587                         diff1 = -diff1;
 588                 if (diff > diff1) {
 589                         diff = diff1;
 590                         div = i;
 591                         mul = mul1;
 592                         if (diff == 0)
 593                                 break;
 594                 }
 595         }
 596         if (i == 256 && diff > (out_freq >> 5))
 597                 goto fail;
 598         return ret | ((mul - 1) << 16) | div;
 599 fail:
 600         return 0;
 601 }
 602
 603 static struct clk *const standard_pmc_clocks[] __initdata = {
 604         /* four primary clocks */
 605         &clk32k,
 606         &main_clk,
 607         &plla,
 608
 609         /* MCK */
 610         &mck
 611 };
 612
 613 /* PLLB generated USB full speed clock init */
 614 static void __init at91_pllb_usbfs_clock_init(unsigned long main_clock)
 615 {
 616         /*
 617          * USB clock init:  choose 48 MHz PLLB value,
 618          * disable 48MHz clock during usb peripheral suspend.
 619          *
 620          * REVISIT:  assumes MCK doesn't derive from PLLB!
 621          */
 622         uhpck.parent = &pllb;
 623
 624         at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) | AT91_PMC_USB96M;
 625         pllb.rate_hz = at91_pll_rate(&pllb, main_clock, at91_pllb_usb_init);
 626         if (cpu_is_at91rm9200()) {
 627                 uhpck.pmc_mask = AT91RM9200_PMC_UHP;
 628                 udpck.pmc_mask = AT91RM9200_PMC_UDP;
 629                 at91_sys_write(AT91_PMC_SCER, AT91RM9200_PMC_MCKUDP);
 630         } else if (cpu_is_at91sam9260() || cpu_is_at91sam9261() ||
 631                    cpu_is_at91sam9263() || cpu_is_at91sam9g20() ||
 632                    cpu_is_at91sam9g10() || cpu_is_at572d940hf()) {
 633                 uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 634                 udpck.pmc_mask = AT91SAM926x_PMC_UDP;
 635         } else if (cpu_is_at91cap9()) {
 636                 uhpck.pmc_mask = AT91CAP9_PMC_UHP;
 637         }
 638         at91_sys_write(AT91_CKGR_PLLBR, 0);
 639
 640         udpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 641         uhpck.rate_hz = at91_usb_rate(&pllb, pllb.rate_hz, at91_pllb_usb_init);
 642 }
 643
 644 /* UPLL generated USB full speed clock init */
 645 static void __init at91_upll_usbfs_clock_init(unsigned long main_clock)
 646 {
 647         /*
 648          * USB clock init: choose 480 MHz from UPLL,
 649          */
 650         unsigned int usbr = AT91_PMC_USBS_UPLL;
 651
 652         /* Setup divider by 10 to reach 48 MHz */
 653         usbr |= ((10 - 1) << 8) & AT91_PMC_OHCIUSBDIV;
 654
 655         at91_sys_write(AT91_PMC_USB, usbr);
 656
 657         /* Now set uhpck values */
 658         uhpck.parent = &utmi_clk;
 659         uhpck.pmc_mask = AT91SAM926x_PMC_UHP;
 660         uhpck.rate_hz = utmi_clk.parent->rate_hz;
 661         uhpck.rate_hz /= 1 + ((at91_sys_read(AT91_PMC_USB) & AT91_PMC_OHCIUSBDIV) >> 8);
 662 }
 663
 664 int __init at91_clock_init(unsigned long main_clock)
 665 {
 666         unsigned tmp, freq, mckr;
 667         int i;
 668         int pll_overclock = false;
 669
 670         /*
 671          * When the bootloader initialized the main oscillator correctly,
 672          * there's no problem using the cycle counter.  But if it didn't,
 673          * or when using oscillator bypass mode, we must be told the speed
 674          * of the main clock.
 675          */
 676         if (!main_clock) {
 677                 do {
 678                         tmp = at91_sys_read(AT91_CKGR_MCFR);
 679                 } while (!(tmp & AT91_PMC_MAINRDY));
 680                 main_clock = (tmp & AT91_PMC_MAINF) * (AT91_SLOW_CLOCK / 16);
 681         }
 682         main_clk.rate_hz = main_clock;
 683
 684         /* report if PLLA is more than mildly overclocked */
 685         plla.rate_hz = at91_pll_rate(&plla, main_clock, at91_sys_read(AT91_CKGR_PLLAR));
 686         if (cpu_has_300M_plla()) {
 687                 if (plla.rate_hz > 300000000)
 688                         pll_overclock = true;
 689         } else if (cpu_has_800M_plla()) {
 690                 if (plla.rate_hz > 800000000)
 691                         pll_overclock = true;
 692         } else {
 693                 if (plla.rate_hz > 209000000)
 694                         pll_overclock = true;
 695         }
 696         if (pll_overclock)
 697                 pr_info("Clocks: PLLA overclocked, %ld MHz\n", plla.rate_hz / 1000000);
 698
 699         if (cpu_is_at91sam9g45()) {
 700                 mckr = at91_sys_read(AT91_PMC_MCKR);
 701                 plla.rate_hz /= (1 << ((mckr & AT91_PMC_PLLADIV2) >> 12));      /* plla divisor by 2 */
 702         }
 703
 704         if (!cpu_has_pllb() && cpu_has_upll()) {
 705                 /* setup UTMI clock as the fourth primary clock
 706                  * (instead of pllb) */
 707                 utmi_clk.type |= CLK_TYPE_PRIMARY;
 708                 utmi_clk.id = 3;
 709         }
 710
 711
 712         /*
 713          * USB HS clock init
 714          */
 715         if (cpu_has_utmi()) {
 716                 /*
 717                  * multiplier is hard-wired to 40
 718                  * (obtain the USB High Speed 480 MHz when input is 12 MHz)
 719                  */
 720                 utmi_clk.rate_hz = 40 * utmi_clk.parent->rate_hz;
 721         }
 722
 723         /*
 724          * USB FS clock init
 725          */
 726         if (cpu_has_pllb())
 727                 at91_pllb_usbfs_clock_init(main_clock);
 728         if (cpu_has_upll())
 729                 /* assumes that we choose UPLL for USB and not PLLA */
 730                 at91_upll_usbfs_clock_init(main_clock);
 731
 732         /*
 733          * MCK and CPU derive from one of those primary clocks.
 734          * For now, assume this parentage won't change.
 735          */
 736         mckr = at91_sys_read(AT91_PMC_MCKR);
 737         mck.parent = at91_css_to_clk(mckr & AT91_PMC_CSS);
 738         freq = mck.parent->rate_hz;
 739         freq /= (1 << ((mckr & AT91_PMC_PRES) >> 2));                           /* prescale */
 740         if (cpu_is_at91rm9200()) {
 741                 mck.rate_hz = freq / (1 + ((mckr & AT91_PMC_MDIV) >> 8));       /* mdiv */
 742         } else if (cpu_is_at91sam9g20()) {
 743                 mck.rate_hz = (mckr & AT91_PMC_MDIV) ?
 744                         freq / ((mckr & AT91_PMC_MDIV) >> 7) : freq;    /* mdiv ; (x >> 7) = ((x >> 8) * 2) */
 745                 if (mckr & AT91_PMC_PDIV)
 746                         freq /= 2;              /* processor clock division */
 747         } else if (cpu_is_at91sam9g45()) {
 748                 mck.rate_hz = (mckr & AT91_PMC_MDIV) == AT91SAM9_PMC_MDIV_3 ?
 749                         freq / 3 : freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8)); /* mdiv */
 750         } else {
 751                 mck.rate_hz = freq / (1 << ((mckr & AT91_PMC_MDIV) >> 8));              /* mdiv */
 752         }
 753
 754         /* Register the PMC's standard clocks */
 755         for (i = 0; i < ARRAY_SIZE(standard_pmc_clocks); i++)
 756                 list_add_tail(&standard_pmc_clocks[i]->node, &clocks);
 757
 758         if (cpu_has_pllb())
 759                 list_add_tail(&pllb.node, &clocks);
 760
 761         if (cpu_has_uhp())
 762                 list_add_tail(&uhpck.node, &clocks);
 763
 764         if (cpu_has_udpfs())
 765                 list_add_tail(&udpck.node, &clocks);
 766
 767         if (cpu_has_utmi())
 768                 list_add_tail(&utmi_clk.node, &clocks);
 769
 770         /* MCK and CPU clock are "always on" */
 771         clk_enable(&mck);
 772
 773         printk("Clocks: CPU %u MHz, master %u MHz, main %u.%03u MHz\n",
 774                 freq / 1000000, (unsigned) mck.rate_hz / 1000000,
 775                 (unsigned) main_clock / 1000000,
 776                 ((unsigned) main_clock % 1000000) / 1000);
 777
 778         return 0;
 779 }
 780
 781 /*
 782  * Several unused clocks may be active.  Turn them off.
 783  */
 784 static int __init at91_clock_reset(void)
 785 {
 786         unsigned long pcdr = 0;
 787         unsigned long scdr = 0;
 788         struct clk *clk;
 789
 790         list_for_each_entry(clk, &clocks, node) {
 791                 if (clk->users > 0)
 792                         continue;
 793
 794                 if (clk->mode == pmc_periph_mode)
 795                         pcdr |= clk->pmc_mask;
 796
 797                 if (clk->mode == pmc_sys_mode)
 798                         scdr |= clk->pmc_mask;
 799
 800                 pr_debug("Clocks: disable unused %s\n", clk->name);
 801         }
 802
 803         at91_sys_write(AT91_PMC_PCDR, pcdr);
 804         at91_sys_write(AT91_PMC_SCDR, scdr);
 805
 806         return 0;
 807 }
 808 late_initcall(at91_clock_reset);