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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / linux / linux-2.6.36 / arch / arm / mach-at91 / at91sam9g45_devices.c
blob50fb1c2f9aa244ed8308d9a0d319e2c0747f713f
1 /*
2 * On-Chip devices setup code for the AT91SAM9G45 family
3 *
4 * Copyright (C) 2009 Atmel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 */
12 #include <asm/mach/arch.h>
13 #include <asm/mach/map.h>
14
15 #include <linux/dma-mapping.h>
16 #include <linux/platform_device.h>
17 #include <linux/i2c-gpio.h>
18
19 #include <linux/fb.h>
20 #include <video/atmel_lcdc.h>
21
22 #include <mach/board.h>
23 #include <mach/gpio.h>
24 #include <mach/at91sam9g45.h>
25 #include <mach/at91sam9g45_matrix.h>
26 #include <mach/at91sam9_smc.h>
27 #include <mach/at_hdmac.h>
28
29 #include "generic.h"
30
31
32 /* --------------------------------------------------------------------
33 * HDMAC - AHB DMA Controller
34 * -------------------------------------------------------------------- */
35
36 #if defined(CONFIG_AT_HDMAC) || defined(CONFIG_AT_HDMAC_MODULE)
37 static u64 hdmac_dmamask = DMA_BIT_MASK(32);
38
39 static struct at_dma_platform_data atdma_pdata = {
40 .nr_channels = 8,
41 };
42
43 static struct resource hdmac_resources[] = {
44 [0] = {
45 .start = AT91_BASE_SYS + AT91_DMA,
46 .end = AT91_BASE_SYS + AT91_DMA + SZ_512 - 1,
47 .flags = IORESOURCE_MEM,
48 },
49 [1] = {
50 .start = AT91SAM9G45_ID_DMA,
51 .end = AT91SAM9G45_ID_DMA,
52 .flags = IORESOURCE_IRQ,
53 },
54 };
55
56 static struct platform_device at_hdmac_device = {
57 .name = "at_hdmac",
58 .id = -1,
59 .dev = {
60 .dma_mask = &hdmac_dmamask,
61 .coherent_dma_mask = DMA_BIT_MASK(32),
62 .platform_data = &atdma_pdata,
63 },
64 .resource = hdmac_resources,
65 .num_resources = ARRAY_SIZE(hdmac_resources),
66 };
67
68 void __init at91_add_device_hdmac(void)
69 {
70 dma_cap_set(DMA_MEMCPY, atdma_pdata.cap_mask);
71 dma_cap_set(DMA_SLAVE, atdma_pdata.cap_mask);
72 platform_device_register(&at_hdmac_device);
73 }
74 #else
75 void __init at91_add_device_hdmac(void) {}
76 #endif
77
78
79 /* --------------------------------------------------------------------
80 * USB Host (OHCI)
81 * -------------------------------------------------------------------- */
82
83 #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
84 static u64 ohci_dmamask = DMA_BIT_MASK(32);
85 static struct at91_usbh_data usbh_ohci_data;
86
87 static struct resource usbh_ohci_resources[] = {
88 [0] = {
89 .start = AT91SAM9G45_OHCI_BASE,
90 .end = AT91SAM9G45_OHCI_BASE + SZ_1M - 1,
91 .flags = IORESOURCE_MEM,
92 },
93 [1] = {
94 .start = AT91SAM9G45_ID_UHPHS,
95 .end = AT91SAM9G45_ID_UHPHS,
96 .flags = IORESOURCE_IRQ,
97 },
98 };
99
100 static struct platform_device at91_usbh_ohci_device = {
101 .name = "at91_ohci",
102 .id = -1,
103 .dev = {
104 .dma_mask = &ohci_dmamask,
105 .coherent_dma_mask = DMA_BIT_MASK(32),
106 .platform_data = &usbh_ohci_data,
107 },
108 .resource = usbh_ohci_resources,
109 .num_resources = ARRAY_SIZE(usbh_ohci_resources),
110 };
111
112 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data)
113 {
114 int i;
115
116 if (!data)
117 return;
118
119 /* Enable VBus control for UHP ports */
120 for (i = 0; i < data->ports; i++) {
121 if (data->vbus_pin[i])
122 at91_set_gpio_output(data->vbus_pin[i], 0);
123 }
124
125 usbh_ohci_data = *data;
126 platform_device_register(&at91_usbh_ohci_device);
127 }
128 #else
129 void __init at91_add_device_usbh_ohci(struct at91_usbh_data *data) {}
130 #endif
131
132
133 /* --------------------------------------------------------------------
134 * USB Host HS (EHCI)
135 * Needs an OHCI host for low and full speed management
136 * -------------------------------------------------------------------- */
137
138 #if defined(CONFIG_USB_EHCI_HCD) || defined(CONFIG_USB_EHCI_HCD_MODULE)
139 static u64 ehci_dmamask = DMA_BIT_MASK(32);
140 static struct at91_usbh_data usbh_ehci_data;
141
142 static struct resource usbh_ehci_resources[] = {
143 [0] = {
144 .start = AT91SAM9G45_EHCI_BASE,
145 .end = AT91SAM9G45_EHCI_BASE + SZ_1M - 1,
146 .flags = IORESOURCE_MEM,
147 },
148 [1] = {
149 .start = AT91SAM9G45_ID_UHPHS,
150 .end = AT91SAM9G45_ID_UHPHS,
151 .flags = IORESOURCE_IRQ,
152 },
153 };
154
155 static struct platform_device at91_usbh_ehci_device = {
156 .name = "atmel-ehci",
157 .id = -1,
158 .dev = {
159 .dma_mask = &ehci_dmamask,
160 .coherent_dma_mask = DMA_BIT_MASK(32),
161 .platform_data = &usbh_ehci_data,
162 },
163 .resource = usbh_ehci_resources,
164 .num_resources = ARRAY_SIZE(usbh_ehci_resources),
165 };
166
167 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data)
168 {
169 int i;
170
171 if (!data)
172 return;
173
174 /* Enable VBus control for UHP ports */
175 for (i = 0; i < data->ports; i++) {
176 if (data->vbus_pin[i])
177 at91_set_gpio_output(data->vbus_pin[i], 0);
178 }
179
180 usbh_ehci_data = *data;
181 at91_clock_associate("uhphs_clk", &at91_usbh_ehci_device.dev, "ehci_clk");
182 platform_device_register(&at91_usbh_ehci_device);
183 }
184 #else
185 void __init at91_add_device_usbh_ehci(struct at91_usbh_data *data) {}
186 #endif
187
188
189 /* --------------------------------------------------------------------
190 * USB HS Device (Gadget)
191 * -------------------------------------------------------------------- */
192
193 #if defined(CONFIG_USB_GADGET_ATMEL_USBA) || \
194 defined(CONFIG_USB_GADGET_ATMEL_USBA_MODULE)
195 static struct resource usba_udc_resources[] = {
196 [0] = {
197 .start = AT91SAM9G45_UDPHS_FIFO,
198 .end = AT91SAM9G45_UDPHS_FIFO + SZ_512K - 1,
199 .flags = IORESOURCE_MEM,
200 },
201 [1] = {
202 .start = AT91SAM9G45_BASE_UDPHS,
203 .end = AT91SAM9G45_BASE_UDPHS + SZ_1K - 1,
204 .flags = IORESOURCE_MEM,
205 },
206 [2] = {
207 .start = AT91SAM9G45_ID_UDPHS,
208 .end = AT91SAM9G45_ID_UDPHS,
209 .flags = IORESOURCE_IRQ,
210 },
211 };
212
213 #define EP(nam, idx, maxpkt, maxbk, dma, isoc) \
214 [idx] = { \
215 .name = nam, \
216 .index = idx, \
217 .fifo_size = maxpkt, \
218 .nr_banks = maxbk, \
219 .can_dma = dma, \
220 .can_isoc = isoc, \
221 }
222
223 static struct usba_ep_data usba_udc_ep[] __initdata = {
224 EP("ep0", 0, 64, 1, 0, 0),
225 EP("ep1", 1, 1024, 2, 1, 1),
226 EP("ep2", 2, 1024, 2, 1, 1),
227 EP("ep3", 3, 1024, 3, 1, 0),
228 EP("ep4", 4, 1024, 3, 1, 0),
229 EP("ep5", 5, 1024, 3, 1, 1),
230 EP("ep6", 6, 1024, 3, 1, 1),
231 };
232
233 #undef EP
234
235 /*
236 * pdata doesn't have room for any endpoints, so we need to
237 * append room for the ones we need right after it.
238 */
239 static struct {
240 struct usba_platform_data pdata;
241 struct usba_ep_data ep[7];
242 } usba_udc_data;
243
244 static struct platform_device at91_usba_udc_device = {
245 .name = "atmel_usba_udc",
246 .id = -1,
247 .dev = {
248 .platform_data = &usba_udc_data.pdata,
249 },
250 .resource = usba_udc_resources,
251 .num_resources = ARRAY_SIZE(usba_udc_resources),
252 };
253
254 void __init at91_add_device_usba(struct usba_platform_data *data)
255 {
256 usba_udc_data.pdata.vbus_pin = -EINVAL;
257 usba_udc_data.pdata.num_ep = ARRAY_SIZE(usba_udc_ep);
258 memcpy(usba_udc_data.ep, usba_udc_ep, sizeof(usba_udc_ep));;
259
260 if (data && data->vbus_pin > 0) {
261 at91_set_gpio_input(data->vbus_pin, 0);
262 at91_set_deglitch(data->vbus_pin, 1);
263 usba_udc_data.pdata.vbus_pin = data->vbus_pin;
264 }
265
266 /* Pullup pin is handled internally by USB device peripheral */
267
268 /* Clocks */
269 at91_clock_associate("utmi_clk", &at91_usba_udc_device.dev, "hclk");
270 at91_clock_associate("udphs_clk", &at91_usba_udc_device.dev, "pclk");
271
272 platform_device_register(&at91_usba_udc_device);
273 }
274 #else
275 void __init at91_add_device_usba(struct usba_platform_data *data) {}
276 #endif
277
278
279 /* --------------------------------------------------------------------
280 * Ethernet
281 * -------------------------------------------------------------------- */
282
283 #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
284 static u64 eth_dmamask = DMA_BIT_MASK(32);
285 static struct at91_eth_data eth_data;
286
287 static struct resource eth_resources[] = {
288 [0] = {
289 .start = AT91SAM9G45_BASE_EMAC,
290 .end = AT91SAM9G45_BASE_EMAC + SZ_16K - 1,
291 .flags = IORESOURCE_MEM,
292 },
293 [1] = {
294 .start = AT91SAM9G45_ID_EMAC,
295 .end = AT91SAM9G45_ID_EMAC,
296 .flags = IORESOURCE_IRQ,
297 },
298 };
299
300 static struct platform_device at91sam9g45_eth_device = {
301 .name = "macb",
302 .id = -1,
303 .dev = {
304 .dma_mask = &eth_dmamask,
305 .coherent_dma_mask = DMA_BIT_MASK(32),
306 .platform_data = &eth_data,
307 },
308 .resource = eth_resources,
309 .num_resources = ARRAY_SIZE(eth_resources),
310 };
311
312 void __init at91_add_device_eth(struct at91_eth_data *data)
313 {
314 if (!data)
315 return;
316
317 if (data->phy_irq_pin) {
318 at91_set_gpio_input(data->phy_irq_pin, 0);
319 at91_set_deglitch(data->phy_irq_pin, 1);
320 }
321
322 /* Pins used for MII and RMII */
323 at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */
324 at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */
325 at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */
326 at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */
327 at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */
328 at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */
329 at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */
330 at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */
331 at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */
332 at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */
333
334 if (!data->is_rmii) {
335 at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */
336 at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */
337 at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */
338 at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */
339 at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */
340 at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */
341 at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */
342 at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */
343 }
344
345 eth_data = *data;
346 platform_device_register(&at91sam9g45_eth_device);
347 }
348 #else
349 void __init at91_add_device_eth(struct at91_eth_data *data) {}
350 #endif
351
352
353 /* --------------------------------------------------------------------
354 * NAND / SmartMedia
355 * -------------------------------------------------------------------- */
356
357 #if defined(CONFIG_MTD_NAND_ATMEL) || defined(CONFIG_MTD_NAND_ATMEL_MODULE)
358 static struct atmel_nand_data nand_data;
359
360 #define NAND_BASE AT91_CHIPSELECT_3
361
362 static struct resource nand_resources[] = {
363 [0] = {
364 .start = NAND_BASE,
365 .end = NAND_BASE + SZ_256M - 1,
366 .flags = IORESOURCE_MEM,
367 },
368 [1] = {
369 .start = AT91_BASE_SYS + AT91_ECC,
370 .end = AT91_BASE_SYS + AT91_ECC + SZ_512 - 1,
371 .flags = IORESOURCE_MEM,
372 }
373 };
374
375 static struct platform_device at91sam9g45_nand_device = {
376 .name = "atmel_nand",
377 .id = -1,
378 .dev = {
379 .platform_data = &nand_data,
380 },
381 .resource = nand_resources,
382 .num_resources = ARRAY_SIZE(nand_resources),
383 };
384
385 void __init at91_add_device_nand(struct atmel_nand_data *data)
386 {
387 unsigned long csa;
388
389 if (!data)
390 return;
391
392 csa = at91_sys_read(AT91_MATRIX_EBICSA);
393 at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA);
394
395 /* enable pin */
396 if (data->enable_pin)
397 at91_set_gpio_output(data->enable_pin, 1);
398
399 /* ready/busy pin */
400 if (data->rdy_pin)
401 at91_set_gpio_input(data->rdy_pin, 1);
402
403 /* card detect pin */
404 if (data->det_pin)
405 at91_set_gpio_input(data->det_pin, 1);
406
407 nand_data = *data;
408 platform_device_register(&at91sam9g45_nand_device);
409 }
410 #else
411 void __init at91_add_device_nand(struct atmel_nand_data *data) {}
412 #endif
413
414
415 /* --------------------------------------------------------------------
416 * TWI (i2c)
417 * -------------------------------------------------------------------- */
418
419 /*
420 * Prefer the GPIO code since the TWI controller isn't robust
421 * (gets overruns and underruns under load) and can only issue
422 * repeated STARTs in one scenario (the driver doesn't yet handle them).
423 */
424 #if defined(CONFIG_I2C_GPIO) || defined(CONFIG_I2C_GPIO_MODULE)
425 static struct i2c_gpio_platform_data pdata_i2c0 = {
426 .sda_pin = AT91_PIN_PA20,
427 .sda_is_open_drain = 1,
428 .scl_pin = AT91_PIN_PA21,
429 .scl_is_open_drain = 1,
430 .udelay = 5, /* ~100 kHz */
431 };
432
433 static struct platform_device at91sam9g45_twi0_device = {
434 .name = "i2c-gpio",
435 .id = 0,
436 .dev.platform_data = &pdata_i2c0,
437 };
438
439 static struct i2c_gpio_platform_data pdata_i2c1 = {
440 .sda_pin = AT91_PIN_PB10,
441 .sda_is_open_drain = 1,
442 .scl_pin = AT91_PIN_PB11,
443 .scl_is_open_drain = 1,
444 .udelay = 5, /* ~100 kHz */
445 };
446
447 static struct platform_device at91sam9g45_twi1_device = {
448 .name = "i2c-gpio",
449 .id = 1,
450 .dev.platform_data = &pdata_i2c1,
451 };
452
453 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
454 {
455 i2c_register_board_info(i2c_id, devices, nr_devices);
456
457 if (i2c_id == 0) {
458 at91_set_GPIO_periph(AT91_PIN_PA20, 1); /* TWD (SDA) */
459 at91_set_multi_drive(AT91_PIN_PA20, 1);
460
461 at91_set_GPIO_periph(AT91_PIN_PA21, 1); /* TWCK (SCL) */
462 at91_set_multi_drive(AT91_PIN_PA21, 1);
463
464 platform_device_register(&at91sam9g45_twi0_device);
465 } else {
466 at91_set_GPIO_periph(AT91_PIN_PB10, 1); /* TWD (SDA) */
467 at91_set_multi_drive(AT91_PIN_PB10, 1);
468
469 at91_set_GPIO_periph(AT91_PIN_PB11, 1); /* TWCK (SCL) */
470 at91_set_multi_drive(AT91_PIN_PB11, 1);
471
472 platform_device_register(&at91sam9g45_twi1_device);
473 }
474 }
475
476 #elif defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
477 static struct resource twi0_resources[] = {
478 [0] = {
479 .start = AT91SAM9G45_BASE_TWI0,
480 .end = AT91SAM9G45_BASE_TWI0 + SZ_16K - 1,
481 .flags = IORESOURCE_MEM,
482 },
483 [1] = {
484 .start = AT91SAM9G45_ID_TWI0,
485 .end = AT91SAM9G45_ID_TWI0,
486 .flags = IORESOURCE_IRQ,
487 },
488 };
489
490 static struct platform_device at91sam9g45_twi0_device = {
491 .name = "at91_i2c",
492 .id = 0,
493 .resource = twi0_resources,
494 .num_resources = ARRAY_SIZE(twi0_resources),
495 };
496
497 static struct resource twi1_resources[] = {
498 [0] = {
499 .start = AT91SAM9G45_BASE_TWI1,
500 .end = AT91SAM9G45_BASE_TWI1 + SZ_16K - 1,
501 .flags = IORESOURCE_MEM,
502 },
503 [1] = {
504 .start = AT91SAM9G45_ID_TWI1,
505 .end = AT91SAM9G45_ID_TWI1,
506 .flags = IORESOURCE_IRQ,
507 },
508 };
509
510 static struct platform_device at91sam9g45_twi1_device = {
511 .name = "at91_i2c",
512 .id = 1,
513 .resource = twi1_resources,
514 .num_resources = ARRAY_SIZE(twi1_resources),
515 };
516
517 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices)
518 {
519 i2c_register_board_info(i2c_id, devices, nr_devices);
520
521 /* pins used for TWI interface */
522 if (i2c_id == 0) {
523 at91_set_A_periph(AT91_PIN_PA20, 0); /* TWD */
524 at91_set_multi_drive(AT91_PIN_PA20, 1);
525
526 at91_set_A_periph(AT91_PIN_PA21, 0); /* TWCK */
527 at91_set_multi_drive(AT91_PIN_PA21, 1);
528
529 platform_device_register(&at91sam9g45_twi0_device);
530 } else {
531 at91_set_A_periph(AT91_PIN_PB10, 0); /* TWD */
532 at91_set_multi_drive(AT91_PIN_PB10, 1);
533
534 at91_set_A_periph(AT91_PIN_PB11, 0); /* TWCK */
535 at91_set_multi_drive(AT91_PIN_PB11, 1);
536
537 platform_device_register(&at91sam9g45_twi1_device);
538 }
539 }
540 #else
541 void __init at91_add_device_i2c(short i2c_id, struct i2c_board_info *devices, int nr_devices) {}
542 #endif
543
544
545 /* --------------------------------------------------------------------
546 * SPI
547 * -------------------------------------------------------------------- */
548
549 #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
550 static u64 spi_dmamask = DMA_BIT_MASK(32);
551
552 static struct resource spi0_resources[] = {
553 [0] = {
554 .start = AT91SAM9G45_BASE_SPI0,
555 .end = AT91SAM9G45_BASE_SPI0 + SZ_16K - 1,
556 .flags = IORESOURCE_MEM,
557 },
558 [1] = {
559 .start = AT91SAM9G45_ID_SPI0,
560 .end = AT91SAM9G45_ID_SPI0,
561 .flags = IORESOURCE_IRQ,
562 },
563 };
564
565 static struct platform_device at91sam9g45_spi0_device = {
566 .name = "atmel_spi",
567 .id = 0,
568 .dev = {
569 .dma_mask = &spi_dmamask,
570 .coherent_dma_mask = DMA_BIT_MASK(32),
571 },
572 .resource = spi0_resources,
573 .num_resources = ARRAY_SIZE(spi0_resources),
574 };
575
576 static const unsigned spi0_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PB18, AT91_PIN_PB19, AT91_PIN_PD27 };
577
578 static struct resource spi1_resources[] = {
579 [0] = {
580 .start = AT91SAM9G45_BASE_SPI1,
581 .end = AT91SAM9G45_BASE_SPI1 + SZ_16K - 1,
582 .flags = IORESOURCE_MEM,
583 },
584 [1] = {
585 .start = AT91SAM9G45_ID_SPI1,
586 .end = AT91SAM9G45_ID_SPI1,
587 .flags = IORESOURCE_IRQ,
588 },
589 };
590
591 static struct platform_device at91sam9g45_spi1_device = {
592 .name = "atmel_spi",
593 .id = 1,
594 .dev = {
595 .dma_mask = &spi_dmamask,
596 .coherent_dma_mask = DMA_BIT_MASK(32),
597 },
598 .resource = spi1_resources,
599 .num_resources = ARRAY_SIZE(spi1_resources),
600 };
601
602 static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB17, AT91_PIN_PD28, AT91_PIN_PD18, AT91_PIN_PD19 };
603
604 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
605 {
606 int i;
607 unsigned long cs_pin;
608 short enable_spi0 = 0;
609 short enable_spi1 = 0;
610
611 /* Choose SPI chip-selects */
612 for (i = 0; i < nr_devices; i++) {
613 if (devices[i].controller_data)
614 cs_pin = (unsigned long) devices[i].controller_data;
615 else if (devices[i].bus_num == 0)
616 cs_pin = spi0_standard_cs[devices[i].chip_select];
617 else
618 cs_pin = spi1_standard_cs[devices[i].chip_select];
619
620 if (devices[i].bus_num == 0)
621 enable_spi0 = 1;
622 else
623 enable_spi1 = 1;
624
625 /* enable chip-select pin */
626 at91_set_gpio_output(cs_pin, 1);
627
628 /* pass chip-select pin to driver */
629 devices[i].controller_data = (void *) cs_pin;
630 }
631
632 spi_register_board_info(devices, nr_devices);
633
634 /* Configure SPI bus(es) */
635 if (enable_spi0) {
636 at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI0_MISO */
637 at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI0_MOSI */
638 at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI0_SPCK */
639
640 at91_clock_associate("spi0_clk", &at91sam9g45_spi0_device.dev, "spi_clk");
641 platform_device_register(&at91sam9g45_spi0_device);
642 }
643 if (enable_spi1) {
644 at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_MISO */
645 at91_set_A_periph(AT91_PIN_PB15, 0); /* SPI1_MOSI */
646 at91_set_A_periph(AT91_PIN_PB16, 0); /* SPI1_SPCK */
647
648 at91_clock_associate("spi1_clk", &at91sam9g45_spi1_device.dev, "spi_clk");
649 platform_device_register(&at91sam9g45_spi1_device);
650 }
651 }
652 #else
653 void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
654 #endif
655
656
657 /* --------------------------------------------------------------------
658 * AC97
659 * -------------------------------------------------------------------- */
660
661 #if defined(CONFIG_SND_ATMEL_AC97C) || defined(CONFIG_SND_ATMEL_AC97C_MODULE)
662 static u64 ac97_dmamask = DMA_BIT_MASK(32);
663 static struct ac97c_platform_data ac97_data;
664
665 static struct resource ac97_resources[] = {
666 [0] = {
667 .start = AT91SAM9G45_BASE_AC97C,
668 .end = AT91SAM9G45_BASE_AC97C + SZ_16K - 1,
669 .flags = IORESOURCE_MEM,
670 },
671 [1] = {
672 .start = AT91SAM9G45_ID_AC97C,
673 .end = AT91SAM9G45_ID_AC97C,
674 .flags = IORESOURCE_IRQ,
675 },
676 };
677
678 static struct platform_device at91sam9g45_ac97_device = {
679 .name = "atmel_ac97c",
680 .id = 0,
681 .dev = {
682 .dma_mask = &ac97_dmamask,
683 .coherent_dma_mask = DMA_BIT_MASK(32),
684 .platform_data = &ac97_data,
685 },
686 .resource = ac97_resources,
687 .num_resources = ARRAY_SIZE(ac97_resources),
688 };
689
690 void __init at91_add_device_ac97(struct ac97c_platform_data *data)
691 {
692 if (!data)
693 return;
694
695 at91_set_A_periph(AT91_PIN_PD8, 0); /* AC97FS */
696 at91_set_A_periph(AT91_PIN_PD9, 0); /* AC97CK */
697 at91_set_A_periph(AT91_PIN_PD7, 0); /* AC97TX */
698 at91_set_A_periph(AT91_PIN_PD6, 0); /* AC97RX */
699
700 /* reset */
701 if (data->reset_pin)
702 at91_set_gpio_output(data->reset_pin, 0);
703
704 ac97_data = *data;
705 platform_device_register(&at91sam9g45_ac97_device);
706 }
707 #else
708 void __init at91_add_device_ac97(struct ac97c_platform_data *data) {}
709 #endif
710
711
712 /* --------------------------------------------------------------------
713 * LCD Controller
714 * -------------------------------------------------------------------- */
715
716 #if defined(CONFIG_FB_ATMEL) || defined(CONFIG_FB_ATMEL_MODULE)
717 static u64 lcdc_dmamask = DMA_BIT_MASK(32);
718 static struct atmel_lcdfb_info lcdc_data;
719
720 static struct resource lcdc_resources[] = {
721 [0] = {
722 .start = AT91SAM9G45_LCDC_BASE,
723 .end = AT91SAM9G45_LCDC_BASE + SZ_4K - 1,
724 .flags = IORESOURCE_MEM,
725 },
726 [1] = {
727 .start = AT91SAM9G45_ID_LCDC,
728 .end = AT91SAM9G45_ID_LCDC,
729 .flags = IORESOURCE_IRQ,
730 },
731 };
732
733 static struct platform_device at91_lcdc_device = {
734 .name = "atmel_lcdfb",
735 .id = 0,
736 .dev = {
737 .dma_mask = &lcdc_dmamask,
738 .coherent_dma_mask = DMA_BIT_MASK(32),
739 .platform_data = &lcdc_data,
740 },
741 .resource = lcdc_resources,
742 .num_resources = ARRAY_SIZE(lcdc_resources),
743 };
744
745 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
746 {
747 if (!data)
748 return;
749
750 at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */
751
752 at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */
753 at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */
754 at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */
755 at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */
756 at91_set_A_periph(AT91_PIN_PE6, 0); /* LCDDEN */
757 at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */
758 at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */
759 at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */
760 at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */
761 at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */
762 at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */
763 at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */
764 at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */
765 at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */
766 at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */
767 at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */
768 at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */
769 at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */
770 at91_set_A_periph(AT91_PIN_PE20, 0); /* LCDD13 */
771 at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */
772 at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */
773 at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */
774 at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */
775 at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */
776 at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */
777 at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */
778 at91_set_A_periph(AT91_PIN_PE28, 0); /* LCDD21 */
779 at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */
780 at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */
781
782 lcdc_data = *data;
783 platform_device_register(&at91_lcdc_device);
784 }
785 #else
786 void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) {}
787 #endif
788
789
790 /* --------------------------------------------------------------------
791 * Timer/Counter block
792 * -------------------------------------------------------------------- */
793
794 #ifdef CONFIG_ATMEL_TCLIB
795 static struct resource tcb0_resources[] = {
796 [0] = {
797 .start = AT91SAM9G45_BASE_TCB0,
798 .end = AT91SAM9G45_BASE_TCB0 + SZ_16K - 1,
799 .flags = IORESOURCE_MEM,
800 },
801 [1] = {
802 .start = AT91SAM9G45_ID_TCB,
803 .end = AT91SAM9G45_ID_TCB,
804 .flags = IORESOURCE_IRQ,
805 },
806 };
807
808 static struct platform_device at91sam9g45_tcb0_device = {
809 .name = "atmel_tcb",
810 .id = 0,
811 .resource = tcb0_resources,
812 .num_resources = ARRAY_SIZE(tcb0_resources),
813 };
814
815 /* TCB1 begins with TC3 */
816 static struct resource tcb1_resources[] = {
817 [0] = {
818 .start = AT91SAM9G45_BASE_TCB1,
819 .end = AT91SAM9G45_BASE_TCB1 + SZ_16K - 1,
820 .flags = IORESOURCE_MEM,
821 },
822 [1] = {
823 .start = AT91SAM9G45_ID_TCB,
824 .end = AT91SAM9G45_ID_TCB,
825 .flags = IORESOURCE_IRQ,
826 },
827 };
828
829 static struct platform_device at91sam9g45_tcb1_device = {
830 .name = "atmel_tcb",
831 .id = 1,
832 .resource = tcb1_resources,
833 .num_resources = ARRAY_SIZE(tcb1_resources),
834 };
835
836 static void __init at91_add_device_tc(void)
837 {
838 /* this chip has one clock and irq for all six TC channels */
839 at91_clock_associate("tcb0_clk", &at91sam9g45_tcb0_device.dev, "t0_clk");
840 platform_device_register(&at91sam9g45_tcb0_device);
841 at91_clock_associate("tcb1_clk", &at91sam9g45_tcb1_device.dev, "t0_clk");
842 platform_device_register(&at91sam9g45_tcb1_device);
843 }
844 #else
845 static void __init at91_add_device_tc(void) { }
846 #endif
847
848
849 /* --------------------------------------------------------------------
850 * RTC
851 * -------------------------------------------------------------------- */
852
853 #if defined(CONFIG_RTC_DRV_AT91RM9200) || defined(CONFIG_RTC_DRV_AT91RM9200_MODULE)
854 static struct platform_device at91sam9g45_rtc_device = {
855 .name = "at91_rtc",
856 .id = -1,
857 .num_resources = 0,
858 };
859
860 static void __init at91_add_device_rtc(void)
861 {
862 platform_device_register(&at91sam9g45_rtc_device);
863 }
864 #else
865 static void __init at91_add_device_rtc(void) {}
866 #endif
867
868
869 /* --------------------------------------------------------------------
870 * Touchscreen
871 * -------------------------------------------------------------------- */
872
873 #if defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC) || \
874 defined(CONFIG_TOUCHSCREEN_ATMEL_TSADCC_MODULE)
875 static u64 tsadcc_dmamask = DMA_BIT_MASK(32);
876 static struct at91_tsadcc_data tsadcc_data;
877
878 static struct resource tsadcc_resources[] = {
879 [0] = {
880 .start = AT91SAM9G45_BASE_TSC,
881 .end = AT91SAM9G45_BASE_TSC + SZ_16K - 1,
882 .flags = IORESOURCE_MEM,
883 },
884 [1] = {
885 .start = AT91SAM9G45_ID_TSC,
886 .end = AT91SAM9G45_ID_TSC,
887 .flags = IORESOURCE_IRQ,
888 }
889 };
890
891 static struct platform_device at91sam9g45_tsadcc_device = {
892 .name = "atmel_tsadcc",
893 .id = -1,
894 .dev = {
895 .dma_mask = &tsadcc_dmamask,
896 .coherent_dma_mask = DMA_BIT_MASK(32),
897 .platform_data = &tsadcc_data,
898 },
899 .resource = tsadcc_resources,
900 .num_resources = ARRAY_SIZE(tsadcc_resources),
901 };
902
903 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data)
904 {
905 if (!data)
906 return;
907
908 at91_set_gpio_input(AT91_PIN_PD20, 0); /* AD0_XR */
909 at91_set_gpio_input(AT91_PIN_PD21, 0); /* AD1_XL */
910 at91_set_gpio_input(AT91_PIN_PD22, 0); /* AD2_YT */
911 at91_set_gpio_input(AT91_PIN_PD23, 0); /* AD3_TB */
912
913 tsadcc_data = *data;
914 platform_device_register(&at91sam9g45_tsadcc_device);
915 }
916 #else
917 void __init at91_add_device_tsadcc(struct at91_tsadcc_data *data) {}
918 #endif
919
920
921 /* --------------------------------------------------------------------
922 * RTT
923 * -------------------------------------------------------------------- */
924
925 static struct resource rtt_resources[] = {
926 {
927 .start = AT91_BASE_SYS + AT91_RTT,
928 .end = AT91_BASE_SYS + AT91_RTT + SZ_16 - 1,
929 .flags = IORESOURCE_MEM,
930 }
931 };
932
933 static struct platform_device at91sam9g45_rtt_device = {
934 .name = "at91_rtt",
935 .id = 0,
936 .resource = rtt_resources,
937 .num_resources = ARRAY_SIZE(rtt_resources),
938 };
939
940 static void __init at91_add_device_rtt(void)
941 {
942 platform_device_register(&at91sam9g45_rtt_device);
943 }
944
945
946 /* --------------------------------------------------------------------
947 * Watchdog
948 * -------------------------------------------------------------------- */
949
950 #if defined(CONFIG_AT91SAM9X_WATCHDOG) || defined(CONFIG_AT91SAM9X_WATCHDOG_MODULE)
951 static struct platform_device at91sam9g45_wdt_device = {
952 .name = "at91_wdt",
953 .id = -1,
954 .num_resources = 0,
955 };
956
957 static void __init at91_add_device_watchdog(void)
958 {
959 platform_device_register(&at91sam9g45_wdt_device);
960 }
961 #else
962 static void __init at91_add_device_watchdog(void) {}
963 #endif
964
965
966 /* --------------------------------------------------------------------
967 * PWM
968 * --------------------------------------------------------------------*/
969
970 #if defined(CONFIG_ATMEL_PWM) || defined(CONFIG_ATMEL_PWM_MODULE)
971 static u32 pwm_mask;
972
973 static struct resource pwm_resources[] = {
974 [0] = {
975 .start = AT91SAM9G45_BASE_PWMC,
976 .end = AT91SAM9G45_BASE_PWMC + SZ_16K - 1,
977 .flags = IORESOURCE_MEM,
978 },
979 [1] = {
980 .start = AT91SAM9G45_ID_PWMC,
981 .end = AT91SAM9G45_ID_PWMC,
982 .flags = IORESOURCE_IRQ,
983 },
984 };
985
986 static struct platform_device at91sam9g45_pwm0_device = {
987 .name = "atmel_pwm",
988 .id = -1,
989 .dev = {
990 .platform_data = &pwm_mask,
991 },
992 .resource = pwm_resources,
993 .num_resources = ARRAY_SIZE(pwm_resources),
994 };
995
996 void __init at91_add_device_pwm(u32 mask)
997 {
998 if (mask & (1 << AT91_PWM0))
999 at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */
1000
1001 if (mask & (1 << AT91_PWM1))
1002 at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */
1003
1004 if (mask & (1 << AT91_PWM2))
1005 at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */
1006
1007 if (mask & (1 << AT91_PWM3))
1008 at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */
1009
1010 pwm_mask = mask;
1011
1012 platform_device_register(&at91sam9g45_pwm0_device);
1013 }
1014 #else
1015 void __init at91_add_device_pwm(u32 mask) {}
1016 #endif
1017
1018
1019 /* --------------------------------------------------------------------
1020 * SSC -- Synchronous Serial Controller
1021 * -------------------------------------------------------------------- */
1022
1023 #if defined(CONFIG_ATMEL_SSC) || defined(CONFIG_ATMEL_SSC_MODULE)
1024 static u64 ssc0_dmamask = DMA_BIT_MASK(32);
1025
1026 static struct resource ssc0_resources[] = {
1027 [0] = {
1028 .start = AT91SAM9G45_BASE_SSC0,
1029 .end = AT91SAM9G45_BASE_SSC0 + SZ_16K - 1,
1030 .flags = IORESOURCE_MEM,
1031 },
1032 [1] = {
1033 .start = AT91SAM9G45_ID_SSC0,
1034 .end = AT91SAM9G45_ID_SSC0,
1035 .flags = IORESOURCE_IRQ,
1036 },
1037 };
1038
1039 static struct platform_device at91sam9g45_ssc0_device = {
1040 .name = "ssc",
1041 .id = 0,
1042 .dev = {
1043 .dma_mask = &ssc0_dmamask,
1044 .coherent_dma_mask = DMA_BIT_MASK(32),
1045 },
1046 .resource = ssc0_resources,
1047 .num_resources = ARRAY_SIZE(ssc0_resources),
1048 };
1049
1050 static inline void configure_ssc0_pins(unsigned pins)
1051 {
1052 if (pins & ATMEL_SSC_TF)
1053 at91_set_A_periph(AT91_PIN_PD1, 1);
1054 if (pins & ATMEL_SSC_TK)
1055 at91_set_A_periph(AT91_PIN_PD0, 1);
1056 if (pins & ATMEL_SSC_TD)
1057 at91_set_A_periph(AT91_PIN_PD2, 1);
1058 if (pins & ATMEL_SSC_RD)
1059 at91_set_A_periph(AT91_PIN_PD3, 1);
1060 if (pins & ATMEL_SSC_RK)
1061 at91_set_A_periph(AT91_PIN_PD4, 1);
1062 if (pins & ATMEL_SSC_RF)
1063 at91_set_A_periph(AT91_PIN_PD5, 1);
1064 }
1065
1066 static u64 ssc1_dmamask = DMA_BIT_MASK(32);
1067
1068 static struct resource ssc1_resources[] = {
1069 [0] = {
1070 .start = AT91SAM9G45_BASE_SSC1,
1071 .end = AT91SAM9G45_BASE_SSC1 + SZ_16K - 1,
1072 .flags = IORESOURCE_MEM,
1073 },
1074 [1] = {
1075 .start = AT91SAM9G45_ID_SSC1,
1076 .end = AT91SAM9G45_ID_SSC1,
1077 .flags = IORESOURCE_IRQ,
1078 },
1079 };
1080
1081 static struct platform_device at91sam9g45_ssc1_device = {
1082 .name = "ssc",
1083 .id = 1,
1084 .dev = {
1085 .dma_mask = &ssc1_dmamask,
1086 .coherent_dma_mask = DMA_BIT_MASK(32),
1087 },
1088 .resource = ssc1_resources,
1089 .num_resources = ARRAY_SIZE(ssc1_resources),
1090 };
1091
1092 static inline void configure_ssc1_pins(unsigned pins)
1093 {
1094 if (pins & ATMEL_SSC_TF)
1095 at91_set_A_periph(AT91_PIN_PD14, 1);
1096 if (pins & ATMEL_SSC_TK)
1097 at91_set_A_periph(AT91_PIN_PD12, 1);
1098 if (pins & ATMEL_SSC_TD)
1099 at91_set_A_periph(AT91_PIN_PD10, 1);
1100 if (pins & ATMEL_SSC_RD)
1101 at91_set_A_periph(AT91_PIN_PD11, 1);
1102 if (pins & ATMEL_SSC_RK)
1103 at91_set_A_periph(AT91_PIN_PD13, 1);
1104 if (pins & ATMEL_SSC_RF)
1105 at91_set_A_periph(AT91_PIN_PD15, 1);
1106 }
1107
1108 /*
1109 * SSC controllers are accessed through library code, instead of any
1110 * kind of all-singing/all-dancing driver. For example one could be
1111 * used by a particular I2S audio codec's driver, while another one
1112 * on the same system might be used by a custom data capture driver.
1113 */
1114 void __init at91_add_device_ssc(unsigned id, unsigned pins)
1115 {
1116 struct platform_device *pdev;
1117
1118 /*
1119 * NOTE: caller is responsible for passing information matching
1120 * "pins" to whatever will be using each particular controller.
1121 */
1122 switch (id) {
1123 case AT91SAM9G45_ID_SSC0:
1124 pdev = &at91sam9g45_ssc0_device;
1125 configure_ssc0_pins(pins);
1126 at91_clock_associate("ssc0_clk", &pdev->dev, "pclk");
1127 break;
1128 case AT91SAM9G45_ID_SSC1:
1129 pdev = &at91sam9g45_ssc1_device;
1130 configure_ssc1_pins(pins);
1131 at91_clock_associate("ssc1_clk", &pdev->dev, "pclk");
1132 break;
1133 default:
1134 return;
1135 }
1136
1137 platform_device_register(pdev);
1138 }
1139
1140 #else
1141 void __init at91_add_device_ssc(unsigned id, unsigned pins) {}
1142 #endif
1143
1144
1145 /* --------------------------------------------------------------------
1146 * UART
1147 * -------------------------------------------------------------------- */
1148
1149 #if defined(CONFIG_SERIAL_ATMEL)
1150 static struct resource dbgu_resources[] = {
1151 [0] = {
1152 .start = AT91_VA_BASE_SYS + AT91_DBGU,
1153 .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
1154 .flags = IORESOURCE_MEM,
1155 },
1156 [1] = {
1157 .start = AT91_ID_SYS,
1158 .end = AT91_ID_SYS,
1159 .flags = IORESOURCE_IRQ,
1160 },
1161 };
1162
1163 static struct atmel_uart_data dbgu_data = {
1164 .use_dma_tx = 0,
1165 .use_dma_rx = 0,
1166 .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
1167 };
1168
1169 static u64 dbgu_dmamask = DMA_BIT_MASK(32);
1170
1171 static struct platform_device at91sam9g45_dbgu_device = {
1172 .name = "atmel_usart",
1173 .id = 0,
1174 .dev = {
1175 .dma_mask = &dbgu_dmamask,
1176 .coherent_dma_mask = DMA_BIT_MASK(32),
1177 .platform_data = &dbgu_data,
1178 },
1179 .resource = dbgu_resources,
1180 .num_resources = ARRAY_SIZE(dbgu_resources),
1181 };
1182
1183 static inline void configure_dbgu_pins(void)
1184 {
1185 at91_set_A_periph(AT91_PIN_PB12, 0); /* DRXD */
1186 at91_set_A_periph(AT91_PIN_PB13, 1); /* DTXD */
1187 }
1188
1189 static struct resource uart0_resources[] = {
1190 [0] = {
1191 .start = AT91SAM9G45_BASE_US0,
1192 .end = AT91SAM9G45_BASE_US0 + SZ_16K - 1,
1193 .flags = IORESOURCE_MEM,
1194 },
1195 [1] = {
1196 .start = AT91SAM9G45_ID_US0,
1197 .end = AT91SAM9G45_ID_US0,
1198 .flags = IORESOURCE_IRQ,
1199 },
1200 };
1201
1202 static struct atmel_uart_data uart0_data = {
1203 .use_dma_tx = 1,
1204 .use_dma_rx = 1,
1205 };
1206
1207 static u64 uart0_dmamask = DMA_BIT_MASK(32);
1208
1209 static struct platform_device at91sam9g45_uart0_device = {
1210 .name = "atmel_usart",
1211 .id = 1,
1212 .dev = {
1213 .dma_mask = &uart0_dmamask,
1214 .coherent_dma_mask = DMA_BIT_MASK(32),
1215 .platform_data = &uart0_data,
1216 },
1217 .resource = uart0_resources,
1218 .num_resources = ARRAY_SIZE(uart0_resources),
1219 };
1220
1221 static inline void configure_usart0_pins(unsigned pins)
1222 {
1223 at91_set_A_periph(AT91_PIN_PB19, 1); /* TXD0 */
1224 at91_set_A_periph(AT91_PIN_PB18, 0); /* RXD0 */
1225
1226 if (pins & ATMEL_UART_RTS)
1227 at91_set_B_periph(AT91_PIN_PB17, 0); /* RTS0 */
1228 if (pins & ATMEL_UART_CTS)
1229 at91_set_B_periph(AT91_PIN_PB15, 0); /* CTS0 */
1230 }
1231
1232 static struct resource uart1_resources[] = {
1233 [0] = {
1234 .start = AT91SAM9G45_BASE_US1,
1235 .end = AT91SAM9G45_BASE_US1 + SZ_16K - 1,
1236 .flags = IORESOURCE_MEM,
1237 },
1238 [1] = {
1239 .start = AT91SAM9G45_ID_US1,
1240 .end = AT91SAM9G45_ID_US1,
1241 .flags = IORESOURCE_IRQ,
1242 },
1243 };
1244
1245 static struct atmel_uart_data uart1_data = {
1246 .use_dma_tx = 1,
1247 .use_dma_rx = 1,
1248 };
1249
1250 static u64 uart1_dmamask = DMA_BIT_MASK(32);
1251
1252 static struct platform_device at91sam9g45_uart1_device = {
1253 .name = "atmel_usart",
1254 .id = 2,
1255 .dev = {
1256 .dma_mask = &uart1_dmamask,
1257 .coherent_dma_mask = DMA_BIT_MASK(32),
1258 .platform_data = &uart1_data,
1259 },
1260 .resource = uart1_resources,
1261 .num_resources = ARRAY_SIZE(uart1_resources),
1262 };
1263
1264 static inline void configure_usart1_pins(unsigned pins)
1265 {
1266 at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD1 */
1267 at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD1 */
1268
1269 if (pins & ATMEL_UART_RTS)
1270 at91_set_A_periph(AT91_PIN_PD16, 0); /* RTS1 */
1271 if (pins & ATMEL_UART_CTS)
1272 at91_set_A_periph(AT91_PIN_PD17, 0); /* CTS1 */
1273 }
1274
1275 static struct resource uart2_resources[] = {
1276 [0] = {
1277 .start = AT91SAM9G45_BASE_US2,
1278 .end = AT91SAM9G45_BASE_US2 + SZ_16K - 1,
1279 .flags = IORESOURCE_MEM,
1280 },
1281 [1] = {
1282 .start = AT91SAM9G45_ID_US2,
1283 .end = AT91SAM9G45_ID_US2,
1284 .flags = IORESOURCE_IRQ,
1285 },
1286 };
1287
1288 static struct atmel_uart_data uart2_data = {
1289 .use_dma_tx = 1,
1290 .use_dma_rx = 1,
1291 };
1292
1293 static u64 uart2_dmamask = DMA_BIT_MASK(32);
1294
1295 static struct platform_device at91sam9g45_uart2_device = {
1296 .name = "atmel_usart",
1297 .id = 3,
1298 .dev = {
1299 .dma_mask = &uart2_dmamask,
1300 .coherent_dma_mask = DMA_BIT_MASK(32),
1301 .platform_data = &uart2_data,
1302 },
1303 .resource = uart2_resources,
1304 .num_resources = ARRAY_SIZE(uart2_resources),
1305 };
1306
1307 static inline void configure_usart2_pins(unsigned pins)
1308 {
1309 at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD2 */
1310 at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD2 */
1311
1312 if (pins & ATMEL_UART_RTS)
1313 at91_set_B_periph(AT91_PIN_PC9, 0); /* RTS2 */
1314 if (pins & ATMEL_UART_CTS)
1315 at91_set_B_periph(AT91_PIN_PC11, 0); /* CTS2 */
1316 }
1317
1318 static struct resource uart3_resources[] = {
1319 [0] = {
1320 .start = AT91SAM9G45_BASE_US3,
1321 .end = AT91SAM9G45_BASE_US3 + SZ_16K - 1,
1322 .flags = IORESOURCE_MEM,
1323 },
1324 [1] = {
1325 .start = AT91SAM9G45_ID_US3,
1326 .end = AT91SAM9G45_ID_US3,
1327 .flags = IORESOURCE_IRQ,
1328 },
1329 };
1330
1331 static struct atmel_uart_data uart3_data = {
1332 .use_dma_tx = 1,
1333 .use_dma_rx = 1,
1334 };
1335
1336 static u64 uart3_dmamask = DMA_BIT_MASK(32);
1337
1338 static struct platform_device at91sam9g45_uart3_device = {
1339 .name = "atmel_usart",
1340 .id = 4,
1341 .dev = {
1342 .dma_mask = &uart3_dmamask,
1343 .coherent_dma_mask = DMA_BIT_MASK(32),
1344 .platform_data = &uart3_data,
1345 },
1346 .resource = uart3_resources,
1347 .num_resources = ARRAY_SIZE(uart3_resources),
1348 };
1349
1350 static inline void configure_usart3_pins(unsigned pins)
1351 {
1352 at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD3 */
1353 at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD3 */
1354
1355 if (pins & ATMEL_UART_RTS)
1356 at91_set_B_periph(AT91_PIN_PA23, 0); /* RTS3 */
1357 if (pins & ATMEL_UART_CTS)
1358 at91_set_B_periph(AT91_PIN_PA24, 0); /* CTS3 */
1359 }
1360
1361 static struct platform_device *__initdata at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
1362 struct platform_device *atmel_default_console_device; /* the serial console device */
1363
1364 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins)
1365 {
1366 struct platform_device *pdev;
1367
1368 switch (id) {
1369 case 0: /* DBGU */
1370 pdev = &at91sam9g45_dbgu_device;
1371 configure_dbgu_pins();
1372 at91_clock_associate("mck", &pdev->dev, "usart");
1373 break;
1374 case AT91SAM9G45_ID_US0:
1375 pdev = &at91sam9g45_uart0_device;
1376 configure_usart0_pins(pins);
1377 at91_clock_associate("usart0_clk", &pdev->dev, "usart");
1378 break;
1379 case AT91SAM9G45_ID_US1:
1380 pdev = &at91sam9g45_uart1_device;
1381 configure_usart1_pins(pins);
1382 at91_clock_associate("usart1_clk", &pdev->dev, "usart");
1383 break;
1384 case AT91SAM9G45_ID_US2:
1385 pdev = &at91sam9g45_uart2_device;
1386 configure_usart2_pins(pins);
1387 at91_clock_associate("usart2_clk", &pdev->dev, "usart");
1388 break;
1389 case AT91SAM9G45_ID_US3:
1390 pdev = &at91sam9g45_uart3_device;
1391 configure_usart3_pins(pins);
1392 at91_clock_associate("usart3_clk", &pdev->dev, "usart");
1393 break;
1394 default:
1395 return;
1396 }
1397 pdev->id = portnr; /* update to mapped ID */
1398
1399 if (portnr < ATMEL_MAX_UART)
1400 at91_uarts[portnr] = pdev;
1401 }
1402
1403 void __init at91_set_serial_console(unsigned portnr)
1404 {
1405 if (portnr < ATMEL_MAX_UART)
1406 atmel_default_console_device = at91_uarts[portnr];
1407 }
1408
1409 void __init at91_add_device_serial(void)
1410 {
1411 int i;
1412
1413 for (i = 0; i < ATMEL_MAX_UART; i++) {
1414 if (at91_uarts[i])
1415 platform_device_register(at91_uarts[i]);
1416 }
1417
1418 if (!atmel_default_console_device)
1419 printk(KERN_INFO "AT91: No default serial console defined.\n");
1420 }
1421 #else
1422 void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins) {}
1423 void __init at91_set_serial_console(unsigned portnr) {}
1424 void __init at91_add_device_serial(void) {}
1425 #endif
1426
1427
1428 /* -------------------------------------------------------------------- */
1429 /*
1430 * These devices are always present and don't need any board-specific
1431 * setup.
1432 */
1433 static int __init at91_add_standard_devices(void)
1434 {
1435 at91_add_device_hdmac();
1436 at91_add_device_rtc();
1437 at91_add_device_rtt();
1438 at91_add_device_watchdog();
1439 at91_add_device_tc();
1440 return 0;
1441 }
1442
1443 arch_initcall(at91_add_standard_devices);
Tomato firmware and modifications.