1 /* Modified by Broadcom Corp. Portions Copyright (c) Broadcom Corp, 2012. */
3 * linux/arch/arm/kernel/entry-armv.S
5 * Copyright (C) 1996,1997,1998 Russell King.
6 * ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
7 * nommu support by Hyok S. Choi (hyok.choi@samsung.com)
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * Low-level vector interface routines
15 * Note: there is a StrongARM bug in the STMIA rn, {regs}^ instruction
16 * that causes it to save wrong values... Be aware!
19 #include <asm/memory.h>
21 #include <asm/vfpmacros.h>
22 #include <mach/entry-macro.S>
23 #include <asm/thread_notify.h>
24 #include <asm/unwind.h>
25 #include <asm/unistd.h>
28 #include "entry-header.S"
31 * Interrupt handling. Preserves r7, r8, r9
34 get_irqnr_preamble r5, lr
35 1: get_irqnr_and_base r0, r6, r5, lr
38 @ routine called with r0 = irq number, r1 = struct pt_regs *
44 test_for_ipi r0, r6, r5, lr
49 #ifdef CONFIG_LOCAL_TIMERS
50 test_for_ltirq r0, r6, r5, lr
60 .section .kprobes.text,"ax",%progbits
63 .section .text.fastpath, "a"
67 * Invalid mode handlers
69 .macro inv_entry, reason
70 sub sp, sp, #S_FRAME_SIZE
71 ARM( stmib sp, {r1 - lr} )
72 THUMB( stmia sp, {r0 - r12} )
73 THUMB( str sp, [sp, #S_SP] )
74 THUMB( str lr, [sp, #S_LR] )
79 inv_entry BAD_PREFETCH
81 ENDPROC(__pabt_invalid)
86 ENDPROC(__dabt_invalid)
91 ENDPROC(__irq_invalid)
94 inv_entry BAD_UNDEFINSTR
97 @ XXX fall through to common_invalid
101 @ common_invalid - generic code for failed exception (re-entrant version of handlers)
107 add r0, sp, #S_PC @ here for interlock avoidance
108 mov r7, #-1 @ "" "" "" ""
109 str r4, [sp] @ save preserved r0
110 stmia r0, {r5 - r7} @ lr_<exception>,
111 @ cpsr_<exception>, "old_r0"
115 ENDPROC(__und_invalid)
121 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5)
122 #define SPFIX(code...) code
124 #define SPFIX(code...)
127 .macro svc_entry, stack_hole=0
129 UNWIND(.save {r0 - pc} )
130 sub sp, sp, #(S_FRAME_SIZE + \stack_hole - 4)
131 #ifdef CONFIG_THUMB2_KERNEL
132 SPFIX( str r0, [sp] ) @ temporarily saved
134 SPFIX( tst r0, #4 ) @ test original stack alignment
135 SPFIX( ldr r0, [sp] ) @ restored
139 SPFIX( subeq sp, sp, #4 )
143 add r5, sp, #S_SP - 4 @ here for interlock avoidance
144 mov r4, #-1 @ "" "" "" ""
145 add r0, sp, #(S_FRAME_SIZE + \stack_hole - 4)
146 SPFIX( addeq r0, r0, #4 )
147 str r1, [sp, #-4]! @ save the "real" r0 copied
148 @ from the exception stack
153 @ We are now ready to fill in the remaining blanks on the stack:
157 @ r2 - lr_<exception>, already fixed up for correct return/restart
158 @ r3 - spsr_<exception>
159 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
169 @ get ready to re-enable interrupts if appropriate
173 biceq r9, r9, #PSR_I_BIT
176 @ Call the processor-specific abort handler:
178 @ r2 - aborted context pc
179 @ r3 - aborted context cpsr
181 @ The abort handler must return the aborted address in r0, and
182 @ the fault status register in r1. r9 must be preserved.
187 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
189 bl CPU_DABORT_HANDLER
193 @ set desired IRQ state, then call main handler
200 @ IRQs off again before pulling preserved data off the stack
205 @ restore SPSR and restart the instruction
208 svc_exit r2 @ return from exception
216 #ifdef CONFIG_TRACE_IRQFLAGS
217 bl trace_hardirqs_off
219 #ifdef CONFIG_PREEMPT
221 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
222 add r7, r8, #1 @ increment it
223 str r7, [tsk, #TI_PREEMPT]
227 #ifdef CONFIG_PREEMPT
228 str r8, [tsk, #TI_PREEMPT] @ restore preempt count
229 ldr r0, [tsk, #TI_FLAGS] @ get flags
230 teq r8, #0 @ if preempt count != 0
231 movne r0, #0 @ force flags to 0
232 tst r0, #_TIF_NEED_RESCHED
235 ldr r4, [sp, #S_PSR] @ irqs are already disabled
236 #ifdef CONFIG_TRACE_IRQFLAGS
238 bleq trace_hardirqs_on
240 svc_exit r4 @ return from exception
246 #ifdef CONFIG_PREEMPT
249 1: bl preempt_schedule_irq @ irq en/disable is done inside
250 ldr r0, [tsk, #TI_FLAGS] @ get new tasks TI_FLAGS
251 tst r0, #_TIF_NEED_RESCHED
252 moveq pc, r8 @ go again
258 #ifdef CONFIG_KPROBES
259 @ If a kprobe is about to simulate a "stmdb sp..." instruction,
260 @ it obviously needs free stack space which then will belong to
268 @ call emulation code, which returns using r9 if it has emulated
269 @ the instruction, or the more conventional lr if we are to treat
270 @ this as a real undefined instruction
274 #ifndef CONFIG_THUMB2_KERNEL
277 ldrh r0, [r2, #-2] @ Thumb instruction at LR - 2
279 cmp r9, #0xe800 @ 32-bit instruction if xx >= 0
280 ldrhhs r9, [r2] @ bottom 16 bits
281 orrhs r0, r9, r0, lsl #16
286 mov r0, sp @ struct pt_regs *regs
290 @ IRQs off again before pulling preserved data off the stack
292 1: disable_irq_notrace
295 @ restore SPSR and restart the instruction
297 ldr r2, [sp, #S_PSR] @ Get SVC cpsr
298 svc_exit r2 @ return from exception
307 @ re-enable interrupts if appropriate
311 biceq r9, r9, #PSR_I_BIT
313 mov r0, r2 @ pass address of aborted instruction.
317 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
319 bl CPU_PABORT_HANDLER
321 msr cpsr_c, r9 @ Maybe enable interrupts
323 bl do_PrefetchAbort @ call abort handler
326 @ IRQs off again before pulling preserved data off the stack
331 @ restore SPSR and restart the instruction
334 svc_exit r2 @ return from exception
351 * EABI note: sp_svc is always 64-bit aligned here, so should S_FRAME_SIZE
354 #if defined(CONFIG_AEABI) && (__LINUX_ARM_ARCH__ >= 5) && (S_FRAME_SIZE & 7)
355 #error "sizeof(struct pt_regs) must be a multiple of 8"
360 UNWIND(.cantunwind ) @ don't unwind the user space
361 sub sp, sp, #S_FRAME_SIZE
362 ARM( stmib sp, {r1 - r12} )
363 THUMB( stmia sp, {r0 - r12} )
366 add r0, sp, #S_PC @ here for interlock avoidance
367 mov r4, #-1 @ "" "" "" ""
369 str r1, [sp] @ save the "real" r0 copied
370 @ from the exception stack
373 @ We are now ready to fill in the remaining blanks on the stack:
375 @ r2 - lr_<exception>, already fixed up for correct return/restart
376 @ r3 - spsr_<exception>
377 @ r4 - orig_r0 (see pt_regs definition in ptrace.h)
379 @ Also, separately save sp_usr and lr_usr
382 ARM( stmdb r0, {sp, lr}^ )
383 THUMB( store_user_sp_lr r0, r1, S_SP - S_PC )
386 @ Enable the alignment trap while in kernel mode
391 @ Clear FP to mark the first stack frame
396 .macro kuser_cmpxchg_check
397 #if __LINUX_ARM_ARCH__ < 6 && !defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
399 #warning "NPTL on non MMU needs fixing"
401 @ Make sure our user space atomic helper is restarted
402 @ if it was interrupted in a critical region. Here we
403 @ perform a quick test inline since it should be false
404 @ 99.9999% of the time. The rest is done out of line.
406 blhs kuser_cmpxchg_fixup
417 @ Call the processor-specific abort handler:
419 @ r2 - aborted context pc
420 @ r3 - aborted context cpsr
422 @ The abort handler must return the aborted address in r0, and
423 @ the fault status register in r1.
428 ldr pc, [r4, #PROCESSOR_DABT_FUNC]
430 bl CPU_DABORT_HANDLER
434 @ IRQs on, then call the main handler
438 adr lr, BSYM(ret_from_exception)
449 #ifdef CONFIG_PREEMPT
450 ldr r8, [tsk, #TI_PREEMPT] @ get preempt count
451 add r7, r8, #1 @ increment it
452 str r7, [tsk, #TI_PREEMPT]
456 #ifdef CONFIG_PREEMPT
457 ldr r0, [tsk, #TI_PREEMPT]
458 str r8, [tsk, #TI_PREEMPT]
460 ARM( strne r0, [r0, -r0] )
461 THUMB( movne r0, #0 )
462 THUMB( strne r0, [r0] )
477 @ fall through to the emulation code, which returns using r9 if
478 @ it has emulated the instruction, or the more conventional lr
479 @ if we are to treat this as a real undefined instruction
483 adr r9, BSYM(ret_from_exception)
484 adr lr, BSYM(__und_usr_unknown)
485 tst r3, #PSR_T_BIT @ Thumb mode?
486 itet eq @ explicit IT needed for the 1f label
487 subeq r4, r2, #4 @ ARM instr at LR - 4
488 subne r4, r2, #2 @ Thumb instr at LR - 2
490 #ifdef CONFIG_CPU_ENDIAN_BE8
491 reveq r0, r0 @ little endian instruction
495 #if __LINUX_ARM_ARCH__ >= 7
497 ARM( ldrht r5, [r4], #2 )
498 THUMB( ldrht r5, [r4] )
499 THUMB( add r4, r4, #2 )
500 and r0, r5, #0xf800 @ mask bits 111x x... .... ....
501 cmp r0, #0xe800 @ 32bit instruction if xx != 0
502 blo __und_usr_unknown
504 add r2, r2, #2 @ r2 is PC + 2, make it PC + 4
505 orr r0, r0, r5, lsl #16
513 @ fallthrough to call_fpe
517 * The out of line fixup for the ldrt above.
519 .pushsection .fixup, "ax"
522 .pushsection __ex_table,"a"
524 #if __LINUX_ARM_ARCH__ >= 7
531 * Check whether the instruction is a co-processor instruction.
532 * If yes, we need to call the relevant co-processor handler.
534 * Note that we don't do a full check here for the co-processor
535 * instructions; all instructions with bit 27 set are well
536 * defined. The only instructions that should fault are the
537 * co-processor instructions. However, we have to watch out
538 * for the ARM6/ARM7 SWI bug.
540 * NEON is a special case that has to be handled here. Not all
541 * NEON instructions are co-processor instructions, so we have
542 * to make a special case of checking for them. Plus, there's
543 * five groups of them, so we have a table of mask/opcode pairs
544 * to check against, and if any match then we branch off into the
547 * Emulators may wish to make use of the following registers:
548 * r0 = instruction opcode.
550 * r9 = normal "successful" return address
551 * r10 = this threads thread_info structure.
552 * lr = unrecognised instruction return address
555 @ Fall-through from Thumb-2 __und_usr
558 adr r6, .LCneon_thumb_opcodes
563 adr r6, .LCneon_arm_opcodes
565 ldr r7, [r6], #4 @ mask value
566 cmp r7, #0 @ end mask?
569 ldr r7, [r6], #4 @ opcode bits matching in mask
570 cmp r8, r7 @ NEON instruction?
574 strb r7, [r10, #TI_USED_CP + 10] @ mark CP#10 as used
575 strb r7, [r10, #TI_USED_CP + 11] @ mark CP#11 as used
576 b do_vfp @ let VFP handler handle this
579 tst r0, #0x08000000 @ only CDP/CPRT/LDC/STC have bit 27
580 tstne r0, #0x04000000 @ bit 26 set on both ARM and Thumb-2
581 #if defined(CONFIG_CPU_ARM610) || defined(CONFIG_CPU_ARM710)
582 and r8, r0, #0x0f000000 @ mask out op-code bits
583 teqne r8, #0x0f000000 @ SWI (ARM6/7 bug)?
586 get_thread_info r10 @ get current thread
587 and r8, r0, #0x00000f00 @ mask out CP number
588 THUMB( lsr r8, r8, #8 )
590 add r6, r10, #TI_USED_CP
591 ARM( strb r7, [r6, r8, lsr #8] ) @ set appropriate used_cp[]
592 THUMB( strb r7, [r6, r8] ) @ set appropriate used_cp[]
594 @ Test if we need to give access to iWMMXt coprocessors
595 ldr r5, [r10, #TI_FLAGS]
596 rsbs r7, r8, #(1 << 8) @ CP 0 or 1 only
597 movcss r7, r5, lsr #(TIF_USING_IWMMXT + 1)
598 bcs iwmmxt_task_enable
600 ARM( add pc, pc, r8, lsr #6 )
601 THUMB( lsl r8, r8, #2 )
606 W(b) do_fpe @ CP#1 (FPE)
607 W(b) do_fpe @ CP#2 (FPE)
610 b crunch_task_enable @ CP#4 (MaverickCrunch)
611 b crunch_task_enable @ CP#5 (MaverickCrunch)
612 b crunch_task_enable @ CP#6 (MaverickCrunch)
622 W(b) do_vfp @ CP#10 (VFP)
623 W(b) do_vfp @ CP#11 (VFP)
625 movw_pc lr @ CP#10 (VFP)
626 movw_pc lr @ CP#11 (VFP)
630 movw_pc lr @ CP#14 (Debug)
631 movw_pc lr @ CP#15 (Control)
637 .word 0xfe000000 @ mask
638 .word 0xf2000000 @ opcode
640 .word 0xff100000 @ mask
641 .word 0xf4000000 @ opcode
643 .word 0x00000000 @ mask
644 .word 0x00000000 @ opcode
646 .LCneon_thumb_opcodes:
647 .word 0xef000000 @ mask
648 .word 0xef000000 @ opcode
650 .word 0xff100000 @ mask
651 .word 0xf9000000 @ opcode
653 .word 0x00000000 @ mask
654 .word 0x00000000 @ opcode
660 add r10, r10, #TI_FPSTATE @ r10 = workspace
661 ldr pc, [r4] @ Call FP module USR entry point
664 * The FP module is called with these registers set:
667 * r9 = normal "successful" return address
669 * lr = unrecognised FP instruction return address
684 adr lr, BSYM(ret_from_exception)
686 ENDPROC(__und_usr_unknown)
692 mov r0, r2 @ pass address of aborted instruction.
696 ldr pc, [r4, #PROCESSOR_PABT_FUNC]
698 bl CPU_PABORT_HANDLER
700 enable_irq @ Enable interrupts
702 bl do_PrefetchAbort @ call abort handler
706 * This is the return code to user mode for abort handlers
708 ENTRY(ret_from_exception)
716 ENDPROC(ret_from_exception)
719 * Register switch for ARMv3 and ARMv4 processors
720 * r0 = previous task_struct, r1 = previous thread_info, r2 = next thread_info
721 * previous and next are guaranteed not to be the same.
726 add ip, r1, #TI_CPU_SAVE
727 ldr r3, [r2, #TI_TP_VALUE]
728 ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
729 THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
730 THUMB( str sp, [ip], #4 )
731 THUMB( str lr, [ip], #4 )
733 ldr r6, [r2, #TI_CPU_DOMAIN]
736 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
737 ldr r7, [r2, #TI_TASK]
738 ldr r8, =__stack_chk_guard
739 ldr r7, [r7, #TSK_STACK_CANARY]
742 mcr p15, 0, r6, c3, c0, 0 @ Set domain register
745 add r4, r2, #TI_CPU_SAVE
746 ldr r0, =thread_notify_head
747 mov r1, #THREAD_NOTIFY_SWITCH
748 bl atomic_notifier_call_chain
749 #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
754 ARM( ldmia r4, {r4 - sl, fp, sp, pc} ) @ Load all regs saved previously
755 THUMB( ldmia ip!, {r4 - sl, fp} ) @ Load all regs saved previously
756 THUMB( ldr sp, [ip], #4 )
757 THUMB( ldr pc, [ip] )
766 * These are segment of kernel provided user code reachable from user space
767 * at a fixed address in kernel memory. This is used to provide user space
768 * with some operations which require kernel help because of unimplemented
769 * native feature and/or instructions in many ARM CPUs. The idea is for
770 * this code to be executed directly in user mode for best efficiency but
771 * which is too intimate with the kernel counter part to be left to user
772 * libraries. In fact this code might even differ from one CPU to another
773 * depending on the available instruction set and restrictions like on
774 * SMP systems. In other words, the kernel reserves the right to change
775 * this code as needed without warning. Only the entry points and their
776 * results are guaranteed to be stable.
778 * Each segment is 32-byte aligned and will be moved to the top of the high
779 * vector page. New segments (if ever needed) must be added in front of
780 * existing ones. This mechanism should be used only for things that are
781 * really small and justified, and not be abused freely.
783 * User space is expected to implement those things inline when optimizing
784 * for a processor that has the necessary native support, but only if such
785 * resulting binaries are already to be incompatible with earlier ARM
786 * processors due to the use of unsupported instructions other than what
787 * is provided here. In other words don't make binaries unable to run on
788 * earlier processors just for the sake of not using these kernel helpers
789 * if your compiled code is not going to use the new instructions for other
795 #ifdef CONFIG_ARM_THUMB
803 .globl __kuser_helper_start
804 __kuser_helper_start:
807 * Reference prototype:
809 * void __kernel_memory_barrier(void)
813 * lr = return address
823 * Definition and user space usage example:
825 * typedef void (__kernel_dmb_t)(void);
826 * #define __kernel_dmb (*(__kernel_dmb_t *)0xffff0fa0)
828 * Apply any needed memory barrier to preserve consistency with data modified
829 * manually and __kuser_cmpxchg usage.
831 * This could be used as follows:
833 * #define __kernel_dmb() \
834 * asm volatile ( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #95" \
835 * : : : "r0", "lr","cc" )
838 __kuser_memory_barrier: @ 0xffff0fa0
845 * Reference prototype:
847 * int __kernel_cmpxchg(int oldval, int newval, int *ptr)
854 * lr = return address
858 * r0 = returned value (zero or non-zero)
859 * C flag = set if r0 == 0, clear if r0 != 0
865 * Definition and user space usage example:
867 * typedef int (__kernel_cmpxchg_t)(int oldval, int newval, int *ptr);
868 * #define __kernel_cmpxchg (*(__kernel_cmpxchg_t *)0xffff0fc0)
870 * Atomically store newval in *ptr if *ptr is equal to oldval for user space.
871 * Return zero if *ptr was changed or non-zero if no exchange happened.
872 * The C flag is also set if *ptr was changed to allow for assembly
873 * optimization in the calling code.
877 * - This routine already includes memory barriers as needed.
879 * For example, a user space atomic_add implementation could look like this:
881 * #define atomic_add(ptr, val) \
882 * ({ register unsigned int *__ptr asm("r2") = (ptr); \
883 * register unsigned int __result asm("r1"); \
885 * "1: @ atomic_add\n\t" \
886 * "ldr r0, [r2]\n\t" \
887 * "mov r3, #0xffff0fff\n\t" \
888 * "add lr, pc, #4\n\t" \
889 * "add r1, r0, %2\n\t" \
890 * "add pc, r3, #(0xffff0fc0 - 0xffff0fff)\n\t" \
892 * : "=&r" (__result) \
893 * : "r" (__ptr), "rIL" (val) \
894 * : "r0","r3","ip","lr","cc","memory" ); \
898 __kuser_cmpxchg: @ 0xffff0fc0
900 #if defined(CONFIG_NEEDS_SYSCALL_FOR_CMPXCHG)
903 * Poor you. No fast solution possible...
904 * The kernel itself must perform the operation.
905 * A special ghost syscall is used for that (see traps.c).
908 ldr r7, =1f @ it's 20 bits
911 1: .word __ARM_NR_cmpxchg
913 #elif __LINUX_ARM_ARCH__ < 6
918 * The only thing that can break atomicity in this cmpxchg
919 * implementation is either an IRQ or a data abort exception
920 * causing another process/thread to be scheduled in the middle
921 * of the critical sequence. To prevent this, code is added to
922 * the IRQ and data abort exception handlers to set the pc back
923 * to the beginning of the critical section if it is found to be
924 * within that critical section (see kuser_cmpxchg_fixup).
926 1: ldr r3, [r2] @ load current val
927 subs r3, r3, r0 @ compare with oldval
928 2: streq r1, [r2] @ store newval if eq
929 rsbs r0, r3, #0 @ set return val and C flag
934 @ Called from kuser_cmpxchg_check macro.
935 @ r2 = address of interrupted insn (must be preserved).
936 @ sp = saved regs. r7 and r8 are clobbered.
937 @ 1b = first critical insn, 2b = last critical insn.
938 @ If r2 >= 1b and r2 <= 2b then saved pc_usr is set to 1b.
940 sub r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
942 rsbcss r8, r8, #(2b - 1b)
943 strcs r7, [sp, #S_PC]
948 #warning "NPTL on non MMU needs fixing"
963 /* beware -- each __kuser slot must be 8 instructions max */
965 b __kuser_memory_barrier
975 * Reference prototype:
977 * int __kernel_get_tls(void)
981 * lr = return address
991 * Definition and user space usage example:
993 * typedef int (__kernel_get_tls_t)(void);
994 * #define __kernel_get_tls (*(__kernel_get_tls_t *)0xffff0fe0)
996 * Get the TLS value as previously set via the __ARM_NR_set_tls syscall.
998 * This could be used as follows:
1000 * #define __kernel_get_tls() \
1001 * ({ register unsigned int __val asm("r0"); \
1002 * asm( "mov r0, #0xffff0fff; mov lr, pc; sub pc, r0, #31" \
1003 * : "=r" (__val) : : "lr","cc" ); \
1007 __kuser_get_tls: @ 0xffff0fe0
1008 ldr r0, [pc, #(16 - 8)] @ read TLS, set in kuser_get_tls_init
1010 mrc p15, 0, r0, c13, c0, 3 @ 0xffff0fe8 hardware TLS code
1012 .word 0 @ 0xffff0ff0 software TLS value, then
1013 .endr @ pad up to __kuser_helper_version
1016 * Reference declaration:
1018 * extern unsigned int __kernel_helper_version;
1020 * Definition and user space usage example:
1022 * #define __kernel_helper_version (*(unsigned int *)0xffff0ffc)
1024 * User space may read this to determine the curent number of helpers
1028 __kuser_helper_version: @ 0xffff0ffc
1029 .word ((__kuser_helper_end - __kuser_helper_start) >> 5)
1031 .globl __kuser_helper_end
1039 * This code is copied to 0xffff0200 so we can use branches in the
1040 * vectors, rather than ldr's. Note that this code must not
1041 * exceed 0x300 bytes.
1043 * Common stub entry macro:
1044 * Enter in IRQ mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1046 * SP points to a minimal amount of processor-private memory, the address
1047 * of which is copied into r0 for the mode specific abort handler.
1049 .macro vector_stub, name, mode, correction=0
1054 sub lr, lr, #\correction
1058 @ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1061 stmia sp, {r0, lr} @ save r0, lr
1063 str lr, [sp, #8] @ save spsr
1066 @ Prepare for SVC32 mode. IRQs remain disabled.
1069 eor r0, r0, #(\mode ^ SVC_MODE | PSR_ISETSTATE)
1073 @ the branch table must immediately follow this code
1077 THUMB( ldr lr, [r0, lr, lsl #2] )
1079 ARM( ldr lr, [pc, lr, lsl #2] )
1080 movs pc, lr @ branch to handler in SVC mode
1081 ENDPROC(vector_\name)
1084 @ handler addresses follow this label
1088 .globl __stubs_start
1091 * Interrupt dispatcher
1093 vector_stub irq, IRQ_MODE, 4
1095 .long __irq_usr @ 0 (USR_26 / USR_32)
1096 .long __irq_invalid @ 1 (FIQ_26 / FIQ_32)
1097 .long __irq_invalid @ 2 (IRQ_26 / IRQ_32)
1098 .long __irq_svc @ 3 (SVC_26 / SVC_32)
1099 .long __irq_invalid @ 4
1100 .long __irq_invalid @ 5
1101 .long __irq_invalid @ 6
1102 .long __irq_invalid @ 7
1103 .long __irq_invalid @ 8
1104 .long __irq_invalid @ 9
1105 .long __irq_invalid @ a
1106 .long __irq_invalid @ b
1107 .long __irq_invalid @ c
1108 .long __irq_invalid @ d
1109 .long __irq_invalid @ e
1110 .long __irq_invalid @ f
1113 * Data abort dispatcher
1114 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1116 vector_stub dabt, ABT_MODE, 8
1118 .long __dabt_usr @ 0 (USR_26 / USR_32)
1119 .long __dabt_invalid @ 1 (FIQ_26 / FIQ_32)
1120 .long __dabt_invalid @ 2 (IRQ_26 / IRQ_32)
1121 .long __dabt_svc @ 3 (SVC_26 / SVC_32)
1122 .long __dabt_invalid @ 4
1123 .long __dabt_invalid @ 5
1124 .long __dabt_invalid @ 6
1125 .long __dabt_invalid @ 7
1126 .long __dabt_invalid @ 8
1127 .long __dabt_invalid @ 9
1128 .long __dabt_invalid @ a
1129 .long __dabt_invalid @ b
1130 .long __dabt_invalid @ c
1131 .long __dabt_invalid @ d
1132 .long __dabt_invalid @ e
1133 .long __dabt_invalid @ f
1136 * Prefetch abort dispatcher
1137 * Enter in ABT mode, spsr = USR CPSR, lr = USR PC
1139 vector_stub pabt, ABT_MODE, 4
1141 .long __pabt_usr @ 0 (USR_26 / USR_32)
1142 .long __pabt_invalid @ 1 (FIQ_26 / FIQ_32)
1143 .long __pabt_invalid @ 2 (IRQ_26 / IRQ_32)
1144 .long __pabt_svc @ 3 (SVC_26 / SVC_32)
1145 .long __pabt_invalid @ 4
1146 .long __pabt_invalid @ 5
1147 .long __pabt_invalid @ 6
1148 .long __pabt_invalid @ 7
1149 .long __pabt_invalid @ 8
1150 .long __pabt_invalid @ 9
1151 .long __pabt_invalid @ a
1152 .long __pabt_invalid @ b
1153 .long __pabt_invalid @ c
1154 .long __pabt_invalid @ d
1155 .long __pabt_invalid @ e
1156 .long __pabt_invalid @ f
1159 * Undef instr entry dispatcher
1160 * Enter in UND mode, spsr = SVC/USR CPSR, lr = SVC/USR PC
1162 vector_stub und, UND_MODE
1164 .long __und_usr @ 0 (USR_26 / USR_32)
1165 .long __und_invalid @ 1 (FIQ_26 / FIQ_32)
1166 .long __und_invalid @ 2 (IRQ_26 / IRQ_32)
1167 .long __und_svc @ 3 (SVC_26 / SVC_32)
1168 .long __und_invalid @ 4
1169 .long __und_invalid @ 5
1170 .long __und_invalid @ 6
1171 .long __und_invalid @ 7
1172 .long __und_invalid @ 8
1173 .long __und_invalid @ 9
1174 .long __und_invalid @ a
1175 .long __und_invalid @ b
1176 .long __und_invalid @ c
1177 .long __und_invalid @ d
1178 .long __und_invalid @ e
1179 .long __und_invalid @ f
1183 /*=============================================================================
1185 *-----------------------------------------------------------------------------
1186 * Enter in FIQ mode, spsr = ANY CPSR, lr = ANY PC
1187 * MUST PRESERVE SVC SPSR, but need to switch to SVC mode to show our msg.
1188 * Basically to switch modes, we *HAVE* to clobber one register... brain
1189 * damage alert! I don't think that we can execute any code in here in any
1190 * other mode than FIQ... Ok you can switch to another mode, but you can't
1191 * get out of that mode without clobbering one register.
1197 /*=============================================================================
1198 * Address exception handler
1199 *-----------------------------------------------------------------------------
1200 * These aren't too critical.
1201 * (they're not supposed to happen, and won't happen in 32-bit data mode).
1208 * We group all the following data together to optimise
1209 * for CPUs with separate I & D caches.
1219 .equ stubs_offset, __vectors_start + 0x200 - __stubs_start
1221 .globl __vectors_start
1223 ARM( swi SYS_ERROR0 )
1226 W(b) vector_und + stubs_offset
1227 W(ldr) pc, .LCvswi + stubs_offset
1228 W(b) vector_pabt + stubs_offset
1229 W(b) vector_dabt + stubs_offset
1230 W(b) vector_addrexcptn + stubs_offset
1231 W(b) vector_irq + stubs_offset
1232 W(b) vector_fiq + stubs_offset
1234 .globl __vectors_end
1240 .globl cr_no_alignment