release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/include/asm/hardware/pl080.h

   1 /* arch/arm/include/asm/hardware/pl080.h
   2  *
   3  * Copyright 2008 Openmoko, Inc.
   4  * Copyright 2008 Simtec Electronics
   5  *      http://armlinux.simtec.co.uk/
   6  *      Ben Dooks <ben@simtec.co.uk>
   7  *
   8  * ARM PrimeCell PL080 DMA controller
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13 */
  14
  15 /* Note, there are some Samsung updates to this controller block which
  16  * make it not entierly compatible with the PL080 specification from
  17  * ARM. When in doubt, check the Samsung documentation first.
  18  *
  19  * The Samsung defines are PL080S, and add an extra controll register,
  20  * the ability to move more than 2^11 counts of data and some extra
  21  * OneNAND features.
  22 */
  23
  24 #define PL080_INT_STATUS                        (0x00)
  25 #define PL080_TC_STATUS                         (0x04)
  26 #define PL080_TC_CLEAR                          (0x08)
  27 #define PL080_ERR_STATUS                        (0x0C)
  28 #define PL080_ERR_CLEAR                         (0x10)
  29 #define PL080_RAW_TC_STATUS                     (0x14)
  30 #define PL080_RAW_ERR_STATUS                    (0x18)
  31 #define PL080_EN_CHAN                           (0x1c)
  32 #define PL080_SOFT_BREQ                         (0x20)
  33 #define PL080_SOFT_SREQ                         (0x24)
  34 #define PL080_SOFT_LBREQ                        (0x28)
  35 #define PL080_SOFT_LSREQ                        (0x2C)
  36
  37 #define PL080_CONFIG                            (0x30)
  38 #define PL080_CONFIG_M2_BE                      (1 << 2)
  39 #define PL080_CONFIG_M1_BE                      (1 << 1)
  40 #define PL080_CONFIG_ENABLE                     (1 << 0)
  41
  42 #define PL080_SYNC                              (0x34)
  43
  44 /* Per channel configuration registers */
  45
  46 #define PL080_Cx_STRIDE                         (0x20)
  47 #define PL080_Cx_BASE(x)                        ((0x100 + (x * 0x20)))
  48 #define PL080_Cx_SRC_ADDR(x)                    ((0x100 + (x * 0x20)))
  49 #define PL080_Cx_DST_ADDR(x)                    ((0x104 + (x * 0x20)))
  50 #define PL080_Cx_LLI(x)                         ((0x108 + (x * 0x20)))
  51 #define PL080_Cx_CONTROL(x)                     ((0x10C + (x * 0x20)))
  52 #define PL080_Cx_CONFIG(x)                      ((0x110 + (x * 0x20)))
  53 #define PL080S_Cx_CONTROL2(x)                   ((0x110 + (x * 0x20)))
  54 #define PL080S_Cx_CONFIG(x)                     ((0x114 + (x * 0x20)))
  55
  56 #define PL080_CH_SRC_ADDR                       (0x00)
  57 #define PL080_CH_DST_ADDR                       (0x04)
  58 #define PL080_CH_LLI                            (0x08)
  59 #define PL080_CH_CONTROL                        (0x0C)
  60 #define PL080_CH_CONFIG                         (0x10)
  61 #define PL080S_CH_CONTROL2                      (0x10)
  62 #define PL080S_CH_CONFIG                        (0x14)
  63
  64 #define PL080_LLI_ADDR_MASK                     (0x3fffffff << 2)
  65 #define PL080_LLI_ADDR_SHIFT                    (2)
  66 #define PL080_LLI_LM_AHB2                       (1 << 0)
  67
  68 #define PL080_CONTROL_TC_IRQ_EN                 (1 << 31)
  69 #define PL080_CONTROL_PROT_MASK                 (0x7 << 28)
  70 #define PL080_CONTROL_PROT_SHIFT                (28)
  71 #define PL080_CONTROL_PROT_CACHE                (1 << 30)
  72 #define PL080_CONTROL_PROT_BUFF                 (1 << 29)
  73 #define PL080_CONTROL_PROT_SYS                  (1 << 28)
  74 #define PL080_CONTROL_DST_INCR                  (1 << 27)
  75 #define PL080_CONTROL_SRC_INCR                  (1 << 26)
  76 #define PL080_CONTROL_DST_AHB2                  (1 << 25)
  77 #define PL080_CONTROL_SRC_AHB2                  (1 << 24)
  78 #define PL080_CONTROL_DWIDTH_MASK               (0x7 << 21)
  79 #define PL080_CONTROL_DWIDTH_SHIFT              (21)
  80 #define PL080_CONTROL_SWIDTH_MASK               (0x7 << 18)
  81 #define PL080_CONTROL_SWIDTH_SHIFT              (18)
  82 #define PL080_CONTROL_DB_SIZE_MASK              (0x7 << 15)
  83 #define PL080_CONTROL_DB_SIZE_SHIFT             (15)
  84 #define PL080_CONTROL_SB_SIZE_MASK              (0x7 << 12)
  85 #define PL080_CONTROL_SB_SIZE_SHIFT             (12)
  86 #define PL080_CONTROL_TRANSFER_SIZE_MASK        (0xfff << 0)
  87 #define PL080_CONTROL_TRANSFER_SIZE_SHIFT       (0)
  88
  89 #define PL080_BSIZE_1                           (0x0)
  90 #define PL080_BSIZE_4                           (0x1)
  91 #define PL080_BSIZE_8                           (0x2)
  92 #define PL080_BSIZE_16                          (0x3)
  93 #define PL080_BSIZE_32                          (0x4)
  94 #define PL080_BSIZE_64                          (0x5)
  95 #define PL080_BSIZE_128                         (0x6)
  96 #define PL080_BSIZE_256                         (0x7)
  97
  98 #define PL080_WIDTH_8BIT                        (0x0)
  99 #define PL080_WIDTH_16BIT                       (0x1)
 100 #define PL080_WIDTH_32BIT                       (0x2)
 101
 102 #define PL080_CONFIG_HALT                       (1 << 18)
 103 #define PL080_CONFIG_ACTIVE                     (1 << 17)  /* RO */
 104 #define PL080_CONFIG_LOCK                       (1 << 16)
 105 #define PL080_CONFIG_TC_IRQ_MASK                (1 << 15)
 106 #define PL080_CONFIG_ERR_IRQ_MASK               (1 << 14)
 107 #define PL080_CONFIG_FLOW_CONTROL_MASK          (0x7 << 11)
 108 #define PL080_CONFIG_FLOW_CONTROL_SHIFT         (11)
 109 #define PL080_CONFIG_DST_SEL_MASK               (0xf << 6)
 110 #define PL080_CONFIG_DST_SEL_SHIFT              (6)
 111 #define PL080_CONFIG_SRC_SEL_MASK               (0xf << 1)
 112 #define PL080_CONFIG_SRC_SEL_SHIFT              (1)
 113 #define PL080_CONFIG_ENABLE                     (1 << 0)
 114
 115 #define PL080_FLOW_MEM2MEM                      (0x0)
 116 #define PL080_FLOW_MEM2PER                      (0x1)
 117 #define PL080_FLOW_PER2MEM                      (0x2)
 118 #define PL080_FLOW_SRC2DST                      (0x3)
 119 #define PL080_FLOW_SRC2DST_DST                  (0x4)
 120 #define PL080_FLOW_MEM2PER_PER                  (0x5)
 121 #define PL080_FLOW_PER2MEM_PER                  (0x6)
 122 #define PL080_FLOW_SRC2DST_SRC                  (0x7)
 123
 124 /* DMA linked list chain structure */
 125
 126 struct pl080_lli {
 127         u32     src_addr;
 128         u32     dst_addr;
 129         u32     next_lli;
 130         u32     control0;
 131 };
 132
 133 struct pl080s_lli {
 134         u32     src_addr;
 135         u32     dst_addr;
 136         u32     next_lli;
 137         u32     control0;
 138         u32     control1;
 139 };