release/src-rt-6.x.4708/linux/linux-2.6.36/arch/arm/common/gic.c

   1 /*
   2  *  linux/arch/arm/common/gic.c
   3  *
   4  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Interrupt architecture for the GIC:
  11  *
  12  * o There is one Interrupt Distributor, which receives interrupts
  13  *   from system devices and sends them to the Interrupt Controllers.
  14  *
  15  * o There is one CPU Interface per CPU, which sends interrupts sent
  16  *   by the Distributor, and interrupts generated locally, to the
  17  *   associated CPU. The base address of the CPU interface is usually
  18  *   aliased so that the same address points to different chips depending
  19  *   on the CPU it is accessed from.
  20  *
  21  * Note that IRQs 0-31 are special - they are local to each CPU.
  22  * As such, the enable set/clear, pending set/clear and active bit
  23  * registers are banked per-cpu for these sources.
  24  */
  25 #include <linux/init.h>
  26 #include <linux/kernel.h>
  27 #include <linux/list.h>
  28 #include <linux/smp.h>
  29 #include <linux/cpumask.h>
  30 #include <linux/io.h>
  31
  32 #include <asm/irq.h>
  33 #include <asm/mach/irq.h>
  34 #include <asm/hardware/gic.h>
  35
  36 static DEFINE_SPINLOCK(irq_controller_lock);
  37
  38 struct gic_chip_data {
  39         unsigned int irq_offset;
  40         void __iomem *dist_base;
  41         void __iomem *cpu_base;
  42 };
  43
  44 #ifndef MAX_GIC_NR
  45 #define MAX_GIC_NR      1
  46 #endif
  47
  48 static struct gic_chip_data gic_data[MAX_GIC_NR];
  49
  50 static inline void __iomem *gic_dist_base(unsigned int irq)
  51 {
  52         struct gic_chip_data *gic_data = get_irq_chip_data(irq);
  53         return gic_data->dist_base;
  54 }
  55
  56 static inline void __iomem *gic_cpu_base(unsigned int irq)
  57 {
  58         struct gic_chip_data *gic_data = get_irq_chip_data(irq);
  59         return gic_data->cpu_base;
  60 }
  61
  62 static inline unsigned int gic_irq(unsigned int irq)
  63 {
  64         struct gic_chip_data *gic_data = get_irq_chip_data(irq);
  65         return irq - gic_data->irq_offset;
  66 }
  67
  68 /*
  69  * Routines to acknowledge, disable and enable interrupts
  70  *
  71  * Linux assumes that when we're done with an interrupt we need to
  72  * unmask it, in the same way we need to unmask an interrupt when
  73  * we first enable it.
  74  *
  75  * The GIC has a separate notion of "end of interrupt" to re-enable
  76  * an interrupt after handling, in order to support hardware
  77  * prioritisation.
  78  *
  79  * We can make the GIC behave in the way that Linux expects by making
  80  * our "acknowledge" routine disable the interrupt, then mark it as
  81  * complete.
  82  */
  83 static void gic_ack_irq(unsigned int irq)
  84 {
  85         u32 mask = 1 << (irq % 32);
  86
  87         spin_lock(&irq_controller_lock);
  88         writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
  89         writel(gic_irq(irq), gic_cpu_base(irq) + GIC_CPU_EOI);
  90         spin_unlock(&irq_controller_lock);
  91 }
  92
  93 static void gic_mask_irq(unsigned int irq)
  94 {
  95         u32 mask = 1 << (irq % 32);
  96
  97         spin_lock(&irq_controller_lock);
  98         writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_CLEAR + (gic_irq(irq) / 32) * 4);
  99         spin_unlock(&irq_controller_lock);
 100 }
 101
 102 static void gic_unmask_irq(unsigned int irq)
 103 {
 104         u32 mask = 1 << (irq % 32);
 105
 106         spin_lock(&irq_controller_lock);
 107         writel(mask, gic_dist_base(irq) + GIC_DIST_ENABLE_SET + (gic_irq(irq) / 32) * 4);
 108         spin_unlock(&irq_controller_lock);
 109 }
 110
 111 static int gic_set_type(unsigned int irq, unsigned int type)
 112 {
 113         void __iomem *base = gic_dist_base(irq);
 114         unsigned int gicirq = gic_irq(irq);
 115         u32 enablemask = 1 << (gicirq % 32);
 116         u32 enableoff = (gicirq / 32) * 4;
 117         u32 confmask = 0x2 << ((gicirq % 16) * 2);
 118         u32 confoff = (gicirq / 16) * 4;
 119         bool enabled = false;
 120         u32 val;
 121
 122         /* Interrupt configuration for SGIs can't be changed */
 123         if (gicirq < 16)
 124                 return -EINVAL;
 125
 126         if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
 127                 return -EINVAL;
 128
 129         spin_lock(&irq_controller_lock);
 130
 131         val = readl(base + GIC_DIST_CONFIG + confoff);
 132         if (type == IRQ_TYPE_LEVEL_HIGH)
 133                 val &= ~confmask;
 134         else if (type == IRQ_TYPE_EDGE_RISING)
 135                 val |= confmask;
 136
 137         /*
 138          * As recommended by the spec, disable the interrupt before changing
 139          * the configuration
 140          */
 141         if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
 142                 writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
 143                 enabled = true;
 144         }
 145
 146         writel(val, base + GIC_DIST_CONFIG + confoff);
 147
 148         if (enabled)
 149                 writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
 150
 151         spin_unlock(&irq_controller_lock);
 152
 153         return 0;
 154 }
 155
 156 #ifdef CONFIG_SMP
 157 static int gic_set_cpu(unsigned int irq, const struct cpumask *mask_val)
 158 {
 159         void __iomem *reg = gic_dist_base(irq) + GIC_DIST_TARGET + (gic_irq(irq) & ~3);
 160         unsigned int shift = (irq % 4) * 8;
 161         unsigned int cpu = cpumask_first(mask_val);
 162         u32 val;
 163
 164         spin_lock(&irq_controller_lock);
 165         irq_desc[irq].node = cpu;
 166         val = readl(reg) & ~(0xff << shift);
 167         val |= 1 << (cpu + shift);
 168         writel(val, reg);
 169         spin_unlock(&irq_controller_lock);
 170
 171         return 0;
 172 }
 173 #endif
 174
 175 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 176 {
 177         struct gic_chip_data *chip_data = get_irq_data(irq);
 178         struct irq_chip *chip = get_irq_chip(irq);
 179         unsigned int cascade_irq, gic_irq;
 180         unsigned long status;
 181
 182         /* primary controller ack'ing */
 183         chip->ack(irq);
 184
 185         spin_lock(&irq_controller_lock);
 186         status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
 187         spin_unlock(&irq_controller_lock);
 188
 189         gic_irq = (status & 0x3ff);
 190         if (gic_irq == 1023)
 191                 goto out;
 192
 193         cascade_irq = gic_irq + chip_data->irq_offset;
 194         if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS))
 195                 do_bad_IRQ(cascade_irq, desc);
 196         else
 197                 generic_handle_irq(cascade_irq);
 198
 199  out:
 200         /* primary controller unmasking */
 201         chip->unmask(irq);
 202 }
 203
 204 static struct irq_chip gic_chip = {
 205         .name           = "GIC",
 206         .ack            = gic_ack_irq,
 207         .mask           = gic_mask_irq,
 208         .unmask         = gic_unmask_irq,
 209         .set_type       = gic_set_type,
 210 #ifdef CONFIG_SMP
 211         .set_affinity   = gic_set_cpu,
 212 #endif
 213 };
 214
 215 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
 216 {
 217         if (gic_nr >= MAX_GIC_NR)
 218                 BUG();
 219         if (set_irq_data(irq, &gic_data[gic_nr]) != 0)
 220                 BUG();
 221         set_irq_chained_handler(irq, gic_handle_cascade_irq);
 222 }
 223
 224 void __init gic_dist_init(unsigned int gic_nr, void __iomem *base,
 225                           unsigned int irq_start)
 226 {
 227         unsigned int max_irq, i;
 228         u32 cpumask = 1 << smp_processor_id();
 229
 230         if (gic_nr >= MAX_GIC_NR)
 231                 BUG();
 232
 233         cpumask |= cpumask << 8;
 234         cpumask |= cpumask << 16;
 235
 236         gic_data[gic_nr].dist_base = base;
 237         gic_data[gic_nr].irq_offset = (irq_start - 1) & ~31;
 238
 239         writel(0, base + GIC_DIST_CTRL);
 240
 241         /*
 242          * Find out how many interrupts are supported.
 243          */
 244         max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
 245         max_irq = (max_irq + 1) * 32;
 246
 247         /*
 248          * The GIC only supports up to 1020 interrupt sources.
 249          * Limit this to either the architected maximum, or the
 250          * platform maximum.
 251          */
 252         if (max_irq > max(1020, NR_IRQS))
 253                 max_irq = max(1020, NR_IRQS);
 254
 255         /*
 256          * Set all global interrupts to be level triggered, active low.
 257          */
 258         for (i = 32; i < max_irq; i += 16)
 259                 writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
 260
 261         /*
 262          * Set all global interrupts to this CPU only.
 263          */
 264         for (i = 32; i < max_irq; i += 4)
 265                 writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 266
 267         /*
 268          * Set priority on all interrupts.
 269          */
 270         for (i = 0; i < max_irq; i += 4)
 271                 writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
 272
 273         /*
 274          * Disable all interrupts.
 275          */
 276         for (i = 0; i < max_irq; i += 32)
 277                 writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
 278
 279         /*
 280          * Setup the Linux IRQ subsystem.
 281          */
 282         for (i = irq_start; i < gic_data[gic_nr].irq_offset + max_irq; i++) {
 283                 set_irq_chip(i, &gic_chip);
 284                 set_irq_chip_data(i, &gic_data[gic_nr]);
 285                 set_irq_handler(i, handle_level_irq);
 286                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 287         }
 288
 289         writel(1, base + GIC_DIST_CTRL);
 290 }
 291
 292 void __cpuinit gic_cpu_init(unsigned int gic_nr, void __iomem *base)
 293 {
 294         if (gic_nr >= MAX_GIC_NR)
 295                 BUG();
 296
 297         gic_data[gic_nr].cpu_base = base;
 298
 299         writel(0xf0, base + GIC_CPU_PRIMASK);
 300         writel(1, base + GIC_CPU_CTRL);
 301 }
 302
 303 #ifdef CONFIG_SMP
 304 void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
 305 {
 306         unsigned long map = *cpus_addr(*mask);
 307
 308         /* this always happens on GIC0 */
 309         writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
 310 }
 311 #endif