2 * linux/arch/alpha/kernel/core_marvel.c
4 * Code common to all Marvel based systems.
7 #define __EXTERN_INLINE inline
9 #include <asm/core_marvel.h>
10 #undef __EXTERN_INLINE
12 #include <linux/types.h>
13 #include <linux/pci.h>
14 #include <linux/sched.h>
15 #include <linux/init.h>
16 #include <linux/vmalloc.h>
17 #include <linux/mc146818rtc.h>
18 #include <linux/rtc.h>
19 #include <linux/module.h>
20 #include <linux/bootmem.h>
22 #include <asm/ptrace.h>
25 #include <asm/pgalloc.h>
26 #include <asm/tlbflush.h>
37 #define DEBUG_CONFIG 0
40 # define DBG_CFG(args) printk args
42 # define DBG_CFG(args)
49 static struct io7
*io7_head
= NULL
;
55 static unsigned long __attribute__ ((unused
))
56 read_ev7_csr(int pe
, unsigned long offset
)
58 ev7_csr
*ev7csr
= EV7_CSR_KERN(pe
, offset
);
68 static void __attribute__ ((unused
))
69 write_ev7_csr(int pe
, unsigned long offset
, unsigned long q
)
71 ev7_csr
*ev7csr
= EV7_CSR_KERN(pe
, offset
);
79 mk_resource_name(int pe
, int port
, char *str
)
84 sprintf(tmp
, "PCI %s PE %d PORT %d", str
, pe
, port
);
85 name
= alloc_bootmem(strlen(tmp
) + 1);
92 marvel_next_io7(struct io7
*prev
)
94 return (prev
? prev
->next
: io7_head
);
98 marvel_find_io7(int pe
)
102 for (io7
= io7_head
; io7
&& io7
->pe
!= pe
; io7
= io7
->next
)
108 static struct io7
* __init
109 alloc_io7(unsigned int pe
)
115 if (marvel_find_io7(pe
)) {
116 printk(KERN_WARNING
"IO7 at PE %d already allocated!\n", pe
);
120 io7
= alloc_bootmem(sizeof(*io7
));
122 spin_lock_init(&io7
->irq_lock
);
124 for (h
= 0; h
< 4; h
++) {
125 io7
->ports
[h
].io7
= io7
;
126 io7
->ports
[h
].port
= h
;
127 io7
->ports
[h
].enabled
= 0; /* default to disabled */
131 * Insert in pe sorted order.
133 if (NULL
== io7_head
) /* empty list */
135 else if (io7_head
->pe
> io7
->pe
) { /* insert at head */
136 io7
->next
= io7_head
;
138 } else { /* insert at position */
139 for (insp
= io7_head
; insp
; insp
= insp
->next
) {
140 if (insp
->pe
== io7
->pe
) {
141 printk(KERN_ERR
"Too many IO7s at PE %d\n",
146 if (NULL
== insp
->next
||
147 insp
->next
->pe
> io7
->pe
) { /* insert here */
148 io7
->next
= insp
->next
;
154 if (NULL
== insp
) { /* couldn't insert ?!? */
155 printk(KERN_WARNING
"Failed to insert IO7 at PE %d "
156 " - adding at head of list\n", io7
->pe
);
157 io7
->next
= io7_head
;
166 io7_clear_errors(struct io7
*io7
)
168 io7_port7_csrs
*p7csrs
;
169 io7_ioport_csrs
*csrs
;
174 * First the IO ports.
176 for (port
= 0; port
< 4; port
++) {
177 csrs
= IO7_CSRS_KERN(io7
->pe
, port
);
179 csrs
->POx_ERR_SUM
.csr
= -1UL;
180 csrs
->POx_TLB_ERR
.csr
= -1UL;
181 csrs
->POx_SPL_COMPLT
.csr
= -1UL;
182 csrs
->POx_TRANS_SUM
.csr
= -1UL;
186 * Then the common ones.
188 p7csrs
= IO7_PORT7_CSRS_KERN(io7
->pe
);
190 p7csrs
->PO7_ERROR_SUM
.csr
= -1UL;
191 p7csrs
->PO7_UNCRR_SYM
.csr
= -1UL;
192 p7csrs
->PO7_CRRCT_SYM
.csr
= -1UL;
197 * IO7 PCI, PCI/X, AGP configuration.
200 io7_init_hose(struct io7
*io7
, int port
)
202 static int hose_index
= 0;
204 struct pci_controller
*hose
= alloc_pci_controller();
205 struct io7_port
*io7_port
= &io7
->ports
[port
];
206 io7_ioport_csrs
*csrs
= IO7_CSRS_KERN(io7
->pe
, port
);
209 hose
->index
= hose_index
++; /* arbitrary */
212 * We don't have an isa or legacy hose, but glibc expects to be
213 * able to use the bus == 0 / dev == 0 form of the iobase syscall
214 * to determine information about the i/o system. Since XFree86
215 * relies on glibc's determination to tell whether or not to use
216 * sparse access, we need to point the pci_isa_hose at a real hose
217 * so at least that determination is correct.
219 if (hose
->index
== 0)
222 io7_port
->csrs
= csrs
;
223 io7_port
->hose
= hose
;
224 hose
->sysdata
= io7_port
;
226 hose
->io_space
= alloc_resource();
227 hose
->mem_space
= alloc_resource();
230 * Base addresses for userland consumption. Since these are going
231 * to be mapped, they are pure physical addresses.
233 hose
->sparse_mem_base
= hose
->sparse_io_base
= 0;
234 hose
->dense_mem_base
= IO7_MEM_PHYS(io7
->pe
, port
);
235 hose
->dense_io_base
= IO7_IO_PHYS(io7
->pe
, port
);
238 * Base addresses and resource ranges for kernel consumption.
240 hose
->config_space_base
= (unsigned long)IO7_CONF_KERN(io7
->pe
, port
);
242 hose
->io_space
->start
= (unsigned long)IO7_IO_KERN(io7
->pe
, port
);
243 hose
->io_space
->end
= hose
->io_space
->start
+ IO7_IO_SPACE
- 1;
244 hose
->io_space
->name
= mk_resource_name(io7
->pe
, port
, "IO");
245 hose
->io_space
->flags
= IORESOURCE_IO
;
247 hose
->mem_space
->start
= (unsigned long)IO7_MEM_KERN(io7
->pe
, port
);
248 hose
->mem_space
->end
= hose
->mem_space
->start
+ IO7_MEM_SPACE
- 1;
249 hose
->mem_space
->name
= mk_resource_name(io7
->pe
, port
, "MEM");
250 hose
->mem_space
->flags
= IORESOURCE_MEM
;
252 if (request_resource(&ioport_resource
, hose
->io_space
) < 0)
253 printk(KERN_ERR
"Failed to request IO on hose %d\n",
255 if (request_resource(&iomem_resource
, hose
->mem_space
) < 0)
256 printk(KERN_ERR
"Failed to request MEM on hose %d\n",
260 * Save the existing DMA window settings for later restoration.
262 for (i
= 0; i
< 4; i
++) {
263 io7_port
->saved_wbase
[i
] = csrs
->POx_WBASE
[i
].csr
;
264 io7_port
->saved_wmask
[i
] = csrs
->POx_WMASK
[i
].csr
;
265 io7_port
->saved_tbase
[i
] = csrs
->POx_TBASE
[i
].csr
;
269 * Set up the PCI to main memory translation windows.
271 * Window 0 is scatter-gather 8MB at 8MB
272 * Window 1 is direct access 1GB at 2GB
273 * Window 2 is scatter-gather (up-to) 1GB at 3GB
274 * Window 3 is disabled
278 * TBIA before modifying windows.
280 marvel_pci_tbi(hose
, 0, -1);
283 * Set up window 0 for scatter-gather 8MB at 8MB.
285 hose
->sg_isa
= iommu_arena_new_node(marvel_cpuid_to_nid(io7
->pe
),
286 hose
, 0x00800000, 0x00800000, 0);
287 hose
->sg_isa
->align_entry
= 8; /* cache line boundary */
288 csrs
->POx_WBASE
[0].csr
=
289 hose
->sg_isa
->dma_base
| wbase_m_ena
| wbase_m_sg
;
290 csrs
->POx_WMASK
[0].csr
= (hose
->sg_isa
->size
- 1) & wbase_m_addr
;
291 csrs
->POx_TBASE
[0].csr
= virt_to_phys(hose
->sg_isa
->ptes
);
294 * Set up window 1 for direct-mapped 1GB at 2GB.
296 csrs
->POx_WBASE
[1].csr
= __direct_map_base
| wbase_m_ena
;
297 csrs
->POx_WMASK
[1].csr
= (__direct_map_size
- 1) & wbase_m_addr
;
298 csrs
->POx_TBASE
[1].csr
= 0;
301 * Set up window 2 for scatter-gather (up-to) 1GB at 3GB.
303 hose
->sg_pci
= iommu_arena_new_node(marvel_cpuid_to_nid(io7
->pe
),
304 hose
, 0xc0000000, 0x40000000, 0);
305 hose
->sg_pci
->align_entry
= 8; /* cache line boundary */
306 csrs
->POx_WBASE
[2].csr
=
307 hose
->sg_pci
->dma_base
| wbase_m_ena
| wbase_m_sg
;
308 csrs
->POx_WMASK
[2].csr
= (hose
->sg_pci
->size
- 1) & wbase_m_addr
;
309 csrs
->POx_TBASE
[2].csr
= virt_to_phys(hose
->sg_pci
->ptes
);
314 csrs
->POx_WBASE
[3].csr
= 0;
317 * Make sure that the AGP Monster Window is disabled.
319 csrs
->POx_CTRL
.csr
&= ~(1UL << 61);
321 printk("FIXME: disabling master aborts\n");
322 csrs
->POx_MSK_HEI
.csr
&= ~(3UL << 14);
324 * TBIA after modifying windows.
326 marvel_pci_tbi(hose
, 0, -1);
330 marvel_init_io7(struct io7
*io7
)
334 printk("Initializing IO7 at PID %d\n", io7
->pe
);
337 * Get the Port 7 CSR pointer.
339 io7
->csrs
= IO7_PORT7_CSRS_KERN(io7
->pe
);
342 * Init this IO7's hoses.
344 for (i
= 0; i
< IO7_NUM_PORTS
; i
++) {
345 io7_ioport_csrs
*csrs
= IO7_CSRS_KERN(io7
->pe
, i
);
346 if (csrs
->POx_CACHE_CTL
.csr
== 8) {
347 io7
->ports
[i
].enabled
= 1;
348 io7_init_hose(io7
, i
);
354 marvel_io7_present(gct6_node
*node
)
358 if (node
->type
!= GCT_TYPE_HOSE
||
359 node
->subtype
!= GCT_SUBTYPE_IO_PORT_MODULE
)
362 pe
= (node
->id
>> 8) & 0xff;
363 printk("Found an IO7 at PID %d\n", pe
);
369 marvel_find_console_vga_hose(void)
371 u64
*pu64
= (u64
*)((u64
)hwrpb
+ hwrpb
->ctbt_offset
);
373 if (pu64
[7] == 3) { /* TERM_TYPE == graphics */
374 struct pci_controller
*hose
= NULL
;
375 int h
= (pu64
[30] >> 24) & 0xff; /* TERM_OUT_LOC, hose # */
379 printk("console graphics is on hose %d (console)\n", h
);
382 * The console's hose numbering is:
387 * We need to find the hose at that pid and port
391 if ((io7
= marvel_find_io7(pid
)))
392 hose
= io7
->ports
[port
].hose
;
395 printk("Console graphics on hose %d\n", hose
->index
);
401 gct6_search_struct gct_wanted_node_list
[] = {
402 { GCT_TYPE_HOSE
, GCT_SUBTYPE_IO_PORT_MODULE
, marvel_io7_present
},
407 * In case the GCT is not complete, let the user specify PIDs with IO7s
408 * at boot time. Syntax is 'io7=a,b,c,...,n' where a-n are the PIDs (decimal)
409 * where IO7s are connected
412 marvel_specify_io7(char *str
)
419 pid
= simple_strtoul(str
, &pchar
, 0);
421 printk("User-specified IO7 at PID %lu\n", pid
);
422 io7
= alloc_io7(pid
);
423 if (io7
) marvel_init_io7(io7
);
426 if (pchar
== str
) pchar
++;
432 __setup("io7=", marvel_specify_io7
);
435 marvel_init_arch(void)
439 /* With multiple PCI busses, we play with I/O as physical addrs. */
440 ioport_resource
.end
= ~0UL;
442 /* PCI DMA Direct Mapping is 1GB at 2GB. */
443 __direct_map_base
= 0x80000000;
444 __direct_map_size
= 0x40000000;
446 /* Parse the config tree. */
447 gct6_find_nodes(GCT_NODE_PTR(0), gct_wanted_node_list
);
450 for (io7
= NULL
; NULL
!= (io7
= marvel_next_io7(io7
)); )
451 marvel_init_io7(io7
);
453 /* Check for graphic console location (if any). */
454 marvel_find_console_vga_hose();
458 marvel_kill_arch(int mode
)
464 * PCI Configuration Space access functions
466 * Configuration space addresses have the following format:
468 * |2 2 2 2|1 1 1 1|1 1 1 1|1 1
469 * |3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
470 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
471 * |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|R|R|
472 * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
474 * n:24 reserved for hose base
475 * 23:16 bus number (8 bits = 128 possible buses)
476 * 15:11 Device number (5 bits)
477 * 10:8 function number
478 * 7:2 register number
481 * IO7 determines whether to use a type 0 or type 1 config cycle
482 * based on the bus number. Therefore the bus number must be set
483 * to 0 for the root bus on any hose.
485 * The function number selects which function of a multi-function device
486 * (e.g., SCSI and Ethernet).
490 static inline unsigned long
491 build_conf_addr(struct pci_controller
*hose
, u8 bus
,
492 unsigned int devfn
, int where
)
494 return (hose
->config_space_base
| (bus
<< 16) | (devfn
<< 8) | where
);
498 mk_conf_addr(struct pci_bus
*pbus
, unsigned int devfn
, int where
)
500 struct pci_controller
*hose
= pbus
->sysdata
;
501 struct io7_port
*io7_port
;
502 unsigned long addr
= 0;
503 u8 bus
= pbus
->number
;
508 /* Check for enabled. */
509 io7_port
= hose
->sysdata
;
510 if (!io7_port
->enabled
)
513 if (!pbus
->parent
) { /* No parent means peer PCI bus. */
514 /* Don't support idsel > 20 on primary bus. */
515 if (devfn
>= PCI_DEVFN(21, 0))
520 addr
= build_conf_addr(hose
, bus
, devfn
, where
);
522 DBG_CFG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr
));
527 marvel_read_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
528 int size
, u32
*value
)
532 if (0 == (addr
= mk_conf_addr(bus
, devfn
, where
)))
533 return PCIBIOS_DEVICE_NOT_FOUND
;
537 *value
= __kernel_ldbu(*(vucp
)addr
);
540 *value
= __kernel_ldwu(*(vusp
)addr
);
543 *value
= *(vuip
)addr
;
546 return PCIBIOS_FUNC_NOT_SUPPORTED
;
549 return PCIBIOS_SUCCESSFUL
;
553 marvel_write_config(struct pci_bus
*bus
, unsigned int devfn
, int where
,
558 if (0 == (addr
= mk_conf_addr(bus
, devfn
, where
)))
559 return PCIBIOS_DEVICE_NOT_FOUND
;
563 __kernel_stb(value
, *(vucp
)addr
);
565 __kernel_ldbu(*(vucp
)addr
);
568 __kernel_stw(value
, *(vusp
)addr
);
570 __kernel_ldwu(*(vusp
)addr
);
578 return PCIBIOS_FUNC_NOT_SUPPORTED
;
581 return PCIBIOS_SUCCESSFUL
;
584 struct pci_ops marvel_pci_ops
=
586 .read
= marvel_read_config
,
587 .write
= marvel_write_config
,
592 * Other PCI helper functions.
595 marvel_pci_tbi(struct pci_controller
*hose
, dma_addr_t start
, dma_addr_t end
)
597 io7_ioport_csrs
*csrs
= ((struct io7_port
*)hose
->sysdata
)->csrs
;
600 csrs
->POx_SG_TBIA
.csr
= 0;
602 csrs
->POx_SG_TBIA
.csr
;
610 struct marvel_rtc_access_info
{
611 unsigned long function
;
617 __marvel_access_rtc(void *info
)
619 struct marvel_rtc_access_info
*rtc_access
= info
;
621 register unsigned long __r0
__asm__("$0");
622 register unsigned long __r16
__asm__("$16") = rtc_access
->function
;
623 register unsigned long __r17
__asm__("$17") = rtc_access
->index
;
624 register unsigned long __r18
__asm__("$18") = rtc_access
->data
;
626 __asm__
__volatile__(
627 "call_pal %4 # cserve rtc"
628 : "=r"(__r16
), "=r"(__r17
), "=r"(__r18
), "=r"(__r0
)
629 : "i"(PAL_cserve
), "0"(__r16
), "1"(__r17
), "2"(__r18
)
630 : "$1", "$22", "$23", "$24", "$25");
632 rtc_access
->data
= __r0
;
636 __marvel_rtc_io(u8 b
, unsigned long addr
, int write
)
640 struct marvel_rtc_access_info rtc_access
;
644 case 0x70: /* RTC_PORT(0) */
645 if (write
) index
= b
;
649 case 0x71: /* RTC_PORT(1) */
650 rtc_access
.index
= index
;
651 rtc_access
.data
= bcd2bin(b
);
652 rtc_access
.function
= 0x48 + !write
; /* GET/PUT_TOY */
654 __marvel_access_rtc(&rtc_access
);
656 ret
= bin2bcd(rtc_access
.data
);
660 printk(KERN_WARNING
"Illegal RTC port %lx\n", addr
);
672 marvel_ioremap(unsigned long addr
, unsigned long size
)
674 struct pci_controller
*hose
;
675 unsigned long baddr
, last
;
676 struct vm_struct
*area
;
682 * Adjust the address.
684 FIXUP_MEMADDR_VGA(addr
);
689 for (hose
= hose_head
; hose
; hose
= hose
->next
) {
690 if ((addr
>> 32) == (hose
->mem_space
->start
>> 32))
697 * We have the hose - calculate the bus limits.
699 baddr
= addr
- hose
->mem_space
->start
;
700 last
= baddr
+ size
- 1;
703 * Is it direct-mapped?
705 if ((baddr
>= __direct_map_base
) &&
706 ((baddr
+ size
- 1) < __direct_map_base
+ __direct_map_size
)) {
707 addr
= IDENT_ADDR
| (baddr
- __direct_map_base
);
708 return (void __iomem
*) addr
;
712 * Check the scatter-gather arena.
715 baddr
>= (unsigned long)hose
->sg_pci
->dma_base
&&
716 last
< (unsigned long)hose
->sg_pci
->dma_base
+ hose
->sg_pci
->size
) {
719 * Adjust the limits (mappings must be page aligned)
721 baddr
-= hose
->sg_pci
->dma_base
;
722 last
-= hose
->sg_pci
->dma_base
;
724 size
= PAGE_ALIGN(last
) - baddr
;
729 area
= get_vm_area(size
, VM_IOREMAP
);
733 ptes
= hose
->sg_pci
->ptes
;
734 for (vaddr
= (unsigned long)area
->addr
;
736 baddr
+= PAGE_SIZE
, vaddr
+= PAGE_SIZE
) {
737 pfn
= ptes
[baddr
>> PAGE_SHIFT
];
739 printk("ioremap failed... pte not valid...\n");
743 pfn
>>= 1; /* make it a true pfn */
745 if (__alpha_remap_area_pages(vaddr
,
748 printk("FAILED to map...\n");
756 vaddr
= (unsigned long)area
->addr
+ (addr
& ~PAGE_MASK
);
758 return (void __iomem
*) vaddr
;
761 /* Assume it was already a reasonable address */
762 vaddr
= baddr
+ hose
->mem_space
->start
;
763 return (void __iomem
*) vaddr
;
767 marvel_iounmap(volatile void __iomem
*xaddr
)
769 unsigned long addr
= (unsigned long) xaddr
;
770 if (addr
>= VMALLOC_START
)
771 vfree((void *)(PAGE_MASK
& addr
));
775 marvel_is_mmio(const volatile void __iomem
*xaddr
)
777 unsigned long addr
= (unsigned long) xaddr
;
779 if (addr
>= VMALLOC_START
)
782 return (addr
& 0xFF000000UL
) == 0;
785 #define __marvel_is_port_kbd(a) (((a) == 0x60) || ((a) == 0x64))
786 #define __marvel_is_port_rtc(a) (((a) == 0x70) || ((a) == 0x71))
788 void __iomem
*marvel_ioportmap (unsigned long addr
)
790 FIXUP_IOADDR_VGA(addr
);
791 return (void __iomem
*)addr
;
795 marvel_ioread8(void __iomem
*xaddr
)
797 unsigned long addr
= (unsigned long) xaddr
;
798 if (__marvel_is_port_kbd(addr
))
800 else if (__marvel_is_port_rtc(addr
))
801 return __marvel_rtc_io(0, addr
, 0);
802 else if (marvel_is_ioaddr(addr
))
803 return __kernel_ldbu(*(vucp
)addr
);
805 /* this should catch other legacy addresses
806 that would normally fail on MARVEL,
807 because there really is nothing there...
813 marvel_iowrite8(u8 b
, void __iomem
*xaddr
)
815 unsigned long addr
= (unsigned long) xaddr
;
816 if (__marvel_is_port_kbd(addr
))
818 else if (__marvel_is_port_rtc(addr
))
819 __marvel_rtc_io(b
, addr
, 1);
820 else if (marvel_is_ioaddr(addr
))
821 __kernel_stb(b
, *(vucp
)addr
);
824 #ifndef CONFIG_ALPHA_GENERIC
825 EXPORT_SYMBOL(marvel_ioremap
);
826 EXPORT_SYMBOL(marvel_iounmap
);
827 EXPORT_SYMBOL(marvel_is_mmio
);
828 EXPORT_SYMBOL(marvel_ioportmap
);
829 EXPORT_SYMBOL(marvel_ioread8
);
830 EXPORT_SYMBOL(marvel_iowrite8
);
837 marvel_pa_to_nid(unsigned long pa
)
841 if ((pa
>> 43) & 1) /* I/O */
842 cpuid
= (~(pa
>> 35) & 0xff);
844 cpuid
= ((pa
>> 34) & 0x3) | ((pa
>> (37 - 2)) & (0x1f << 2));
846 return marvel_cpuid_to_nid(cpuid
);
850 marvel_cpuid_to_nid(int cpuid
)
856 marvel_node_mem_start(int nid
)
860 pa
= (nid
& 0x3) | ((nid
& (0x1f << 2)) << 1);
867 marvel_node_mem_size(int nid
)
869 return 16UL * 1024 * 1024 * 1024; /* 16GB */
876 #include <linux/agp_backend.h>
877 #include <asm/agp_backend.h>
878 #include <linux/slab.h>
879 #include <linux/delay.h>
881 struct marvel_agp_aperture
{
882 struct pci_iommu_arena
*arena
;
888 marvel_agp_setup(alpha_agp_info
*agp
)
890 struct marvel_agp_aperture
*aper
;
892 if (!alpha_agpgart_size
)
895 aper
= kmalloc(sizeof(*aper
), GFP_KERNEL
);
896 if (aper
== NULL
) return -ENOMEM
;
898 aper
->arena
= agp
->hose
->sg_pci
;
899 aper
->pg_count
= alpha_agpgart_size
/ PAGE_SIZE
;
900 aper
->pg_start
= iommu_reserve(aper
->arena
, aper
->pg_count
,
903 if (aper
->pg_start
< 0) {
904 printk(KERN_ERR
"Failed to reserve AGP memory\n");
909 agp
->aperture
.bus_base
=
910 aper
->arena
->dma_base
+ aper
->pg_start
* PAGE_SIZE
;
911 agp
->aperture
.size
= aper
->pg_count
* PAGE_SIZE
;
912 agp
->aperture
.sysdata
= aper
;
918 marvel_agp_cleanup(alpha_agp_info
*agp
)
920 struct marvel_agp_aperture
*aper
= agp
->aperture
.sysdata
;
923 status
= iommu_release(aper
->arena
, aper
->pg_start
, aper
->pg_count
);
924 if (status
== -EBUSY
) {
926 "Attempted to release bound AGP memory - unbinding\n");
927 iommu_unbind(aper
->arena
, aper
->pg_start
, aper
->pg_count
);
928 status
= iommu_release(aper
->arena
, aper
->pg_start
,
932 printk(KERN_ERR
"Failed to release AGP memory\n");
939 marvel_agp_configure(alpha_agp_info
*agp
)
941 io7_ioport_csrs
*csrs
= ((struct io7_port
*)agp
->hose
->sysdata
)->csrs
;
942 struct io7
*io7
= ((struct io7_port
*)agp
->hose
->sysdata
)->io7
;
943 unsigned int new_rate
= 0;
944 unsigned long agp_pll
;
947 * Check the requested mode against the PLL setting.
948 * The agpgart_be code has not programmed the card yet,
949 * so we can still tweak mode here.
951 agp_pll
= io7
->csrs
->POx_RST
[IO7_AGP_PORT
].csr
;
952 switch(IO7_PLL_RNGB(agp_pll
)) {
953 case 0x4: /* 2x only */
955 * The PLL is only programmed for 2x, so adjust the
956 * rate to 2x, if necessary.
958 if (agp
->mode
.bits
.rate
!= 2)
962 case 0x6: /* 1x / 4x */
964 * The PLL is programmed for 1x or 4x. Don't go faster
965 * than requested, so if the requested rate is 2x, use 1x.
967 if (agp
->mode
.bits
.rate
== 2)
971 default: /* ??????? */
973 * Don't know what this PLL setting is, take the requested
974 * rate, but warn the user.
976 printk("%s: unknown PLL setting RNGB=%lx (PLL6_CTL=%016lx)\n",
977 __func__
, IO7_PLL_RNGB(agp_pll
), agp_pll
);
982 * Set the new rate, if necessary.
985 printk("Requested AGP Rate %dX not compatible "
986 "with PLL setting - using %dX\n",
990 agp
->mode
.bits
.rate
= new_rate
;
993 printk("Enabling AGP on hose %d: %dX%s RQ %d\n",
994 agp
->hose
->index
, agp
->mode
.bits
.rate
,
995 agp
->mode
.bits
.sba
? " - SBA" : "", agp
->mode
.bits
.rq
);
997 csrs
->AGP_CMD
.csr
= agp
->mode
.lw
;
1003 marvel_agp_bind_memory(alpha_agp_info
*agp
, off_t pg_start
, struct agp_memory
*mem
)
1005 struct marvel_agp_aperture
*aper
= agp
->aperture
.sysdata
;
1006 return iommu_bind(aper
->arena
, aper
->pg_start
+ pg_start
,
1007 mem
->page_count
, mem
->pages
);
1011 marvel_agp_unbind_memory(alpha_agp_info
*agp
, off_t pg_start
, struct agp_memory
*mem
)
1013 struct marvel_agp_aperture
*aper
= agp
->aperture
.sysdata
;
1014 return iommu_unbind(aper
->arena
, aper
->pg_start
+ pg_start
,
1018 static unsigned long
1019 marvel_agp_translate(alpha_agp_info
*agp
, dma_addr_t addr
)
1021 struct marvel_agp_aperture
*aper
= agp
->aperture
.sysdata
;
1022 unsigned long baddr
= addr
- aper
->arena
->dma_base
;
1025 if (addr
< agp
->aperture
.bus_base
||
1026 addr
>= agp
->aperture
.bus_base
+ agp
->aperture
.size
) {
1027 printk("%s: addr out of range\n", __func__
);
1031 pte
= aper
->arena
->ptes
[baddr
>> PAGE_SHIFT
];
1033 printk("%s: pte not valid\n", __func__
);
1036 return (pte
>> 1) << PAGE_SHIFT
;
1039 struct alpha_agp_ops marvel_agp_ops
=
1041 .setup
= marvel_agp_setup
,
1042 .cleanup
= marvel_agp_cleanup
,
1043 .configure
= marvel_agp_configure
,
1044 .bind
= marvel_agp_bind_memory
,
1045 .unbind
= marvel_agp_unbind_memory
,
1046 .translate
= marvel_agp_translate
1050 marvel_agp_info(void)
1052 struct pci_controller
*hose
;
1053 io7_ioport_csrs
*csrs
;
1054 alpha_agp_info
*agp
;
1058 for (io7
= NULL
; (io7
= marvel_next_io7(io7
)) != NULL
; ) {
1059 struct pci_controller
*h
;
1062 if (!io7
->ports
[IO7_AGP_PORT
].enabled
)
1065 h
= io7
->ports
[IO7_AGP_PORT
].hose
;
1066 addr
= (vuip
)build_conf_addr(h
, 0, PCI_DEVFN(5, 0), 0);
1068 if (*addr
!= 0xffffffffu
) {
1074 if (!hose
|| !hose
->sg_pci
)
1077 printk("MARVEL - using hose %d as AGP\n", hose
->index
);
1080 * Get the csrs from the hose.
1082 csrs
= ((struct io7_port
*)hose
->sysdata
)->csrs
;
1085 * Allocate the info structure.
1087 agp
= kmalloc(sizeof(*agp
), GFP_KERNEL
);
1095 agp
->private = NULL
;
1096 agp
->ops
= &marvel_agp_ops
;
1099 * Aperture - not configured until ops.setup().
1101 agp
->aperture
.bus_base
= 0;
1102 agp
->aperture
.size
= 0;
1103 agp
->aperture
.sysdata
= NULL
;
1108 * NOTE: IO7 reports through AGP_STAT that it can support a read queue
1109 * depth of 17 (rq = 0x10). It actually only supports a depth of
1112 agp
->capability
.lw
= csrs
->AGP_STAT
.csr
;
1113 agp
->capability
.bits
.rq
= 0xf;
1118 agp
->mode
.lw
= csrs
->AGP_CMD
.csr
;