release/src-rt-6.x.4708/include/sbpcmcia.h

   1 /*
   2  * BCM43XX Sonics SiliconBackplane PCMCIA core hardware definitions.
   3  *
   4  * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: sbpcmcia.h 361350 2012-10-08 10:09:58Z $
  19  */
  20
  21 #ifndef _SBPCMCIA_H
  22 #define _SBPCMCIA_H
  23
  24 /* All the addresses that are offsets in attribute space are divided
  25  * by two to account for the fact that odd bytes are invalid in
  26  * attribute space and our read/write routines make the space appear
  27  * as if they didn't exist. Still we want to show the original numbers
  28  * as documented in the hnd_pcmcia core manual.
  29  */
  30
  31 /* PCMCIA Function Configuration Registers */
  32 #define PCMCIA_FCR              (0x700 / 2)
  33
  34 #define FCR0_OFF                0
  35 #define FCR1_OFF                (0x40 / 2)
  36 #define FCR2_OFF                (0x80 / 2)
  37 #define FCR3_OFF                (0xc0 / 2)
  38
  39 #define PCMCIA_FCR0             (0x700 / 2)
  40 #define PCMCIA_FCR1             (0x740 / 2)
  41 #define PCMCIA_FCR2             (0x780 / 2)
  42 #define PCMCIA_FCR3             (0x7c0 / 2)
  43
  44 /* Standard PCMCIA FCR registers */
  45
  46 #define PCMCIA_COR              0
  47
  48 #define COR_RST                 0x80
  49 #define COR_LEV                 0x40
  50 #define COR_IRQEN               0x04
  51 #define COR_BLREN               0x01
  52 #define COR_FUNEN               0x01
  53
  54
  55 #define PCICIA_FCSR             (2 / 2)
  56 #define PCICIA_PRR              (4 / 2)
  57 #define PCICIA_SCR              (6 / 2)
  58 #define PCICIA_ESR              (8 / 2)
  59
  60
  61 #define PCM_MEMOFF              0x0000
  62 #define F0_MEMOFF               0x1000
  63 #define F1_MEMOFF               0x2000
  64 #define F2_MEMOFF               0x3000
  65 #define F3_MEMOFF               0x4000
  66
  67 /* Memory base in the function fcr's */
  68 #define MEM_ADDR0               (0x728 / 2)
  69 #define MEM_ADDR1               (0x72a / 2)
  70 #define MEM_ADDR2               (0x72c / 2)
  71
  72 /* PCMCIA base plus Srom access in fcr0: */
  73 #define PCMCIA_ADDR0            (0x072e / 2)
  74 #define PCMCIA_ADDR1            (0x0730 / 2)
  75 #define PCMCIA_ADDR2            (0x0732 / 2)
  76
  77 #define MEM_SEG                 (0x0734 / 2)
  78 #define SROM_CS                 (0x0736 / 2)
  79 #define SROM_DATAL              (0x0738 / 2)
  80 #define SROM_DATAH              (0x073a / 2)
  81 #define SROM_ADDRL              (0x073c / 2)
  82 #define SROM_ADDRH              (0x073e / 2)
  83 #define SROM_INFO2              (0x0772 / 2)    /* Corerev >= 2 && <= 5 */
  84 #define SROM_INFO               (0x07be / 2)    /* Corerev >= 6 */
  85
  86 /*  Values for srom_cs: */
  87 #define SROM_IDLE               0
  88 #define SROM_WRITE              1
  89 #define SROM_READ               2
  90 #define SROM_WEN                4
  91 #define SROM_WDS                7
  92 #define SROM_DONE               8
  93
  94 /* Fields in srom_info: */
  95 #define SRI_SZ_MASK             0x03
  96 #define SRI_BLANK               0x04
  97 #define SRI_OTP                 0x80
  98
  99 #if !defined(LINUX_POSTMOGRIFY_REMOVAL)
 100 /* CIS stuff */
 101
 102 /* The CIS stops where the FCRs start */
 103 #define CIS_SIZE                PCMCIA_FCR
 104
 105 /* CIS tuple length field max */
 106 #define CIS_TUPLE_LEN_MAX       0xff
 107
 108 /* Standard tuples we know about */
 109
 110 #define CISTPL_NULL                     0x00
 111 #define CISTPL_VERS_1           0x15            /* CIS ver, manf, dev & ver strings */
 112 #define CISTPL_MANFID           0x20            /* Manufacturer and device id */
 113 #define CISTPL_FUNCID           0x21            /* Function identification */
 114 #define CISTPL_FUNCE            0x22            /* Function extensions */
 115 #define CISTPL_CFTABLE          0x1b            /* Config table entry */
 116 #define CISTPL_END              0xff            /* End of the CIS tuple chain */
 117
 118 /* Function identifier provides context for the function extentions tuple */
 119 #define CISTPL_FID_SDIO         0x0c            /* Extensions defined by SDIO spec */
 120
 121 /* Function extensions for LANs (assumed for extensions other than SDIO) */
 122 #define LAN_TECH                1               /* Technology type */
 123 #define LAN_SPEED               2               /* Raw bit rate */
 124 #define LAN_MEDIA               3               /* Transmission media */
 125 #define LAN_NID                 4               /* Node identification (aka MAC addr) */
 126 #define LAN_CONN                5               /* Connector standard */
 127
 128
 129 /* CFTable */
 130 #define CFTABLE_REGWIN_2K       0x08            /* 2k reg windows size */
 131 #define CFTABLE_REGWIN_4K       0x10            /* 4k reg windows size */
 132 #define CFTABLE_REGWIN_8K       0x20            /* 8k reg windows size */
 133
 134 /* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
 135  * take one for HNBU, and use "extensions" (a la FUNCE) within it.
 136  */
 137
 138 #define CISTPL_BRCM_HNBU        0x80
 139
 140 /* Subtypes of BRCM_HNBU: */
 141
 142 #define HNBU_SROMREV            0x00    /* A byte with sromrev, 1 if not present */
 143 #define HNBU_CHIPID             0x01    /* Two 16bit values: PCI vendor & device id */
 144 #define HNBU_BOARDREV           0x02    /* One byte board revision */
 145 #define HNBU_PAPARMS            0x03    /* PA parameters: 8 (sromrev == 1)
 146                                          * or 9 (sromrev > 1) bytes
 147                                          */
 148 #define HNBU_OEM                0x04    /* Eight bytes OEM data (sromrev == 1) */
 149 #define HNBU_CC                 0x05    /* Default country code (sromrev == 1) */
 150 #define HNBU_AA                 0x06    /* Antennas available */
 151 #define HNBU_AG                 0x07    /* Antenna gain */
 152 #define HNBU_BOARDFLAGS         0x08    /* board flags (2 or 4 bytes) */
 153 #define HNBU_LEDS               0x09    /* LED set */
 154 #define HNBU_CCODE              0x0a    /* Country code (2 bytes ascii + 1 byte cctl)
 155                                          * in rev 2
 156                                          */
 157 #define HNBU_CCKPO              0x0b    /* 2 byte cck power offsets in rev 3 */
 158 #define HNBU_OFDMPO             0x0c    /* 4 byte 11g ofdm power offsets in rev 3 */
 159 #define HNBU_GPIOTIMER          0x0d    /* 2 bytes with on/off values in rev 3 */
 160 #define HNBU_PAPARMS5G          0x0e    /* 5G PA params */
 161 #define HNBU_ANT5G              0x0f    /* 4328 5G antennas available/gain */
 162 #define HNBU_RDLID              0x10    /* 2 byte USB remote downloader (RDL) product Id */
 163 #define HNBU_RSSISMBXA2G        0x11    /* 4328 2G RSSI mid pt sel & board switch arch,
 164                                          * 2 bytes, rev 3.
 165                                          */
 166 #define HNBU_RSSISMBXA5G        0x12    /* 4328 5G RSSI mid pt sel & board switch arch,
 167                                          * 2 bytes, rev 3.
 168                                          */
 169 #define HNBU_XTALFREQ           0x13    /* 4 byte Crystal frequency in kilohertz */
 170 #define HNBU_TRI2G              0x14    /* 4328 2G TR isolation, 1 byte */
 171 #define HNBU_TRI5G              0x15    /* 4328 5G TR isolation, 3 bytes */
 172 #define HNBU_RXPO2G             0x16    /* 4328 2G RX power offset, 1 byte */
 173 #define HNBU_RXPO5G             0x17    /* 4328 5G RX power offset, 1 byte */
 174 #define HNBU_BOARDNUM           0x18    /* board serial number, independent of mac addr */
 175 #define HNBU_MACADDR            0x19    /* mac addr override for the standard CIS LAN_NID */
 176 #define HNBU_RDLSN              0x1a    /* 2 bytes; serial # advertised in USB descriptor */
 177 #define HNBU_BOARDTYPE          0x1b    /* 2 bytes; boardtype */
 178 #define HNBU_LEDDC              0x1c    /* 2 bytes; LED duty cycle */
 179 #define HNBU_HNBUCIS            0x1d    /* what follows is proprietary HNBU CIS format */
 180 #define HNBU_PAPARMS_SSLPNPHY   0x1e    /* SSLPNPHY PA params */
 181 #define HNBU_RSSISMBXA2G_SSLPNPHY 0x1f /* SSLPNPHY RSSI mid pt sel & board switch arch */
 182 #define HNBU_RDLRNDIS           0x20    /* 1 byte; 1 = RDL advertises RNDIS config */
 183 #define HNBU_CHAINSWITCH        0x21    /* 2 byte; txchain, rxchain */
 184 #define HNBU_REGREV             0x22    /* 1 byte; */
 185 #define HNBU_FEM                0x23    /* 2 or 4 byte: 11n frontend specification */
 186 #define HNBU_PAPARMS_C0         0x24    /* 8 or 30 bytes: 11n pa paramater for chain 0 */
 187 #define HNBU_PAPARMS_C1         0x25    /* 8 or 30 bytes: 11n pa paramater for chain 1 */
 188 #define HNBU_PAPARMS_C2         0x26    /* 8 or 30 bytes: 11n pa paramater for chain 2 */
 189 #define HNBU_PAPARMS_C3         0x27    /* 8 or 30 bytes: 11n pa paramater for chain 3 */
 190 #define HNBU_PO_CCKOFDM         0x28    /* 6 or 18 bytes: cck2g/ofdm2g/ofdm5g power offset */
 191 #define HNBU_PO_MCS2G           0x29    /* 8 bytes: mcs2g power offset */
 192 #define HNBU_PO_MCS5GM          0x2a    /* 8 bytes: mcs5g mid band power offset */
 193 #define HNBU_PO_MCS5GLH         0x2b    /* 16 bytes: mcs5g low-high band power offset */
 194 #define HNBU_PO_CDD             0x2c    /* 2 bytes: cdd2g/5g power offset */
 195 #define HNBU_PO_STBC            0x2d    /* 2 bytes: stbc2g/5g power offset */
 196 #define HNBU_PO_40M             0x2e    /* 2 bytes: 40Mhz channel 2g/5g power offset */
 197 #define HNBU_PO_40MDUP          0x2f    /* 2 bytes: 40Mhz channel dup 2g/5g power offset */
 198
 199 #define HNBU_RDLRWU             0x30    /* 1 byte; 1 = RDL advertises Remote Wake-up */
 200 #define HNBU_WPS                0x31    /* 1 byte; GPIO pin for WPS button */
 201 #define HNBU_USBFS              0x32    /* 1 byte; 1 = USB advertises FS mode only */
 202 #define HNBU_BRMIN              0x33    /* 4 byte bootloader min resource mask */
 203 #define HNBU_BRMAX              0x34    /* 4 byte bootloader max resource mask */
 204 #define HNBU_PATCH              0x35    /* bootloader patch addr(2b) & data(4b) pair */
 205 #define HNBU_CCKFILTTYPE        0x36    /* CCK digital filter selection options */
 206 #define HNBU_OFDMPO5G           0x37    /* 4 * 3 = 12 byte 11a ofdm power offsets in rev 3 */
 207 #define HNBU_ELNA2G             0x38
 208 #define HNBU_ELNA5G             0x39
 209 #define HNBU_TEMPTHRESH 0x3A /* 2 bytes
 210                                          * byte1 tempthresh
 211                                          * byte2 period(msb 4 bits) | hysterisis(lsb 4 bits)
 212                                          */
 213 #define HNBU_UUID 0x3B /* 16 Bytes Hex */
 214
 215 #define HNBU_USBEPNUM           0x40    /* USB endpoint numbers */
 216
 217 /* POWER PER RATE for SROM V9 */
 218 #define HNBU_CCKBW202GPO       0x41    /* 2 bytes each
 219                                          * CCK Power offsets for 20 MHz rates (11, 5.5, 2, 1Mbps)
 220                                          * cckbw202gpo cckbw20ul2gpo
 221                                          */
 222
 223 #define HNBU_LEGOFDMBW202GPO    0x42    /* 4 bytes each
 224                                          * OFDM power offsets for 20 MHz Legacy rates
 225                                          * (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
 226                                          * legofdmbw202gpo  legofdmbw20ul2gpo
 227                                          */
 228
 229 #define HNBU_LEGOFDMBW205GPO   0x43    /* 4 bytes each
 230                                         * 5G band: OFDM power offsets for 20 MHz Legacy rates
 231                                         * (54, 48, 36, 24, 18, 12, 9, 6 Mbps)
 232                                         * low subband : legofdmbw205glpo  legofdmbw20ul2glpo
 233                                         * mid subband :legofdmbw205gmpo  legofdmbw20ul2gmpo
 234                                         * high subband :legofdmbw205ghpo  legofdmbw20ul2ghpo
 235                                         */
 236
 237 #define HNBU_MCS2GPO    0x44    /* 4 bytes each
 238                                      * mcs 0-7  power-offset. LSB nibble: m0, MSB nibble: m7
 239                                      * mcsbw202gpo  mcsbw20ul2gpo mcsbw402gpo
 240                                      */
 241 #define HNBU_MCS5GLPO    0x45    /* 4 bytes each
 242                                      * 5G low subband mcs 0-7 power-offset.
 243                                      * LSB nibble: m0, MSB nibble: m7
 244                                      * mcsbw205glpo  mcsbw20ul5glpo mcsbw405glpo
 245                                      */
 246 #define HNBU_MCS5GMPO    0x46    /* 4 bytes each
 247                                      * 5G mid subband mcs 0-7 power-offset.
 248                                      * LSB nibble: m0, MSB nibble: m7
 249                                      * mcsbw205gmpo  mcsbw20ul5gmpo mcsbw405gmpo
 250                                      */
 251 #define HNBU_MCS5GHPO    0x47    /* 4 bytes each
 252                                      * 5G high subband mcs 0-7 power-offset.
 253                                      * LSB nibble: m0, MSB nibble: m7
 254                                      * mcsbw205ghpo  mcsbw20ul5ghpo mcsbw405ghpo
 255                                      */
 256 #define HNBU_MCS32PO    0x48    /*  2 bytes total
 257                                  * mcs-32 power offset for each band/subband.
 258                                  * LSB nibble: 2G band, MSB nibble:
 259                                  * mcs322ghpo, mcs325gmpo, mcs325glpo, mcs322gpo
 260                                  */
 261 #define HNBU_LEG40DUPPO 0x49 /*  2 bytes total
 262                                 * Additional power offset for Legacy Dup40 transmissions.
 263                                  * Applied in addition to legofdmbw20ulXpo, X=2g, 5gl, 5gm, or 5gh.
 264                                  * LSB nibble: 2G band, MSB nibble: 5G band high subband.
 265                                  * leg40dup5ghpo, leg40dup5gmpo, leg40dup5glpo, leg40dup2gpo
 266                                  */
 267
 268 #define HNBU_PMUREGS    0x4a /* Variable length (5 bytes for each register)
 269                                 * The setting of the ChipCtrl, PLL, RegulatorCtrl, Up/Down Timer and
 270                                 * ResourceDependency Table registers.
 271                                 */
 272
 273 #define HNBU_PATCH2             0x4b    /* bootloader TCAM patch addr(4b) & data(4b) pair .
 274                                 * This is required for socram rev 15 onwards.
 275                                 */
 276
 277 #define HNBU_USBRDY             0x4c    /* Variable length (upto 5 bytes)
 278                                 * This is to indicate the USB/HSIC host controller
 279                                 * that the device is ready for enumeration.
 280                                 */
 281
 282 #define HNBU_USBREGS    0x4d    /* Variable length
 283                                 * The setting of the devcontrol, HSICPhyCtrl1 and HSICPhyCtrl2
 284                                 * registers during the USB initialization.
 285                                 */
 286
 287 #define HNBU_BLDR_TIMEOUT       0x4e    /* 2 bytes used for HSIC bootloader to reset chip
 288                                 * on connect timeout.
 289                                 * The Delay after USBConnect for timeout till dongle receives
 290                                 * get_descriptor request.
 291                                 */
 292 #define HNBU_USBFLAGS           0x4f
 293 #define HNBU_PATCH_AUTOINC      0x50
 294 #define HNBU_MDIO_REGLIST       0x51
 295 #define HNBU_MDIOEX_REGLIST     0x52
 296 /* Unified OTP: tupple to embed USB manfid inside SDIO CIS */
 297 #define HNBU_UMANFID            0x53
 298 #define HNBU_PUBKEY             0x54    /* 128 byte; publick key to validate downloaded FW */
 299 #define HNBU_MUXENAB            0x56    /* 1 byte to enable mux options */
 300 #define HNBU_GCI_CCR            0x57    /* GCI Chip control register */
 301 #define HNBU_FEM_CFG            0x58    /* FEM config */
 302 #define HNBU_ACPA_C0            0x59    /* ACPHY PA parameters: chain 0 */
 303 #define HNBU_ACPA_C1            0x5a    /* ACPHY PA parameters: chain 1 */
 304 #define HNBU_ACPA_C2            0x5b    /* ACPHY PA parameters: chain 2 */
 305 #define HNBU_MEAS_PWR           0x5c
 306 #define HNBU_PDOFF              0x5d
 307 #define HNBU_ACPPR_2GPO         0x5e    /* ACPHY Power-per-rate 2gpo */
 308 #define HNBU_ACPPR_5GPO         0x5f    /* ACPHY Power-per-rate 5gpo */
 309 #define HNBU_ACPPR_SBPO         0x60    /* ACPHY Power-per-rate sbpo */
 310 #define HNBU_NOISELVL           0x61
 311 #define HNBU_RXGAIN_ERR         0x62
 312 #define HNBU_AGBGA              0x63
 313 #define HNBU_USBDESC_COMPOSITE  0x64    /* USB WLAN/BT composite descriptor */
 314 #define HNBU_PATCH_AUTOINC8     0x65    /* Auto increment patch entry for 8 byte patching */
 315 #define HNBU_PATCH8             0x66    /* Patch entry for 8 byte patching */
 316 #define HNBU_ACRXGAINS_C0       0x67    /* ACPHY rxgains: chain 0 */
 317 #define HNBU_ACRXGAINS_C1       0x68    /* ACPHY rxgains: chain 1 */
 318 #define HNBU_ACRXGAINS_C2       0x69    /* ACPHY rxgains: chain 2 */
 319 #define HNBU_TXDUTY             0x6a    /* Tx duty cycle for ACPHY 5g 40/80 Mhz */
 320 #define HNBU_USBUTMI_CTL        0x6b    /* 2 byte USB UTMI/LDO Control */
 321 #define HNBU_PDOFF_2G           0x6c
 322 #define HNBU_USBSSPHY_UTMI_CTL0 0x6d    /* 4 byte USB SSPHY UTMI Control */
 323 #define HNBU_USBSSPHY_UTMI_CTL1 0x6e    /* 4 byte USB SSPHY UTMI Control */
 324 #define HNBU_USBSSPHY_UTMI_CTL2 0x6f    /* 4 byte USB SSPHY UTMI Control */
 325 #define HNBU_USBSSPHY_SLEEP0    0x70    /* 2 byte USB SSPHY sleep */
 326 #define HNBU_USBSSPHY_SLEEP1    0x71    /* 2 byte USB SSPHY sleep */
 327 #define HNBU_USBSSPHY_SLEEP2    0x72    /* 2 byte USB SSPHY sleep */
 328 #define HNBU_USBSSPHY_SLEEP3    0x73    /* 2 byte USB SSPHY sleep */
 329
 330 #define HNBU_SROM3SWRGN         0x80    /* 78 bytes; srom rev 3 s/w region without crc8
 331                                          * plus extra info appended.
 332                                          */
 333 #define HNBU_RESERVED           0x81    /* Reserved for non-BRCM post-mfg additions */
 334 #define HNBU_CUSTOM1            0x82    /* 4 byte; For non-BRCM post-mfg additions */
 335 #define HNBU_CUSTOM2            0x83    /* Reserved; For non-BRCM post-mfg additions */
 336
 337
 338 #endif /* !defined(LINUX_POSTMOGRIFY_REMOVAL) */
 339
 340 /* sbtmstatelow */
 341 #define SBTML_INT_ACK           0x40000         /* ack the sb interrupt */
 342 #define SBTML_INT_EN            0x20000         /* enable sb interrupt */
 343
 344 /* sbtmstatehigh */
 345 #define SBTMH_INT_STATUS        0x40000         /* sb interrupt status */
 346
 347 #endif  /* _SBPCMCIA_H */