release/src-rt-6.x.4708/include/sbhndarm.h

   1 /*
   2  * Broadcom SiliconBackplane ARM definitions
   3  *
   4  * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
   5  *
   6  * Permission to use, copy, modify, and/or distribute this software for any
   7  * purpose with or without fee is hereby granted, provided that the above
   8  * copyright notice and this permission notice appear in all copies.
   9  *
  10  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  11  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  12  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  13  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  14  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  15  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  16  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  17  *
  18  * $Id: sbhndarm.h 352647 2012-08-23 16:41:55Z $
  19  */
  20
  21 #ifndef _sbhndarm_h_
  22 #define _sbhndarm_h_
  23
  24 #include <arminc.h>
  25 #include <sbconfig.h>
  26
  27 /* register offsets */
  28 #define ARM7_CORECTL            0
  29
  30 /* bits in corecontrol */
  31 #define ACC_FORCED_RST          0x1
  32 #define ACC_SERRINT                     0x2
  33 #define ACC_WFICLKSTOP          0x4
  34 #define ACC_NOTSLEEPINGCLKREQ_SHIFT     24
  35
  36 /* arm resetlog */
  37 #define SBRESETLOG              0x1
  38 #define SERRORLOG               0x2
  39
  40 /* arm core-specific control flags */
  41 #define SICF_REMAP_MSK          0x001c
  42 #define SICF_REMAP_NONE         0
  43 #define SICF_REMAP_ROM          0x0004
  44 #define SIFC_REMAP_FLASH        0x0008
  45
  46 /* misc core-specific defines */
  47 #if defined(__ARM_ARCH_4T__)
  48 /* arm7tdmi-s */
  49 /* backplane related stuff */
  50 #define ARM_CORE_ID             ARM7S_CORE_ID   /* arm coreid */
  51 #define SI_ARM_ROM              SI_ARM7S_ROM    /* ROM backplane/system address */
  52 #define SI_ARM_SRAM2            SI_ARM7S_SRAM2  /* RAM backplane address when remap is 1 or 2 */
  53 #elif defined(__ARM_ARCH_7M__)
  54 /* cortex-m3 */
  55 /* backplane related stuff */
  56 #define ARM_CORE_ID             ARMCM3_CORE_ID  /* arm coreid */
  57 #define SI_ARM_ROM              SI_ARMCM3_ROM   /* ROM backplane/system address */
  58 #define SI_ARM_SRAM2            SI_ARMCM3_SRAM2 /* RAM backplane address when remap is 1 or 2 */
  59 /* core registers offsets */
  60 #define ARMCM3_CYCLECNT         0x90            /* Cortex-M3 core registers offsets */
  61 #define ARMCM3_INTTIMER         0x94
  62 #define ARMCM3_INTMASK          0x98
  63 #define ARMCM3_INTSTATUS        0x9c
  64 /* interrupt/exception */
  65 #define ARMCM3_NUMINTS          16              /* # of external interrupts */
  66 #define ARMCM3_INTALL           ((1 << ARMCM3_NUMINTS) - 1)     /* Interrupt mask */
  67 #define ARMCM3_FAULTMASK        0x40000000      /* Master fault enable/disable */
  68 #define ARMCM3_PRIMASK          0x80000000      /* Master interrupt enable/disable */
  69 #define ARMCM3_SHARED_INT       0               /* Interrupt shared by multiple cores */
  70 #define ARMCM3_INT(i)           (1 << (i))      /* Individual interrupt enable/disable */
  71 /* compatible with arm7tdmi-s */
  72 #define PS_I    ARMCM3_PRIMASK
  73 #define PS_F    ARMCM3_FAULTMASK
  74 /* intmask/intstatus bits */
  75 #define ARMCM3_INTMASK_TIMER    0x1
  76 #define ARMCM3_INTMASK_SYSRESET 0x4
  77 #define ARMCM3_INTMASK_LOCKUP   0x8
  78
  79 /*
  80  * Overlay Support in Rev 5
  81  */
  82 #define ARMCM3_OVL_VALID_SHIFT          0
  83 #define ARMCM3_OVL_VALID                1
  84 #define ARMCM3_OVL_SZ_SHIFT             1
  85 #define ARMCM3_OVL_SZ_MASK              0x0000000e
  86 #define ARMCM3_OVL_SZ_512B              0       /* 512B */
  87 #define ARMCM3_OVL_SZ_1KB               1       /* 1KB */
  88 #define ARMCM3_OVL_SZ_2KB               2       /* 2KB */
  89 #define ARMCM3_OVL_SZ_4KB               3       /* 4KB */
  90 #define ARMCM3_OVL_SZ_8KB               4       /* 8KB */
  91 #define ARMCM3_OVL_SZ_16KB              5       /* 16KB */
  92 #define ARMCM3_OVL_SZ_32KB              6       /* 32KB */
  93 #define ARMCM3_OVL_SZ_64KB              7       /* 64KB */
  94 #define ARMCM3_OVL_ADDR_SHIFT           9
  95 #define ARMCM3_OVL_ADDR_MASK            0x003FFE00
  96 #define ARMCM3_OVL_MAX                  16
  97
  98 #elif defined(__ARM_ARCH_7R__)
  99 /* cortex-r4 */
 100 /* backplane related stuff */
 101 #define ARM_CORE_ID             ARMCR4_CORE_ID  /* arm coreid */
 102 #define SI_ARM_ROM              SI_ARMCR4_ROM   /* ROM backplane/system address */
 103 #define SI_ARM_SRAM2            0x0     /* In the cr4 the RAM is just not available
 104                                          * when remap is 1
 105                                          */
 106
 107 /* core registers offsets */
 108 #define ARMCR4_CORECTL          0
 109 #define ARMCR4_CORECAP          4
 110 #define ARMCR4_COREST           8
 111
 112 #define ARMCR4_FIQRSTATUS       0x10
 113 #define ARMCR4_FIQMASK          0x14
 114 #define ARMCR4_IRQMASK          0x18
 115
 116 #define ARMCR4_INTSTATUS        0x20
 117 #define ARMCR4_INTMASK          0x24
 118 #define ARMCR4_CYCLECNT         0x28
 119 #define ARMCR4_INTTIMER         0x2c
 120
 121 #define ARMCR4_GPIOSEL          0x30
 122 #define ARMCR4_GPIOEN           0x34
 123
 124 #define ARMCR4_BANKIDX          0x40
 125 #define ARMCR4_BANKINFO         0x44
 126 #define ARMCR4_BANKSTBY         0x48
 127 #define ARMCR4_BANKPDA          0x4c
 128
 129 #define ARMCR4_TCAMPATCHCTRL            0x68
 130 #define ARMCR4_TCAMPATCHTBLBASEADDR     0x6C
 131 #define ARMCR4_TCAMCMDREG               0x70
 132 #define ARMCR4_TCAMDATAREG              0x74
 133 #define ARMCR4_TCAMBANKXMASKREG         0x78
 134
 135 #define ARMCR4_ROMNB_MASK       0xf00
 136 #define ARMCR4_ROMNB_SHIFT      8
 137 #define ARMCR4_TCBBNB_MASK      0xf0
 138 #define ARMCR4_TCBBNB_SHIFT     4
 139 #define ARMCR4_TCBANB_MASK      0xf
 140 #define ARMCR4_TCBANB_SHIFT     0
 141
 142 #define ARMCR4_MT_MASK          0x300
 143 #define ARMCR4_MT_SHIFT         8
 144 #define ARMCR4_MT_ROM           0x100
 145 #define ARMCR4_MT_RAM           0
 146
 147 #define ARMCR4_BSZ_MASK         0x3f
 148 #define ARMCR4_BSZ_MULT         8192
 149
 150 #define ARMCR4_TCAM_ENABLE              (1 << 31)
 151 #define ARMCR4_TCAM_CLKENAB             (1 << 30)
 152 #define ARMCR4_TCAM_PATCHCNT_MASK       0xf
 153
 154 #define ARMCR4_TCAM_CMD_DONE    (1 << 31)
 155 #define ARMCR4_TCAM_MATCH       (1 << 24)
 156 #define ARMCR4_TCAM_OPCODE_MASK (3 << 16)
 157 #define ARMCR4_TCAM_OPCODE_SHIFT 16
 158 #define ARMCR4_TCAM_ADDR_MASK   0xffff
 159 #define ARMCR4_TCAM_NONE        (0 << ARMCR4_TCAM_OPCODE_SHIFT)
 160 #define ARMCR4_TCAM_READ        (1 << ARMCR4_TCAM_OPCODE_SHIFT)
 161 #define ARMCR4_TCAM_WRITE       (2 << ARMCR4_TCAM_OPCODE_SHIFT)
 162 #define ARMCR4_TCAM_COMPARE     (3 << ARMCR4_TCAM_OPCODE_SHIFT)
 163 #define ARMCR4_TCAM_CMD_DONE_DLY        1000
 164
 165 #define ARMCR4_DATA_MASK        (~0x7)
 166 #define ARMCR4_DATA_VALID       (1 << 0)
 167
 168
 169 /* arm core-specific conrol flags */
 170 #define SICF_CPUHALT            0x0020
 171 #define SICF_UPDATEFW           0x0040
 172
 173 /* arm core-specific status flags */
 174 #define SISF_SDRENABLE          0x0001
 175 #define SISF_TCMPROT            0x0002
 176
 177 #define CHIP_SDRENABLE(sih)     (sih->boardflags2 & BFL2_SDR_EN)
 178 #define CHIP_TCMPROTENAB(sih)   (si_arm_sflags(sih) & SISF_TCMPROT)
 179
 180 #elif defined(__ARM_ARCH_7A__)
 181 /* backplane related stuff */
 182 #define ARM_CORE_ID             ARMCA9_CORE_ID  /* arm coreid */
 183
 184 #else   /* !__ARM_ARCH_4T__ && !__ARM_ARCH_7M__ && !__ARM_ARCH_7R__ */
 185 #error Unrecognized ARM Architecture
 186 #endif  /* !__ARM_ARCH_4T__ && !__ARM_ARCH_7M__ && !__ARM_ARCH_7R__ */
 187
 188 #ifndef _LANGUAGE_ASSEMBLY
 189
 190 /* cpp contortions to concatenate w/arg prescan */
 191 #ifndef PAD
 192 #define _PADLINE(line)  pad ## line
 193 #define _XSTR(line)     _PADLINE(line)
 194 #define PAD             _XSTR(__LINE__)
 195 #endif  /* PAD */
 196
 197 #if defined(__ARM_ARCH_4T__)
 198 /* arm7tdmi-s */
 199 typedef volatile struct {
 200         uint32  corecontrol;    /* 0 */
 201         uint32  sleepcontrol;   /* 4 */
 202         uint32  PAD;
 203         uint32  biststatus;     /* 0xc */
 204         uint32  firqstatus;     /* 0x10 */
 205         uint32  fiqmask;        /* 0x14 */
 206         uint32  irqmask;        /* 0x18 */
 207         uint32  PAD;
 208         uint32  resetlog;       /* 0x20 */
 209         uint32  gpioselect;     /* 0x24 */
 210         uint32  gpioenable;     /* 0x28 */
 211         uint32  PAD;
 212         uint32  bpaddrlo;       /* 0x30 */
 213         uint32  bpaddrhi;       /* 0x34 */
 214         uint32  bpdata;         /* 0x38 */
 215         uint32  bpindaccess;    /* 0x3c */
 216         uint32  PAD[104];
 217         uint32  clk_ctl_st;     /* 0x1e0 */
 218         uint32  hw_war;         /* 0x1e4 */
 219 } armregs_t;
 220 #define ARMREG(regs, reg)       (&((armregs_t *)regs)->reg)
 221 #endif  /* __ARM_ARCH_4T__ */
 222
 223 #if defined(__ARM_ARCH_7M__)
 224 /* cortex-m3 */
 225 typedef volatile struct {
 226         uint32  corecontrol;    /* 0x0 */
 227         uint32  corestatus;     /* 0x4 */
 228         uint32  PAD[1];
 229         uint32  biststatus;     /* 0xc */
 230         uint32  nmiisrst;       /* 0x10 */
 231         uint32  nmimask;        /* 0x14 */
 232         uint32  isrmask;        /* 0x18 */
 233         uint32  PAD[1];
 234         uint32  resetlog;       /* 0x20 */
 235         uint32  gpioselect;     /* 0x24 */
 236         uint32  gpioenable;     /* 0x28 */
 237         uint32  PAD[1];
 238         uint32  bpaddrlo;       /* 0x30 */
 239         uint32  bpaddrhi;       /* 0x34 */
 240         uint32  bpdata;         /* 0x38 */
 241         uint32  bpindaccess;    /* 0x3c */
 242         uint32  ovlidx;         /* 0x40 */
 243         uint32  ovlmatch;       /* 0x44 */
 244         uint32  ovladdr;        /* 0x48 */
 245         uint32  PAD[13];
 246         uint32  bwalloc;        /* 0x80 */
 247         uint32  PAD[3];
 248         uint32  cyclecnt;       /* 0x90 */
 249         uint32  inttimer;       /* 0x94 */
 250         uint32  intmask;        /* 0x98 */
 251         uint32  intstatus;      /* 0x9c */
 252         uint32  PAD[80];
 253         uint32  clk_ctl_st;     /* 0x1e0 */
 254 } cm3regs_t;
 255 #define ARMREG(regs, reg)       (&((cm3regs_t *)regs)->reg)
 256 #endif  /* __ARM_ARCH_7M__ */
 257
 258 #if defined(__ARM_ARCH_7R__)
 259 /* cortex-R4 */
 260 typedef volatile struct {
 261         uint32  corecontrol;    /* 0x0 */
 262         uint32  corecapabilities; /* 0x4 */
 263         uint32  corestatus;     /* 0x8 */
 264         uint32  biststatus;     /* 0xc */
 265         uint32  nmiisrst;       /* 0x10 */
 266         uint32  nmimask;        /* 0x14 */
 267         uint32  isrmask;        /* 0x18 */
 268         uint32  PAD[1];
 269         uint32  intstatus;      /* 0x20 */
 270         uint32  intmask;        /* 0x24 */
 271         uint32  cyclecnt;       /* 0x28 */
 272         uint32  inttimer;       /* 0x2c */
 273         uint32  gpioselect;     /* 0x30 */
 274         uint32  gpioenable;     /* 0x34 */
 275         uint32  PAD[2];
 276         uint32  bankidx;        /* 0x40 */
 277         uint32  bankinfo;       /* 0x44 */
 278         uint32  bankstbyctl;    /* 0x48 */
 279         uint32  bankpda;        /* 0x4c */
 280         uint32  PAD[6];
 281         uint32  tcampatchctrl;  /* 0x68 */
 282         uint32  tcampatchtblbaseaddr;   /* 0x6c */
 283         uint32  tcamcmdreg;     /* 0x70 */
 284         uint32  tcamdatareg;    /* 0x74 */
 285         uint32  tcambankxmaskreg;       /* 0x78 */
 286         uint32  PAD[89];
 287         uint32  clk_ctl_st;     /* 0x1e0 */
 288 } cr4regs_t;
 289 #define ARMREG(regs, reg)       (&((cr4regs_t *)regs)->reg)
 290 #endif  /* __ARM_ARCH_7R__ */
 291
 292 #endif  /* _LANGUAGE_ASSEMBLY */
 293
 294 #endif  /* _sbhndarm_h_ */