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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / include / pcie_core.h
blob259b5a4795ad2a7152ae761ab89413df8b82d833
1 /*
2 * BCM43XX PCIE core hardware definitions.
3 *
4 * Copyright (C) 2012, Broadcom Corporation. All Rights Reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * $Id: pcie_core.h 348160 2012-07-31 21:25:18Z $
19 */
20 #ifndef _PCIE_CORE_H
21 #define _PCIE_CORE_H
22
23 /* cpp contortions to concatenate w/arg prescan */
24 #ifndef PAD
25 #define _PADLINE(line) pad ## line
26 #define _XSTR(line) _PADLINE(line)
27 #define PAD _XSTR(__LINE__)
28 #endif
29
30 /* PCIE Enumeration space offsets */
31 #define PCIE_CORE_CONFIG_OFFSET 0x0
32 #define PCIE_FUNC0_CONFIG_OFFSET 0x400
33 #define PCIE_FUNC1_CONFIG_OFFSET 0x500
34 #define PCIE_FUNC2_CONFIG_OFFSET 0x600
35 #define PCIE_FUNC3_CONFIG_OFFSET 0x700
36 #define PCIE_SPROM_SHADOW_OFFSET 0x800
37 #define PCIE_SBCONFIG_OFFSET 0xE00
38
39 /* PCIE Bar0 Address Mapping. Each function maps 16KB config space */
40 #define PCIE_DEV_BAR0_SIZE 0x4000
41 #define PCIE_BAR0_WINMAPCORE_OFFSET 0x0
42 #define PCIE_BAR0_EXTSPROM_OFFSET 0x1000
43 #define PCIE_BAR0_PCIECORE_OFFSET 0x2000
44 #define PCIE_BAR0_CCCOREREG_OFFSET 0x3000
45
46 /* different register spaces to access thr'u pcie indirect access */
47 #define PCIE_CONFIGREGS 1 /* Access to config space */
48 #define PCIE_PCIEREGS 2 /* Access to pcie registers */
49
50 /* SB side: PCIE core and host control registers */
51 typedef struct sbpcieregs {
52 uint32 control; /* host mode only */
53 uint32 iocstatus; /* PCIE2: iostatus */
54 uint32 PAD[1];
55 uint32 biststatus; /* bist Status: 0x00C */
56 uint32 gpiosel; /* PCIE gpio sel: 0x010 */
57 uint32 gpioouten; /* PCIE gpio outen: 0x14 */
58 uint32 PAD[2];
59 uint32 intstatus; /* Interrupt status: 0x20 */
60 uint32 intmask; /* Interrupt mask: 0x24 */
61 uint32 sbtopcimailbox; /* sb to pcie mailbox: 0x028 */
62 uint32 obffcontrol; /* PCIE2: 0x2C */
63 uint32 obffintstatus; /* PCIE2: 0x30 */
64 uint32 obffdatastatus; /* PCIE2: 0x34 */
65 uint32 PAD[2];
66 uint32 errlog; /* PCIE2: 0x40 */
67 uint32 errlogaddr; /* PCIE2: 0x44 */
68 uint32 mailboxint; /* PCIE2: 0x48 */
69 uint32 mailboxintmsk; /* PCIE2: 0x4c */
70 uint32 PAD[44];
71
72 uint32 sbtopcie0; /* sb to pcie translation 0: 0x100 */
73 uint32 sbtopcie1; /* sb to pcie translation 1: 0x104 */
74 uint32 sbtopcie2; /* sb to pcie translation 2: 0x108 */
75 uint32 PAD[5];
76
77 /* pcie core supports in direct access to config space */
78 uint32 configaddr; /* pcie config space access: Address field: 0x120 */
79 uint32 configdata; /* pcie config space access: Data field: 0x124 */
80 union {
81 struct {
82 /* mdio access to serdes */
83 uint32 mdiocontrol; /* controls the mdio access: 0x128 */
84 uint32 mdiodata; /* Data to the mdio access: 0x12c */
85 /* pcie protocol phy/dllp/tlp register indirect access mechanism */
86 uint32 pcieindaddr; /* indirect access to the internal register: 0x130 */
87 uint32 pcieinddata; /* Data to/from the internal regsiter: 0x134 */
88 uint32 clkreqenctrl; /* >= rev 6, Clkreq rdma control : 0x138 */
89 } pcie1;
90 struct {
91 /* mdio access to serdes */
92 uint32 mdiocontrol; /* controls the mdio access: 0x128 */
93 uint32 mdiowrdata; /* write data to mdio 0x12C */
94 uint32 mdiorddata; /* read data to mdio 0x130 */
95 uint32 PAD[2];
96 } pcie2;
97 } u;
98 uint32 PAD[177];
99 uint32 pciecfg[4][64]; /* 0x400 - 0x7FF, PCIE Cfg Space */
100 uint16 sprom[64]; /* SPROM shadow Area */
101 } sbpcieregs_t;
102
103 /* PCI control */
104 #define PCIE_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
105 #define PCIE_RST 0x02 /* Value driven out to pin */
106
107 #define PCIE_CFGADDR 0x120 /* offsetof(configaddr) */
108 #define PCIE_CFGDATA 0x124 /* offsetof(configdata) */
109
110 /* Interrupt status/mask */
111 #define PCIE_INTA 0x01 /* PCIE INTA message is received */
112 #define PCIE_INTB 0x02 /* PCIE INTB message is received */
113 #define PCIE_INTFATAL 0x04 /* PCIE INTFATAL message is received */
114 #define PCIE_INTNFATAL 0x08 /* PCIE INTNONFATAL message is received */
115 #define PCIE_INTCORR 0x10 /* PCIE INTCORR message is received */
116 #define PCIE_INTPME 0x20 /* PCIE INTPME message is received */
117
118 #define PCIE_INT_MB_FN0_0 0x0100 /* PCIE to SB Mailbox int Fn0.0 is received */
119 #define PCIE_INT_MB_FN0_1 0x0200 /* PCIE to SB Mailbox int Fn0.1 is received */
120 #define PCIE_INT_MB_FN1_0 0x0400 /* PCIE to SB Mailbox int Fn1.0 is received */
121 #define PCIE_INT_MB_FN1_1 0x0800 /* PCIE to SB Mailbox int Fn1.1 is received */
122 #define PCIE_INT_MB_FN2_0 0x1000 /* PCIE to SB Mailbox int Fn2.0 is received */
123 #define PCIE_INT_MB_FN2_1 0x2000 /* PCIE to SB Mailbox int Fn2.1 is received */
124 #define PCIE_INT_MB_FN3_0 0x4000 /* PCIE to SB Mailbox int Fn3.0 is received */
125 #define PCIE_INT_MB_FN3_1 0x8000 /* PCIE to SB Mailbox int Fn3.1 is received */
126
127 /* PCIE MailboxInt/MailboxIntMask register */
128 #define PCIE_MB_TOSB_FN0_0 0x0001 /* write to assert PCIEtoSB Mailbox interrupt */
129 #define PCIE_MB_TOSB_FN0_1 0x0002
130 #define PCIE_MB_TOSB_FN1_0 0x0004
131 #define PCIE_MB_TOSB_FN1_1 0x0008
132 #define PCIE_MB_TOSB_FN2_0 0x0010
133 #define PCIE_MB_TOSB_FN2_1 0x0020
134 #define PCIE_MB_TOSB_FN3_0 0x0040
135 #define PCIE_MB_TOSB_FN3_1 0x0080
136 #define PCIE_MB_TOPCIE_FN0_0 0x0100 /* int status/mask for SBtoPCIE Mailbox interrupts */
137 #define PCIE_MB_TOPCIE_FN0_1 0x0200
138 #define PCIE_MB_TOPCIE_FN1_0 0x0400
139 #define PCIE_MB_TOPCIE_FN1_1 0x0800
140 #define PCIE_MB_TOPCIE_FN2_0 0x1000
141 #define PCIE_MB_TOPCIE_FN2_1 0x2000
142 #define PCIE_MB_TOPCIE_FN3_0 0x4000
143 #define PCIE_MB_TOPCIE_FN3_1 0x8000
144
145 /* SB to PCIE translation masks */
146 #define SBTOPCIE0_MASK 0xfc000000
147 #define SBTOPCIE1_MASK 0xfc000000
148 #define SBTOPCIE2_MASK 0xc0000000
149
150 /* Access type bits (0:1) */
151 #define SBTOPCIE_MEM 0
152 #define SBTOPCIE_IO 1
153 #define SBTOPCIE_CFG0 2
154 #define SBTOPCIE_CFG1 3
155
156 /* Prefetch enable bit 2 */
157 #define SBTOPCIE_PF 4
158
159 /* Write Burst enable for memory write bit 3 */
160 #define SBTOPCIE_WR_BURST 8
161
162 /* config access */
163 #define CONFIGADDR_FUNC_MASK 0x7000
164 #define CONFIGADDR_FUNC_SHF 12
165 #define CONFIGADDR_REG_MASK 0x0FFF
166 #define CONFIGADDR_REG_SHF 0
167
168 #define PCIE_CONFIG_INDADDR(f, r) ((((f) & CONFIGADDR_FUNC_MASK) << CONFIGADDR_FUNC_SHF) | \
169 (((r) & CONFIGADDR_REG_MASK) << CONFIGADDR_REG_SHF))
170
171 /* PCIE protocol regs Indirect Address */
172 #define PCIEADDR_PROT_MASK 0x300
173 #define PCIEADDR_PROT_SHF 8
174 #define PCIEADDR_PL_TLP 0
175 #define PCIEADDR_PL_DLLP 1
176 #define PCIEADDR_PL_PLP 2
177
178 /* PCIE protocol PHY diagnostic registers */
179 #define PCIE_PLP_MODEREG 0x200 /* Mode */
180 #define PCIE_PLP_STATUSREG 0x204 /* Status */
181 #define PCIE_PLP_LTSSMCTRLREG 0x208 /* LTSSM control */
182 #define PCIE_PLP_LTLINKNUMREG 0x20c /* Link Training Link number */
183 #define PCIE_PLP_LTLANENUMREG 0x210 /* Link Training Lane number */
184 #define PCIE_PLP_LTNFTSREG 0x214 /* Link Training N_FTS */
185 #define PCIE_PLP_ATTNREG 0x218 /* Attention */
186 #define PCIE_PLP_ATTNMASKREG 0x21C /* Attention Mask */
187 #define PCIE_PLP_RXERRCTR 0x220 /* Rx Error */
188 #define PCIE_PLP_RXFRMERRCTR 0x224 /* Rx Framing Error */
189 #define PCIE_PLP_RXERRTHRESHREG 0x228 /* Rx Error threshold */
190 #define PCIE_PLP_TESTCTRLREG 0x22C /* Test Control reg */
191 #define PCIE_PLP_SERDESCTRLOVRDREG 0x230 /* SERDES Control Override */
192 #define PCIE_PLP_TIMINGOVRDREG 0x234 /* Timing param override */
193 #define PCIE_PLP_RXTXSMDIAGREG 0x238 /* RXTX State Machine Diag */
194 #define PCIE_PLP_LTSSMDIAGREG 0x23C /* LTSSM State Machine Diag */
195
196 /* PCIE protocol DLLP diagnostic registers */
197 #define PCIE_DLLP_LCREG 0x100 /* Link Control */
198 #define PCIE_DLLP_LSREG 0x104 /* Link Status */
199 #define PCIE_DLLP_LAREG 0x108 /* Link Attention */
200 #define PCIE_DLLP_LAMASKREG 0x10C /* Link Attention Mask */
201 #define PCIE_DLLP_NEXTTXSEQNUMREG 0x110 /* Next Tx Seq Num */
202 #define PCIE_DLLP_ACKEDTXSEQNUMREG 0x114 /* Acked Tx Seq Num */
203 #define PCIE_DLLP_PURGEDTXSEQNUMREG 0x118 /* Purged Tx Seq Num */
204 #define PCIE_DLLP_RXSEQNUMREG 0x11C /* Rx Sequence Number */
205 #define PCIE_DLLP_LRREG 0x120 /* Link Replay */
206 #define PCIE_DLLP_LACKTOREG 0x124 /* Link Ack Timeout */
207 #define PCIE_DLLP_PMTHRESHREG 0x128 /* Power Management Threshold */
208 #define PCIE_DLLP_RTRYWPREG 0x12C /* Retry buffer write ptr */
209 #define PCIE_DLLP_RTRYRPREG 0x130 /* Retry buffer Read ptr */
210 #define PCIE_DLLP_RTRYPPREG 0x134 /* Retry buffer Purged ptr */
211 #define PCIE_DLLP_RTRRWREG 0x138 /* Retry buffer Read/Write */
212 #define PCIE_DLLP_ECTHRESHREG 0x13C /* Error Count Threshold */
213 #define PCIE_DLLP_TLPERRCTRREG 0x140 /* TLP Error Counter */
214 #define PCIE_DLLP_ERRCTRREG 0x144 /* Error Counter */
215 #define PCIE_DLLP_NAKRXCTRREG 0x148 /* NAK Received Counter */
216 #define PCIE_DLLP_TESTREG 0x14C /* Test */
217 #define PCIE_DLLP_PKTBIST 0x150 /* Packet BIST */
218 #define PCIE_DLLP_PCIE11 0x154 /* DLLP PCIE 1.1 reg */
219
220 #define PCIE_DLLP_LSREG_LINKUP (1 << 16)
221
222 /* PCIE protocol TLP diagnostic registers */
223 #define PCIE_TLP_CONFIGREG 0x000 /* Configuration */
224 #define PCIE_TLP_WORKAROUNDSREG 0x004 /* TLP Workarounds */
225 #define PCIE_TLP_WRDMAUPPER 0x010 /* Write DMA Upper Address */
226 #define PCIE_TLP_WRDMALOWER 0x014 /* Write DMA Lower Address */
227 #define PCIE_TLP_WRDMAREQ_LBEREG 0x018 /* Write DMA Len/ByteEn Req */
228 #define PCIE_TLP_RDDMAUPPER 0x01C /* Read DMA Upper Address */
229 #define PCIE_TLP_RDDMALOWER 0x020 /* Read DMA Lower Address */
230 #define PCIE_TLP_RDDMALENREG 0x024 /* Read DMA Len Req */
231 #define PCIE_TLP_MSIDMAUPPER 0x028 /* MSI DMA Upper Address */
232 #define PCIE_TLP_MSIDMALOWER 0x02C /* MSI DMA Lower Address */
233 #define PCIE_TLP_MSIDMALENREG 0x030 /* MSI DMA Len Req */
234 #define PCIE_TLP_SLVREQLENREG 0x034 /* Slave Request Len */
235 #define PCIE_TLP_FCINPUTSREQ 0x038 /* Flow Control Inputs */
236 #define PCIE_TLP_TXSMGRSREQ 0x03C /* Tx StateMachine and Gated Req */
237 #define PCIE_TLP_ADRACKCNTARBLEN 0x040 /* Address Ack XferCnt and ARB Len */
238 #define PCIE_TLP_DMACPLHDR0 0x044 /* DMA Completion Hdr 0 */
239 #define PCIE_TLP_DMACPLHDR1 0x048 /* DMA Completion Hdr 1 */
240 #define PCIE_TLP_DMACPLHDR2 0x04C /* DMA Completion Hdr 2 */
241 #define PCIE_TLP_DMACPLMISC0 0x050 /* DMA Completion Misc0 */
242 #define PCIE_TLP_DMACPLMISC1 0x054 /* DMA Completion Misc1 */
243 #define PCIE_TLP_DMACPLMISC2 0x058 /* DMA Completion Misc2 */
244 #define PCIE_TLP_SPTCTRLLEN 0x05C /* Split Controller Req len */
245 #define PCIE_TLP_SPTCTRLMSIC0 0x060 /* Split Controller Misc 0 */
246 #define PCIE_TLP_SPTCTRLMSIC1 0x064 /* Split Controller Misc 1 */
247 #define PCIE_TLP_BUSDEVFUNC 0x068 /* Bus/Device/Func */
248 #define PCIE_TLP_RESETCTR 0x06C /* Reset Counter */
249 #define PCIE_TLP_RTRYBUF 0x070 /* Retry Buffer value */
250 #define PCIE_TLP_TGTDEBUG1 0x074 /* Target Debug Reg1 */
251 #define PCIE_TLP_TGTDEBUG2 0x078 /* Target Debug Reg2 */
252 #define PCIE_TLP_TGTDEBUG3 0x07C /* Target Debug Reg3 */
253 #define PCIE_TLP_TGTDEBUG4 0x080 /* Target Debug Reg4 */
254
255 /* MDIO control */
256 #define MDIOCTL_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
257 #define MDIOCTL_DIVISOR_VAL 0x2
258 #define MDIOCTL_PREAM_EN 0x80 /* Enable preamble sequnce */
259 #define MDIOCTL_ACCESS_DONE 0x100 /* Tranaction complete */
260
261 /* MDIO Data */
262 #define MDIODATA_MASK 0x0000ffff /* data 2 bytes */
263 #define MDIODATA_TA 0x00020000 /* Turnaround */
264 #define MDIODATA_REGADDR_SHF_OLD 18 /* Regaddr shift (rev < 10) */
265 #define MDIODATA_REGADDR_MASK_OLD 0x003c0000 /* Regaddr Mask (rev < 10) */
266 #define MDIODATA_DEVADDR_SHF_OLD 22 /* Physmedia devaddr shift (rev < 10) */
267 #define MDIODATA_DEVADDR_MASK_OLD 0x0fc00000 /* Physmedia devaddr Mask (rev < 10) */
268 #define MDIODATA_REGADDR_SHF 18 /* Regaddr shift */
269 #define MDIODATA_REGADDR_MASK 0x007c0000 /* Regaddr Mask */
270 #define MDIODATA_DEVADDR_SHF 23 /* Physmedia devaddr shift */
271 #define MDIODATA_DEVADDR_MASK 0x0f800000 /* Physmedia devaddr Mask */
272 #define MDIODATA_WRITE 0x10000000 /* write Transaction */
273 #define MDIODATA_READ 0x20000000 /* Read Transaction */
274 #define MDIODATA_START 0x40000000 /* start of Transaction */
275
276 #define MDIODATA_DEV_ADDR 0x0 /* dev address for serdes */
277 #define MDIODATA_BLK_ADDR 0x1F /* blk address for serdes */
278
279 /* MDIO control/wrData/rdData register defines for PCIE Gen 2 */
280 #define MDIOCTL2_DIVISOR_MASK 0x7f /* clock to be used on MDIO */
281 #define MDIOCTL2_DIVISOR_VAL 0x2
282 #define MDIOCTL2_REGADDR_SHF 8 /* Regaddr shift */
283 #define MDIOCTL2_REGADDR_MASK 0x00FFFF00 /* Regaddr Mask */
284 #define MDIOCTL2_DEVADDR_SHF 24 /* Physmedia devaddr shift */
285 #define MDIOCTL2_DEVADDR_MASK 0x0f000000 /* Physmedia devaddr Mask */
286 #define MDIOCTL2_SLAVE_BYPASS 0x10000000 /* IP slave bypass */
287 #define MDIOCTL2_READ 0x20000000 /* IP slave bypass */
288
289 #define MDIODATA2_DONE 0x80000000 /* rd/wr transaction done */
290 #define MDIODATA2_MASK 0x7FFFFFFF /* rd/wr transaction data */
291 #define MDIODATA2_DEVADDR_SHF 4 /* Physmedia devaddr shift */
292
293
294 /* MDIO devices (SERDES modules)
295 * unlike old pcie cores (rev < 10), rev10 pcie serde organizes registers into a few blocks.
296 * two layers mapping (blockidx, register offset) is required
297 */
298 #define MDIO_DEV_IEEE0 0x000
299 #define MDIO_DEV_IEEE1 0x001
300 #define MDIO_DEV_BLK0 0x800
301 #define MDIO_DEV_BLK1 0x801
302 #define MDIO_DEV_BLK2 0x802
303 #define MDIO_DEV_BLK3 0x803
304 #define MDIO_DEV_BLK4 0x804
305 #define MDIO_DEV_TXPLL 0x808 /* TXPLL register block idx */
306 #define MDIO_DEV_TXCTRL0 0x820
307 #define MDIO_DEV_SERDESID 0x831
308 #define MDIO_DEV_RXCTRL0 0x840
309
310
311 /* XgxsBlk1_A Register Offsets */
312 #define BLK1_PWR_MGMT0 0x16
313 #define BLK1_PWR_MGMT1 0x17
314 #define BLK1_PWR_MGMT2 0x18
315 #define BLK1_PWR_MGMT3 0x19
316 #define BLK1_PWR_MGMT4 0x1A
317
318 /* serdes regs (rev < 10) */
319 #define MDIODATA_DEV_PLL 0x1d /* SERDES PLL Dev */
320 #define MDIODATA_DEV_TX 0x1e /* SERDES TX Dev */
321 #define MDIODATA_DEV_RX 0x1f /* SERDES RX Dev */
322 /* SERDES RX registers */
323 #define SERDES_RX_CTRL 1 /* Rx cntrl */
324 #define SERDES_RX_TIMER1 2 /* Rx Timer1 */
325 #define SERDES_RX_CDR 6 /* CDR */
326 #define SERDES_RX_CDRBW 7 /* CDR BW */
327
328 /* SERDES RX control register */
329 #define SERDES_RX_CTRL_FORCE 0x80 /* rxpolarity_force */
330 #define SERDES_RX_CTRL_POLARITY 0x40 /* rxpolarity_value */
331
332 /* SERDES PLL registers */
333 #define SERDES_PLL_CTRL 1 /* PLL control reg */
334 #define PLL_CTRL_FREQDET_EN 0x4000 /* bit 14 is FREQDET on */
335
336 /* Power management threshold */
337 #define PCIE_L0THRESHOLDTIME_MASK 0xFF00 /* bits 0 - 7 */
338 #define PCIE_L1THRESHOLDTIME_MASK 0xFF00 /* bits 8 - 15 */
339 #define PCIE_L1THRESHOLDTIME_SHIFT 8 /* PCIE_L1THRESHOLDTIME_SHIFT */
340 #define PCIE_L1THRESHOLD_WARVAL 0x72 /* WAR value */
341 #define PCIE_ASPMTIMER_EXTEND 0x01000000 /* > rev7: enable extend ASPM timer */
342
343 /* SPROM offsets */
344 #define SRSH_ASPM_OFFSET 4 /* word 4 */
345 #define SRSH_ASPM_ENB 0x18 /* bit 3, 4 */
346 #define SRSH_ASPM_L1_ENB 0x10 /* bit 4 */
347 #define SRSH_ASPM_L0s_ENB 0x8 /* bit 3 */
348 #define SRSH_PCIE_MISC_CONFIG 5 /* word 5 */
349 #define SRSH_L23READY_EXIT_NOPERST 0x8000 /* bit 15 */
350 #define SRSH_CLKREQ_OFFSET_REV5 20 /* word 20 for srom rev <= 5 */
351 #define SRSH_CLKREQ_OFFSET_REV8 52 /* word 52 for srom rev 8 */
352 #define SRSH_CLKREQ_ENB 0x0800 /* bit 11 */
353 #define SRSH_BD_OFFSET 6 /* word 6 */
354 #define SRSH_AUTOINIT_OFFSET 18 /* auto initialization enable */
355
356 /* Linkcontrol reg offset in PCIE Cap */
357 #define PCIE_CAP_LINKCTRL_OFFSET 16 /* linkctrl offset in pcie cap */
358 #define PCIE_CAP_LCREG_ASPML0s 0x01 /* ASPM L0s in linkctrl */
359 #define PCIE_CAP_LCREG_ASPML1 0x02 /* ASPM L1 in linkctrl */
360 #define PCIE_CLKREQ_ENAB 0x100 /* CLKREQ Enab in linkctrl */
361 #define PCIE_LINKSPEED_MASK 0xF0000 /* bits 0 - 3 of high word */
362 #define PCIE_LINKSPEED_SHIFT 16 /* PCIE_LINKSPEED_SHIFT */
363
364 /* Devcontrol reg offset in PCIE Cap */
365 #define PCIE_CAP_DEVCTRL_OFFSET 8 /* devctrl offset in pcie cap */
366 #define PCIE_CAP_DEVCTRL_MRRS_MASK 0x7000 /* Max read request size mask */
367 #define PCIE_CAP_DEVCTRL_MRRS_SHIFT 12 /* Max read request size shift */
368 #define PCIE_CAP_DEVCTRL_MRRS_128B 0 /* 128 Byte */
369 #define PCIE_CAP_DEVCTRL_MRRS_256B 1 /* 256 Byte */
370 #define PCIE_CAP_DEVCTRL_MRRS_512B 2 /* 512 Byte */
371 #define PCIE_CAP_DEVCTRL_MRRS_1024B 3 /* 1024 Byte */
372 #define PCIE_CAP_DEVCTRL_MPS_MASK 0x00e0 /* Max payload size mask */
373 #define PCIE_CAP_DEVCTRL_MPS_SHIFT 5 /* Max payload size shift */
374 #define PCIE_CAP_DEVCTRL_MPS_128B 0 /* 128 Byte */
375 #define PCIE_CAP_DEVCTRL_MPS_256B 1 /* 256 Byte */
376 #define PCIE_CAP_DEVCTRL_MPS_512B 2 /* 512 Byte */
377 #define PCIE_CAP_DEVCTRL_MPS_1024B 3 /* 1024 Byte */
378
379 #define PCIE_ASPM_ENAB 3 /* ASPM L0s & L1 in linkctrl */
380 #define PCIE_ASPM_L1_ENAB 2 /* ASPM L0s & L1 in linkctrl */
381 #define PCIE_ASPM_L0s_ENAB 1 /* ASPM L0s & L1 in linkctrl */
382 #define PCIE_ASPM_DISAB 0 /* ASPM L0s & L1 in linkctrl */
383
384 /* Devcontrol2 reg offset in PCIE Cap */
385 #define PCIE_CAP_DEVCTRL2_OFFSET 0x28 /* devctrl2 offset in pcie cap */
386 #define PCIE_CAP_DEVCTRL2_LTR_ENAB_MASK 0x400 /* Latency Tolerance Reporting Enable */
387
388 /* Status reg PCIE_PLP_STATUSREG */
389 #define PCIE_PLP_POLARITYINV_STAT 0x10
390
391
392 /* PCIE BRCM Vendor CAP REVID reg bits */
393 #define BRCMCAP_PCIEREV_CT_MASK 0xF00
394 #define BRCMCAP_PCIEREV_CT_SHIFT 8
395 #define BRCMCAP_PCIEREV_REVID_MASK 0xFF
396 #define BRCMCAP_PCIEREV_REVID_SHIFT 0
397
398 #define PCIE_REVREG_CT_PCIE1 0
399 #define PCIE_REVREG_CT_PCIE2 1
400
401 /* PCIE GEN2 specific defines */
402 /* PCIE BRCM Vendor Cap offsets w.r.t to vendor cap ptr */
403 #define PCIE2R0_BRCMCAP_REVID_OFFSET 4
404 #define PCIE2R0_BRCMCAP_BAR0_WIN0_WRAP_OFFSET 8
405 #define PCIE2R0_BRCMCAP_BAR0_WIN2_OFFSET 12
406 #define PCIE2R0_BRCMCAP_BAR0_WIN2_WRAP_OFFSET 16
407 #define PCIE2R0_BRCMCAP_BAR0_WIN_OFFSET 20
408 #define PCIE2R0_BRCMCAP_BAR1_WIN_OFFSET 24
409 #define PCIE2R0_BRCMCAP_SPROM_CTRL_OFFSET 28
410 #define PCIE2R0_BRCMCAP_BAR2_WIN_OFFSET 32
411 #define PCIE2R0_BRCMCAP_INTSTATUS_OFFSET 36
412 #define PCIE2R0_BRCMCAP_INTMASK_OFFSET 40
413 #define PCIE2R0_BRCMCAP_PCIE2SB_MB_OFFSET 44
414 #define PCIE2R0_BRCMCAP_BPADDR_OFFSET 48
415 #define PCIE2R0_BRCMCAP_BPDATA_OFFSET 52
416 #define PCIE2R0_BRCMCAP_CLKCTLSTS_OFFSET 56
417
418
419 #endif /* _PCIE_CORE_H */
Tomato firmware and modifications.