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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / cfe / cfe / pci / pciconf.c
blob56fc7d1830eafe2e174007392e0ed0134d4c5b5d
1 /* *********************************************************************
2 * Broadcom Common Firmware Environment (CFE)
3 *
4 * PCI Configuration File: pciconf.c
5 *
6 *********************************************************************
7 *
8 * Copyright 2001,2002,2003
9 * Broadcom Corporation. All rights reserved.
10 *
11 * This software is furnished under license and may be used and
12 * copied only in accordance with the following terms and
13 * conditions. Subject to these conditions, you may download,
14 * copy, install, use, modify and distribute modified or unmodified
15 * copies of this software in source and/or binary form. No title
16 * or ownership is transferred hereby.
17 *
18 * 1) Any source code used, modified or distributed must reproduce
19 * and retain this copyright notice and list of conditions
20 * as they appear in the source file.
21 *
22 * 2) No right is granted to use any trade name, trademark, or
23 * logo of Broadcom Corporation. The "Broadcom Corporation"
24 * name may not be used to endorse or promote products derived
25 * from this software without the prior written permission of
26 * Broadcom Corporation.
27 *
28 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
29 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
30 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
31 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
32 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
33 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
34 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
35 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
36 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
37 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
38 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
39 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
40 * THE POSSIBILITY OF SUCH DAMAGE.
41 */
42
43 /*
44 * Based in part on the algor p5064 version of pciconf.c:
45 * generic PCI bus configuration
46 * Copyright (c) 1999 Algorithmics Ltd
47 * which in turn appears to be based on PMON code.
48 */
49
50 #include "cfe_pci.h"
51 #include "cfe_timer.h"
52 #include "lib_types.h"
53 #include "lib_string.h"
54 #include "lib_printf.h"
55 #include "lib_malloc.h"
56
57 #include "pcivar.h"
58 #include "pcireg.h"
59 #include "pcidevs.h"
60 #include "ldtreg.h"
61
62 #ifndef MIN
63 #define MIN(a,b) ((a) < (b) ? (a) : (b))
64 #endif
65
66 #ifndef MAX
67 #define MAX(a,b) ((a) > (b) ? (a) : (b))
68 #endif
69
70 #define PRINTF printf
71 #define VPRINTF vprintf
72
73 extern void cfe_ledstr(const char *);
74 #define SBD_DISPLAY(msg) cfe_ledstr(msg)
75
76 int _pciverbose;
77
78 /* pci_devinfo uses sprintf(), and we don't necessarily want to drag
79 in all those tables for a minimal build, so set this function
80 pointer if it is required. */
81 void (*_pci_devinfo_func) (pcireg_t, pcireg_t, int, char *);
82
83 int _pci_enumerated = 0;
84
85 /* The "devices" here are actually PCI "functions" */
86 #ifndef PCIMAX_DEV
87 #define PCIMAX_DEV 16 /* arbitrary */
88 #endif
89 #ifndef PCIMAX_MEMWIN
90 #define PCIMAX_MEMWIN 3 /* arbitrary per device */
91 #endif
92 #ifndef PCIMAX_IOWIN
93 #define PCIMAX_IOWIN 1 /* arbitrary per device */
94 #endif
95
96 /* Summary data structures retained after configuration. */
97
98 struct pci_tree {
99 int nargs;
100 struct pci_attach_args *args;
101 };
102
103 static struct pci_tree pcitree[PCI_HOST_PORTS];
104
105
106 /* Additional configuration-time data structures. */
107
108 struct pcidev {
109 struct pci_attach_args *pa;
110 int bus;
111 unsigned char min_gnt;
112 unsigned char max_lat;
113 short nmemwin;
114 short niowin;
115 };
116
117 struct pciwin {
118 struct pcidev *dev;
119 int reg;
120 size_t size;
121 pcireg_t address;
122 };
123
124 struct pcirange {
125 pcireg_t base;
126 pcireg_t next;
127 pcireg_t limit;
128 };
129
130 static struct pci_attach_args *pciarg; /* the array of devices (external) */
131 static struct pcidev *pcidev; /* parallel attr array (internal) */
132
133 static int pci_nbus;
134 static int pcindev;
135 static int pcimaxdev;
136
137 static struct pciwin *pcimemwin; /* the array of memory windows */
138 static int pcinmemwin;
139 static int pcimaxmemwin;
140 static struct pcirange pcimemaddr;
141
142 static struct pciwin *pciiowin; /* the array of i/o windows */
143 static int pciniowin;
144 static int pcimaxiowin;
145 static struct pcirange pciioaddr;
146
147
148
149 static int lhb_secondary_bus;
150 static int lhb_subordinate_bus;
151
152
153 static void
154 print_bdf (int port, int bus, int device, int function)
155 {
156 PRINTF ("PCI");
157 if (PCI_HOST_PORTS > 1 && port >= 0)
158 PRINTF ("[%d]", port);
159 if (bus >= 0)
160 PRINTF (" bus %d", bus);
161 if (device >= 0)
162 PRINTF (" slot %d", device);
163 if (function >= 0)
164 PRINTF ("/%d", function);
165 PRINTF (": ");
166 }
167
168 static void
169 pci_bdfprintf (int port, int bus, int device, int function,
170 const char *fmt, ...)
171 {
172 va_list arg;
173
174 print_bdf (port, bus, device, function);
175 #ifdef __VARARGS_H
176 va_start(arg);
177 #else
178 va_start(arg, fmt);
179 #endif
180 VPRINTF (fmt, arg);
181 va_end(arg);
182 }
183
184 void
185 pci_tagprintf (pcitag_t tag, const char *fmt, ...)
186 {
187 va_list arg;
188 int port, bus, device, function;
189
190 pci_break_tag (tag, &port, &bus, &device, &function);
191 print_bdf (port, bus, device, function);
192
193 #ifdef __VARARGS_H
194 va_start(arg);
195 #else
196 va_start(arg, fmt);
197 #endif
198 VPRINTF (fmt, arg);
199 va_end(arg);
200 }
201
202
203 /* Initialize the pci-pci bridges and bus hierarchy. */
204
205 /* let rec */
206 static void pci_businit (int port, int bus, pci_flags_t flags);
207
208 static void
209 pci_businit_dev_func (pcitag_t tag, pci_flags_t flags)
210 {
211 pcireg_t id, class, bhlc;
212
213 class = pci_conf_read(tag, PCI_CLASS_REG);
214 id = pci_conf_read(tag, PCI_ID_REG);
215 bhlc = pci_conf_read(tag, PCI_BHLC_REG);
216
217 pcindev++;
218
219 if (PCI_CLASS(class) == PCI_CLASS_BRIDGE && PCI_HDRTYPE_TYPE(bhlc) == 1) {
220 enum {NONE, PCI, LDT} sec_type;
221 int offset;
222 int port, bus, device, function;
223 int bus2;
224 struct pci_bus *ppri, *psec;
225 pcireg_t data;
226
227 sec_type = NONE;
228 offset = 0;
229 switch (PCI_SUBCLASS(class)) {
230 case PCI_SUBCLASS_BRIDGE_PCI:
231 /* See if there is an LDT capability for the secondary. */
232 offset = pci_find_ldt_cap(tag, LDT_SECONDARY);
233 sec_type = offset == 0 ? PCI : LDT;
234 break;
235 case PCI_SUBCLASS_BRIDGE_HOST:
236 case PCI_SUBCLASS_BRIDGE_MISC:
237 /* A Type 1 host bridge (e.g., SB-1250 LDT) or an
238 X-to-LDT bridge with unassigned subclass (LDT?).
239 Probe iff the secondary is LDT (best policy?) */
240 offset = pci_find_ldt_cap(tag, LDT_SECONDARY);
241 if (offset != 0) sec_type = LDT;
242 break;
243 }
244
245 if (sec_type == NONE)
246 return;
247
248 if (sec_type == LDT && offset != 0) {
249 pcireg_t cr = pci_conf_read(tag, offset+LDT_COMMAND_CAP_OFF);
250 if ((cr & LDT_COMMAND_DOUBLE_ENDED) != 0)
251 return;
252 }
253
254 bus2 = pci_nextbus(port);
255 if (bus2 < 0)
256 return;
257 pci_nbus = bus2 + 1;
258
259 pci_break_tag(tag, &port, &bus, &device, &function);
260 ppri = pci_businfo(port, bus);
261
262 psec = pci_businfo(port, bus2);
263 psec->tag = tag;
264 psec->primary = bus;
265 psec->port = port;
266
267 /*
268 * set primary to bus, secondary to bus2, and
269 * subordinate to max possible bus number
270 */
271 data = (PCI_BUSMAX << 16) | (bus2 << 8) | bus;
272 pci_conf_write(tag, PPB_BUSINFO_REG, data);
273
274 /*
275 * set base interrupt mapping.
276 */
277 if (bus == 0) {
278 /* We assume board-specific wiring for bus 0 devices. */
279 psec->inta_shift = pci_int_shift_0(tag);
280 } else {
281 /* We assume expansion boards wired per PCI Bridge spec */
282 psec->inta_shift = (ppri->inta_shift + device) % 4;
283 }
284
285 /* if the new bus is LDT, do the fabric initialization */
286 if (sec_type == LDT)
287 psec->no_probe = ldt_chain_init(tag, port, bus2, flags);
288 else
289 psec->no_probe = 0;
290
291 #ifdef _CSWARM_
292 /* We must avoid attempting to scan the secondary bus of the
293 diagnostic sturgeon on a cswarm (MasterAbortMode == 0
294 appears not to suppress propagation of aborts). We know
295 its secondary bus number will be 2 on cswarm. */
296 if (bus2 == 2) {
297 psec->no_probe = 1;
298 }
299 #endif
300
301 if (psec->no_probe) {
302 psec->min_io_addr = 0xffffffff;
303 psec->max_io_addr = 0;
304 psec->min_mem_addr = 0xffffffff;
305 psec->max_mem_addr = 0;
306 } else
307 pci_businit(port, bus2, flags);
308
309 /* reset subordinate bus number */
310 data = (data & 0xff00ffff) | ((pci_nbus - 1) << 16);
311 pci_conf_write(tag, PPB_BUSINFO_REG, data);
312
313 if (PCI_VENDOR(id) == PCI_VENDOR_SIBYTE &&
314 PCI_PRODUCT(id) == PCI_PRODUCT_SIBYTE_SB1250_LDT &&
315 PCI_REVISION(class) == 1) {
316 lhb_secondary_bus = bus2;
317 lhb_subordinate_bus = pci_nbus - 1;
318 }
319 }
320 }
321
322 static void
323 pci_businit_dev (int port, int bus, int device, pci_flags_t flags)
324 {
325 pcitag_t tag;
326 pcireg_t bhlc;
327 int function, maxfunc;
328
329 tag = pci_make_tag(port, bus, device, 0);
330 if (!pci_canscan (tag))
331 return;
332
333 if (!pci_probe_tag(tag))
334 return;
335
336 bhlc = pci_conf_read(tag, PCI_BHLC_REG);
337 maxfunc = PCI_HDRTYPE_MULTIFN(bhlc) ? PCI_FUNCMAX : 0;
338
339 for (function = 0; function <= maxfunc; function++) {
340 tag = pci_make_tag(port, bus, device, function);
341 if (pci_probe_tag(tag))
342 pci_businit_dev_func(tag, flags);
343 }
344 }
345
346
347 static void
348 pci_businit (int port, int bus, pci_flags_t flags)
349 {
350 int device;
351 struct pci_bus *ppri = pci_businfo(port, bus);
352
353 ppri->min_io_addr = 0xffffffff;
354 ppri->max_io_addr = 0;
355 ppri->min_mem_addr = 0xffffffff;
356 ppri->max_mem_addr = 0;
357
358 /* Pass 1 errata: we must number the buses in ascending order to
359 avoid problems with the LDT host bridge capturing all
360 configuration cycles. */
361
362 for (device = 0; device <= PCI_DEVMAX; device++)
363 pci_businit_dev (port, bus, device, flags);
364 }
365
366
367 /* Scan each PCI device on the system and record its configuration
368 requirements. */
369
370 static void
371 pci_query_dev_func (pcitag_t tag)
372 {
373 pcireg_t id, class;
374 pcireg_t old, mask;
375 pcireg_t stat;
376 pcireg_t bparam;
377 pcireg_t icr;
378 pcireg_t bhlc;
379 pcireg_t t; /* used for pushing writes to cfg registers */
380 unsigned int x;
381 int reg, mapreg_end, mapreg_rom;
382 struct pci_bus *pb;
383 struct pci_attach_args *pa;
384 struct pcidev *pd;
385 struct pciwin *pm, *pi;
386 int port, bus, device, function, incr;
387 uint16_t cmd;
388 uint8_t pin, pci_int;
389
390 class = pci_conf_read(tag, PCI_CLASS_REG);
391 id = pci_conf_read(tag, PCI_ID_REG);
392 pci_break_tag(tag, &port, &bus, &device, &function);
393
394 if (_pciverbose && _pci_devinfo_func) {
395 char devinfo[256];
396 (*_pci_devinfo_func)(id, class, 1, devinfo);
397 pci_tagprintf(tag, "%s\n", devinfo);
398 }
399
400 if (pcindev >= pcimaxdev) {
401 panic ("pci: unexpected device number\n");
402 return;
403 }
404
405 pa = &pciarg[pcindev];
406 pa->pa_tag = tag;
407 pa->pa_id = id;
408 pa->pa_class = class;
409
410 pd = &pcidev[pcindev++];
411 pd->pa = pa;
412 pd->bus = bus;
413 pd->nmemwin = 0;
414 pd->niowin = 0;
415
416 pb = pci_businfo(port, bus);
417 pb->ndev++;
418
419 stat = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
420
421 /* do all devices support fast back-to-back */
422 if ((stat & PCI_STATUS_BACKTOBACK_SUPPORT) == 0)
423 pb->fast_b2b = 0; /* no, sorry */
424
425 /* do all devices run at 66 MHz */
426 if ((stat & PCI_STATUS_66MHZ_SUPPORT) == 0)
427 pb->freq66 = 0; /* no, sorry */
428
429 /* find slowest devsel */
430 x = PCI_STATUS_DEVSEL(stat);
431 if (x > pb->devsel)
432 pb->devsel = x;
433
434 bparam = pci_conf_read(tag, PCI_BPARAM_INTERRUPT_REG);
435
436 pd->min_gnt = PCI_BPARAM_GRANT (bparam);
437 pd->max_lat = PCI_BPARAM_LATENCY (bparam);
438
439 if (pd->min_gnt != 0 || pd->max_lat != 0) {
440 /* find largest minimum grant time of all devices */
441 if (pd->min_gnt != 0 && pd->min_gnt > pb->min_gnt)
442 pb->min_gnt = pd->min_gnt;
443
444 /* find smallest maximum latency time of all devices */
445 if (pd->max_lat != 0 && pd->max_lat < pb->max_lat)
446 pb->max_lat = pd->max_lat;
447
448 if (pd->max_lat != 0)
449 /* subtract our minimum on-bus time per sec from bus bandwidth */
450 pb->bandwidth -= pd->min_gnt * 4000000 /
451 (pd->min_gnt + pd->max_lat);
452 }
453
454 /* Hook any special setup code and test for skipping resource
455 allocation, e.g., for our own host bridges. */
456 if (pci_device_preset(tag) != 0)
457 return;
458
459 /* Does the function need an interrupt mapping? */
460 icr = pci_conf_read(tag, PCI_BPARAM_INTERRUPT_REG);
461 pin = PCI_INTERRUPT_PIN(icr);
462 icr &=~ (PCI_INTERRUPT_LINE_MASK << PCI_INTERRUPT_LINE_SHIFT);
463 if (pin == PCI_INTERRUPT_PIN_NONE)
464 pci_int = 0;
465 else if (bus == 0)
466 pci_int = pci_int_map_0(tag);
467 else
468 pci_int = (pb->inta_shift + device + (pin - 1)) % 4 + 1;
469 icr |= pci_int_line(pci_int) << PCI_INTERRUPT_LINE_SHIFT;
470 pci_conf_write(tag, PCI_BPARAM_INTERRUPT_REG, icr);
471
472 /* Find and size the BARs */
473 bhlc = pci_conf_read(tag, PCI_BHLC_REG);
474 switch (PCI_HDRTYPE_TYPE(bhlc)) {
475 case 0: /* Type 0 */
476 mapreg_end = PCI_MAPREG_END;
477 mapreg_rom = PCI_MAPREG_ROM;
478 break;
479 case 1: /* Type 1 (bridge) */
480 mapreg_end = PCI_MAPREG_PPB_END;
481 mapreg_rom = PCI_MAPREG_PPB_ROM;
482 break;
483 case 2: /* Type 2 (cardbus) */
484 mapreg_end = PCI_MAPREG_PCB_END;
485 mapreg_rom = PCI_MAPREG_NONE;
486 break;
487 default: /* unknown */
488 mapreg_end = PCI_MAPREG_START; /* assume none */
489 mapreg_rom = PCI_MAPREG_NONE;
490 break;
491 }
492
493 cmd = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
494 cmd &= (PCI_COMMAND_MASK << PCI_COMMAND_SHIFT); /* don't clear status */
495 pci_conf_write(tag, PCI_COMMAND_STATUS_REG,
496 cmd & ~(PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE));
497 t = pci_conf_read(tag, PCI_COMMAND_STATUS_REG); /* push the write */
498
499 for (reg = PCI_MAPREG_START; reg < mapreg_end; reg += incr) {
500 old = pci_conf_read(tag, reg);
501 pci_conf_write(tag, reg, 0xffffffff);
502 mask = pci_conf_read(tag, reg);
503 pci_conf_write(tag, reg, old);
504
505 /* Assume 4 byte reg, unless we find out otherwise below. */
506 incr = 4;
507
508 /* 0 if not implemented, all-1s if (for some reason) 2nd half
509 of 64-bit BAR or if device broken and reg not implemented
510 (should return 0). */
511 if (mask == 0 || mask == 0xffffffff)
512 continue;
513
514 if (_pciverbose >= 3)
515 pci_tagprintf (tag, "reg 0x%x = 0x%x\n", reg, mask);
516
517 if (PCI_MAPREG_TYPE(mask) == PCI_MAPREG_TYPE_IO) {
518
519 mask |= 0xffff0000; /* must be ones */
520
521 if (pciniowin >= pcimaxiowin) {
522 PRINTF ("pci: too many i/o windows\n");
523 continue;
524 }
525 pi = &pciiowin[pciniowin++];
526
527 pi->dev = pd;
528 pi->reg = reg;
529 pi->size = -(PCI_MAPREG_IO_ADDR(mask));
530 pd->niowin++;
531 } else {
532 switch (PCI_MAPREG_MEM_TYPE(mask)) {
533 case PCI_MAPREG_MEM_TYPE_32BIT:
534 case PCI_MAPREG_MEM_TYPE_32BIT_1M:
535 break;
536 case PCI_MAPREG_MEM_TYPE_64BIT:
537 incr = 8;
538 {
539 pcireg_t oldhi, maskhi;
540
541 if (reg + 4 >= PCI_MAPREG_END) {
542 pci_tagprintf (tag,
543 "misplaced 64-bit region ignored\n");
544 continue;
545 }
546
547 oldhi = pci_conf_read(tag, reg + 4);
548 pci_conf_write(tag, reg + 4, 0xffffffff);
549 maskhi = pci_conf_read(tag, reg + 4);
550 pci_conf_write(tag, reg + 4, oldhi);
551
552 if (maskhi != 0xffffffff && maskhi != 0x00000000) {
553 /* First, fix malformed 0*1* */
554 if ((maskhi & (maskhi+1)) == 0x00000000) {
555 pci_tagprintf (tag,
556 "Warning: "
557 "ill-formed 64-bit BAR (%08x)\n",
558 maskhi);
559 maskhi = 0xffffffff;
560 }
561 }
562 /* Check for 1*0*. */
563 if ((-maskhi & ~maskhi) != 0x00000000) {
564 pci_tagprintf (tag,
565 "true 64-bit region (%08x) ignored\n",
566 maskhi);
567 continue;
568 }
569 }
570 break;
571 default:
572 pci_tagprintf (tag, "reserved mapping type 0x%x\n",
573 PCI_MAPREG_MEM_TYPE(mask));
574 continue;
575 }
576
577 if (!PCI_MAPREG_MEM_PREFETCHABLE(mask))
578 pb->prefetch = 0;
579
580 if (pcinmemwin >= pcimaxmemwin) {
581 PRINTF ("pci: too many memory windows\n");
582 continue;
583 }
584 pm = &pcimemwin[pcinmemwin++];
585
586 pm->dev = pd;
587 pm->reg = reg;
588 pm->size = -(PCI_MAPREG_MEM_ADDR(mask));
589 pd->nmemwin++;
590 }
591 }
592
593 /* Finally check for Expansion ROM */
594 if (mapreg_rom != PCI_MAPREG_NONE) {
595 reg = mapreg_rom;
596 old = pci_conf_read(tag, reg);
597 pci_conf_write(tag, reg, 0xfffffffe);
598 mask = pci_conf_read(tag, reg);
599 pci_conf_write(tag, reg, old);
600
601 /* 0 if not implemented, 0xfffffffe or 0xffffffff if device
602 broken and/or register not implemented. */
603 if (mask != 0 && mask != 0xfffffffe && mask != 0xffffffff) {
604 if (_pciverbose >= 3)
605 pci_tagprintf (tag, "reg 0x%x = 0x%x\n", reg, mask);
606
607 if (pcinmemwin >= pcimaxmemwin) {
608 PRINTF ("pci: too many memory windows\n");
609 goto done;
610 }
611
612 pm = &pcimemwin[pcinmemwin++];
613 pm->dev = pd;
614 pm->reg = reg;
615 pm->size = -(PCI_MAPREG_ROM_ADDR(mask));
616 pd->nmemwin++;
617 }
618 }
619
620 done:
621 cmd |= PCI_COMMAND_INVALIDATE_ENABLE; /* any reason not to? */
622 pci_conf_write(tag, PCI_COMMAND_STATUS_REG, cmd);
623 }
624
625 static void
626 pci_query_dev (int port, int bus, int device)
627 {
628 pcitag_t tag;
629 pcireg_t bhlc;
630 int probed, function, maxfunc;
631
632 tag = pci_make_tag(port, bus, device, 0);
633 if (!pci_canscan (tag))
634 return;
635
636 if (_pciverbose >= 2)
637 pci_bdfprintf (port, bus, device, -1, "probe...");
638
639 probed = pci_probe_tag(tag);
640
641 if (_pciverbose >= 2)
642 PRINTF ("completed\n");
643
644 if (!probed)
645 return;
646
647 bhlc = pci_conf_read(tag, PCI_BHLC_REG);
648 maxfunc = PCI_HDRTYPE_MULTIFN(bhlc) ? PCI_FUNCMAX : 0;
649
650 for (function = 0; function <= maxfunc; function++) {
651 tag = pci_make_tag(port, bus, device, function);
652 if (pci_probe_tag(tag))
653 pci_query_dev_func(tag);
654 }
655
656 if (_pciverbose >= 2)
657 pci_bdfprintf (port, bus, device, -1, "done\n");
658 }
659
660
661 static void
662 pci_query (int port, int bus)
663 {
664 struct pci_bus *pb = pci_businfo(port, bus);
665 int device;
666 pcireg_t sec_status;
667 unsigned int def_ltim, max_ltim;
668
669 if (bus != 0) {
670 sec_status = pci_conf_read(pb->tag, PPB_IO_STATUS_REG);
671 pb->fast_b2b = (sec_status & PCI_STATUS_BACKTOBACK_SUPPORT) ? 1 : 0;
672 pb->freq66 = (sec_status & PCI_STATUS_66MHZ_SUPPORT) ? 1 : 0;
673 }
674
675 if (pb->no_probe)
676 pb->ndev = 0;
677 else {
678 for (device = 0; device <= PCI_DEVMAX; device++)
679 pci_query_dev (port, bus, device);
680 }
681
682 if (pb->ndev != 0) {
683 /* convert largest minimum grant time to cycle count */
684 max_ltim = pb->min_gnt * (pb->freq66 ? 66 : 33) / 4;
685
686 /* now see how much bandwidth is left to distribute */
687 if (pb->bandwidth <= 0) {
688 pci_bdfprintf (port, bus, -1, -1,
689 "warning: total bandwidth exceeded\n");
690 def_ltim = 1;
691 } else {
692 /* calculate a fair share for each device */
693 def_ltim = pb->bandwidth / pb->ndev;
694 if (def_ltim > pb->max_lat)
695 /* that would exceed critical time for some device */
696 def_ltim = pb->max_lat;
697 /* convert to cycle count */
698 def_ltim = def_ltim * (pb->freq66 ? 66 : 33) / 4;
699 }
700 /* most devices don't implement bottom three bits, so round up */
701 def_ltim = (def_ltim + 7) & ~7;
702 max_ltim = (max_ltim + 7) & ~7;
703
704 pb->def_ltim = MIN (def_ltim, 255);
705 pb->max_ltim = MIN (MAX (max_ltim, def_ltim), 255);
706 }
707 }
708
709
710 static int
711 wincompare (const void *a, const void *b)
712 {
713 const struct pciwin *wa = a, *wb = b;
714 if (wa->dev->bus != wb->dev->bus)
715 /* sort into ascending order of bus number */
716 return (int)(wa->dev->bus - wb->dev->bus);
717 else
718 /* sort into descending order of size */
719 return (int)(wb->size - wa->size);
720 }
721
722
723 static pcireg_t
724 pci_allocate_io(pcitag_t tag, size_t size)
725 {
726 pcireg_t address;
727
728 /* allocate upwards after rounding to size boundary */
729 address = (pciioaddr.next + (size - 1)) & ~(size - 1);
730 if (size != 0) {
731 if (address < pciioaddr.next || address + size > pciioaddr.limit)
732 return -1;
733 pciioaddr.next = address + size;
734 }
735 return address;
736 }
737
738 static pcireg_t
739 pci_align_io_addr(pcireg_t addr)
740 {
741 /* align to appropriate bridge boundaries (4K for Rev 1.1 Bridge Arch).
742 Over/underflow will show up in subsequent allocations. */
743 return (addr + ((1 << 12)-1)) & ~((1 << 12)-1);
744 }
745
746 static void
747 pci_assign_iowins(int port, int bus,
748 struct pciwin *pi_first, struct pciwin *pi_limit)
749 {
750 struct pciwin *pi;
751 struct pci_bus *pb = pci_businfo(port, bus);
752 pcireg_t t; /* for pushing writes */
753
754 pciioaddr.next = pci_align_io_addr(pciioaddr.next);
755
756 if (bus == lhb_secondary_bus) {
757 pb->min_io_addr = pciioaddr.next;
758 pciioaddr.next += (1 << 12);
759 pb->max_io_addr = pciioaddr.next - 1;
760 }
761
762 for (pi = pi_first; pi < pi_limit; pi++) {
763 struct pcidev *pd = pi->dev;
764 pcitag_t tag = pd->pa->pa_tag;
765 pcireg_t base;
766
767 if (pd->niowin < 0)
768 continue;
769 pi->address = pci_allocate_io (tag, pi->size);
770 if (pi->address == -1) {
771 pci_tagprintf (tag,
772 "(%d) not enough PCI i/o space (%ld requested)\n",
773 pi->reg, (long)pi->size);
774 pd->nmemwin = pd->niowin = -1;
775 continue;
776 }
777
778 if (pi->address < pb->min_io_addr)
779 pb->min_io_addr = pi->address;
780 if (pi->address + pi->size - 1 > pb->max_io_addr)
781 pb->max_io_addr = pi->address + pi->size - 1;
782
783 if (_pciverbose >= 2)
784 pci_tagprintf (tag,
785 "I/O BAR at 0x%x gets %ld bytes @ 0x%x\n",
786 pi->reg, (long)pi->size, pi->address);
787 base = pci_conf_read(tag, pi->reg);
788 base = (base & ~PCI_MAPREG_IO_ADDR_MASK) | pi->address;
789 pci_conf_write(tag, pi->reg, base);
790 t = pci_conf_read(tag, pi->reg);
791 }
792
793 if (pb->min_io_addr < pb->max_io_addr) {
794 /* if any io on bus, expand to valid bridge limit */
795 pb->max_io_addr |= ((1 << 12)-1);
796 pciioaddr.next = pb->max_io_addr + 1;
797 }
798
799 if (bus == lhb_subordinate_bus) {
800 pciioaddr.next = pci_align_io_addr(pciioaddr.next) + (1 << 12);
801 }
802 }
803
804 static void
805 pci_setup_iowins (int port)
806 {
807 struct pciwin *pi, *pi_first, *pi_limit;
808 int bus;
809
810 qsort(pciiowin, pciniowin, sizeof(struct pciwin), wincompare);
811 pi_first = pciiowin;
812 pi_limit = &pciiowin[pciniowin];
813
814 for (bus = 0; bus < pci_nbus; bus++) {
815 pi = pi_first;
816 while (pi != pi_limit && pi->dev->bus == bus)
817 pi++;
818 pci_assign_iowins(port, bus, pi_first, pi);
819 pi_first = pi;
820 }
821 }
822
823
824 static pcireg_t
825 pci_allocate_mem(pcitag_t tag, size_t size)
826 {
827 pcireg_t address;
828
829 /* allocate upwards after rounding to size boundary */
830 address = (pcimemaddr.next + (size - 1)) & ~(size - 1);
831 if (size != 0) {
832 if (address < pcimemaddr.next || address + size > pcimemaddr.limit)
833 return -1;
834 pcimemaddr.next = address + size;
835 }
836 return address;
837 }
838
839 static pcireg_t
840 pci_align_mem_addr(pcireg_t addr)
841 {
842 /* align to appropriate bridge boundaries (1M for Rev 1.1 Bridge Arch).
843 Over/underflow will show up in subsequent allocations. */
844 return (addr + ((1 << 20)-1)) & ~((1 << 20)-1);
845 }
846
847 static void
848 pci_assign_memwins(int port, int bus,
849 struct pciwin *pm_first, struct pciwin *pm_limit)
850 {
851 struct pciwin *pm;
852 struct pci_bus *pb = pci_businfo(port, bus);
853 pcireg_t t; /* for pushing writes */
854
855 pcimemaddr.next = pci_align_mem_addr(pcimemaddr.next);
856
857 if (bus == lhb_secondary_bus) {
858 pb->min_mem_addr = pcimemaddr.next;
859 pcimemaddr.next += (1 << 20);
860 pb->max_mem_addr = pcimemaddr.next - 1;
861 }
862
863 for (pm = pm_first; pm < pm_limit; ++pm) {
864 struct pcidev *pd = pm->dev;
865 pcitag_t tag = pd->pa->pa_tag;
866
867 if (pd->nmemwin < 0)
868 continue;
869 pm->address = pci_allocate_mem (tag, pm->size);
870 if (pm->address == -1) {
871 pci_tagprintf (tag,
872 "(%d) not enough PCI mem space (%ld requested)\n",
873 pm->reg, (long)pm->size);
874 pd->nmemwin = pd->niowin = -1;
875 continue;
876 }
877 if (_pciverbose >= 2)
878 pci_tagprintf (tag,
879 "%s BAR at 0x%x gets %ld bytes @ 0x%x\n",
880 pm->reg != PCI_MAPREG_ROM ? "MEM" : "ROM",
881 pm->reg, (long)pm->size, pm->address);
882
883 if (pm->address < pb->min_mem_addr)
884 pb->min_mem_addr = pm->address;
885 if (pm->address + pm->size - 1 > pb->max_mem_addr)
886 pb->max_mem_addr = pm->address + pm->size - 1;
887
888 if (pm->reg != PCI_MAPREG_ROM) {
889 /* normal memory - expansion rom done below */
890 pcireg_t base = pci_conf_read(tag, pm->reg);
891 base = pm->address | (base & ~PCI_MAPREG_MEM_ADDR_MASK);
892 pci_conf_write(tag, pm->reg, base);
893 t = pci_conf_read(tag, pm->reg);
894 if (PCI_MAPREG_MEM_TYPE(t) == PCI_MAPREG_MEM_TYPE_64BIT) {
895 pci_conf_write(tag, pm->reg + 4, 0);
896 t = pci_conf_read(tag, pm->reg + 4);
897 }
898 }
899 }
900
901 /* align final bus window */
902 if (pb->min_mem_addr < pb->max_mem_addr) {
903 pb->max_mem_addr |= ((1 << 20) - 1);
904 pcimemaddr.next = pb->max_mem_addr + 1;
905 }
906
907 if (bus == lhb_subordinate_bus) {
908 pcimemaddr.next = pci_align_mem_addr(pcimemaddr.next) + (1 << 20);
909 }
910 }
911
912 static void
913 pci_setup_memwins (int port)
914 {
915 struct pciwin *pm, *pm_first, *pm_limit;
916 int bus;
917
918 qsort(pcimemwin, pcinmemwin, sizeof(struct pciwin), wincompare);
919 pm_first = pcimemwin;
920 pm_limit = &pcimemwin[pcinmemwin];
921
922 for (bus = 0; bus < pci_nbus; bus++) {
923 pm = pm_first;
924 while (pm != pm_limit && pm->dev->bus == bus)
925 pm++;
926 pci_assign_memwins(port, bus, pm_first, pm);
927 pm_first = pm;
928 }
929
930 /* Program expansion rom address base after normal memory base,
931 to keep DEC ethernet chip happy */
932 for (pm = pcimemwin; pm < pm_limit; pm++) {
933 if (pm->reg == PCI_MAPREG_ROM && pm->address != -1) {
934 struct pcidev *pd = pm->dev; /* expansion rom */
935 pcitag_t tag = pd->pa->pa_tag;
936 pcireg_t base;
937 pcireg_t t; /* for pushing writes */
938
939 /* Do not enable ROM at this time -- PCI spec 2.2 s6.2.5.2 last
940 paragraph, says that if the expansion ROM is enabled, accesses
941 to other registers via the BARs may not be done by portable
942 software!!! */
943 base = pci_conf_read(tag, pm->reg);
944 base = pm->address | (base & ~PCI_MAPREG_ROM_ADDR_MASK);
945 base &= ~PCI_MAPREG_ROM_ENABLE;
946 pci_conf_write(tag, pm->reg, base);
947 t = pci_conf_read(tag, pm->reg);
948 }
949 }
950 }
951
952
953 static void
954 pci_setup_ppb(int port, pci_flags_t flags)
955 {
956 int i;
957
958 for (i = pci_nbus - 1; i > 0; i--) {
959 struct pci_bus *psec = pci_businfo(port, i);
960 struct pci_bus *ppri = pci_businfo(port, psec->primary);
961 if (ppri->min_io_addr > psec->min_io_addr)
962 ppri->min_io_addr = psec->min_io_addr;
963 if (ppri->max_io_addr < psec->max_io_addr)
964 ppri->max_io_addr = psec->max_io_addr;
965 if (ppri->min_mem_addr > psec->min_mem_addr)
966 ppri->min_mem_addr = psec->min_mem_addr;
967 if (ppri->max_mem_addr < psec->max_mem_addr)
968 ppri->max_mem_addr = psec->max_mem_addr;
969 }
970
971 if (_pciverbose >= 2) {
972 struct pci_bus *pb = pci_businfo(port, 0);
973 if (pb->min_io_addr < pb->max_io_addr)
974 pci_bdfprintf (port, 0, -1, -1, "io 0x%08x-0x%08x\n",
975 pb->min_io_addr, pb->max_io_addr);
976 if (pb->min_mem_addr < pb->max_mem_addr)
977 pci_bdfprintf (port, 0, -1, -1, "mem 0x%08x-0x%08x\n",
978 pb->min_mem_addr, pb->max_mem_addr);
979 }
980
981 for (i = 1; i < pci_nbus; i++) {
982 struct pci_bus *pb = pci_businfo(port, i);
983 pcireg_t cmd;
984 pcireg_t iodata, memdata;
985 pcireg_t brctl;
986 pcireg_t t; /* for pushing writes */
987
988 cmd = pci_conf_read(pb->tag, PCI_COMMAND_STATUS_REG);
989 if (_pciverbose >= 2)
990 pci_bdfprintf (port, i, -1, -1,
991 "subordinate to bus %d\n", pb->primary);
992
993 cmd |= PCI_COMMAND_MASTER_ENABLE;
994 if (pb->min_io_addr < pb->max_io_addr) {
995 uint32_t io_limit;
996
997 /* Pass 1 work-round: limits are next free, not last used. */
998 io_limit = pb->max_io_addr;
999 if (i == lhb_secondary_bus)
1000 io_limit++;
1001
1002 cmd |= PCI_COMMAND_IO_ENABLE;
1003 if (_pciverbose >= 2)
1004 pci_bdfprintf (port, i, -1, -1, "io 0x%08x-0x%08x\n",
1005 pb->min_io_addr, io_limit);
1006 iodata = pci_conf_read(pb->tag, PPB_IO_STATUS_REG);
1007 if ((iodata & PPB_IO_ADDR_CAP_MASK) == PPB_IO_ADDR_CAP_32) {
1008 pcireg_t upperdata;
1009
1010 upperdata = ((pb->min_io_addr) >> 16) & PPB_IO_UPPER_BASE_MASK;
1011 upperdata |= (io_limit & PPB_IO_UPPER_LIMIT_MASK);
1012 pci_conf_write(pb->tag, PPB_IO_UPPER_REG, upperdata);
1013 }
1014 iodata = (iodata & ~PPB_IO_BASE_MASK)
1015 | ((pb->min_io_addr >> 8) & 0xf0);
1016 iodata = (iodata & ~PPB_IO_LIMIT_MASK)
1017 | ((io_limit & PPB_IO_LIMIT_MASK) & 0xf000);
1018 } else {
1019 /* Force an empty window */
1020 iodata = pci_conf_read(pb->tag, PPB_IO_STATUS_REG);
1021 iodata &=~ (PPB_IO_BASE_MASK | PPB_IO_LIMIT_MASK);
1022 iodata |= (1 << 4) | (0 << (8+4));
1023 }
1024 pci_conf_write(pb->tag, PPB_IO_STATUS_REG, iodata);
1025 /* Push the write (see SB-1250 Errata, Section 8.10) */
1026 t = pci_conf_read(pb->tag, PPB_IO_STATUS_REG);
1027
1028 if (pb->min_mem_addr < pb->max_mem_addr) {
1029 uint32_t mem_limit;
1030
1031 mem_limit = pb->max_mem_addr;
1032 if (i == lhb_secondary_bus)
1033 mem_limit++;
1034
1035 cmd |= PCI_COMMAND_MEM_ENABLE;
1036 if (_pciverbose >= 2)
1037 pci_bdfprintf (port, i, -1, -1, "mem 0x%08x-0x%08x\n",
1038 pb->min_mem_addr, mem_limit);
1039 memdata = pci_conf_read(pb->tag, PPB_MEM_REG);
1040 memdata = (memdata & ~PPB_MEM_BASE_MASK)
1041 | ((pb->min_mem_addr >> 16) & 0xfff0);
1042 memdata = (memdata & ~PPB_MEM_LIMIT_MASK)
1043 | ((mem_limit & PPB_MEM_LIMIT_MASK) & 0xfff00000);
1044 } else {
1045 /* Force an empty window */
1046 memdata = pci_conf_read(pb->tag, PPB_MEM_REG);
1047 memdata &=~ (PPB_MEM_BASE_MASK | PPB_MEM_LIMIT_MASK);
1048 memdata |= (1 << 4) | (0 << (16+4));
1049 }
1050 pci_conf_write(pb->tag, PPB_MEM_REG, memdata);
1051 /* Push the write (see SB-1250 Errata, Section 8.10) */
1052 t = pci_conf_read(pb->tag, PPB_MEM_REG);
1053
1054 /* Force an empty prefetchable memory window */
1055 memdata = pci_conf_read(pb->tag, PPB_PREFMEM_REG);
1056 memdata &=~ (PPB_MEM_BASE_MASK | PPB_MEM_LIMIT_MASK);
1057 memdata |= (1 << 4) | (0 << (16+4));
1058 pci_conf_write(pb->tag, PPB_PREFMEM_REG, memdata);
1059 /* Push the write (see SB-1250 Errata, Section 8.10) */
1060 t = pci_conf_read(pb->tag, PPB_PREFMEM_REG);
1061
1062 /* Do any final bridge dependent initialization */
1063 pci_bridge_setup(pb->tag, flags);
1064
1065 brctl = pci_conf_read(pb->tag, PPB_BRCTL_INTERRUPT_REG);
1066 #ifdef _SB1250_PASS2_
1067 /* LDT MasterAborts _will_ cause bus errors in pass 2 when
1068 enabled. Pending negotiations with clients, leave
1069 MasterAbortMode off to disable their propagation. */
1070 #else
1071 brctl |= (PPB_BRCTL_SERR_ENABLE | PPB_BRCTL_MASTER_ABORT_MODE);
1072 #endif
1073 if (pb->fast_b2b)
1074 brctl |= PPB_BRCTL_BACKTOBACK_ENABLE;
1075 pci_conf_write(pb->tag, PPB_BRCTL_INTERRUPT_REG, brctl);
1076 t = pci_conf_read(pb->tag, PPB_BRCTL_INTERRUPT_REG); /* push */
1077
1078 pci_conf_write(pb->tag, PCI_COMMAND_STATUS_REG, cmd);
1079 }
1080 }
1081
1082
1083 int
1084 pci_cacheline_log2 (void)
1085 {
1086 /* default to 8 words == 2^3 */
1087 return 3;
1088 }
1089
1090
1091 int
1092 pci_maxburst_log2 (void)
1093 {
1094 return 32; /* no limit */
1095 }
1096
1097 static void
1098 pci_setup_devices (int port, pci_flags_t flags)
1099 {
1100 struct pcidev *pd;
1101
1102 /* Enable each PCI interface */
1103 for (pd = pcidev; pd < &pcidev[pcindev]; pd++) {
1104 struct pci_bus *pb = pci_businfo(port, pd->bus);
1105 pcitag_t tag = pd->pa->pa_tag;
1106 pcireg_t cmd, misc;
1107 unsigned int ltim;
1108
1109 /* Consider setting interrupt line here */
1110
1111 cmd = pci_conf_read(tag, PCI_COMMAND_STATUS_REG);
1112 cmd |= PCI_COMMAND_MASTER_ENABLE
1113 | PCI_COMMAND_SERR_ENABLE
1114 | PCI_COMMAND_PARITY_ENABLE;
1115 /* Always enable i/o & memory space, in case this card is
1116 just snarfing space from the fixed ISA block and doesn't
1117 declare separate PCI space. */
1118 cmd |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE;
1119 if (pb->fast_b2b)
1120 cmd |= PCI_COMMAND_BACKTOBACK_ENABLE;
1121
1122 /* Write status too, to clear any pending error bits. */
1123 pci_conf_write(tag, PCI_COMMAND_STATUS_REG, cmd);
1124
1125 ltim = pd->min_gnt * (pb->freq66 ? 66 : 33) / 4;
1126 ltim = MIN (MAX (pb->def_ltim, ltim), pb->max_ltim);
1127
1128 misc = pci_conf_read (tag, PCI_BHLC_REG);
1129 PCI_LATTIMER_SET (misc, ltim);
1130 PCI_CACHELINE_SET (misc, 1 << pci_cacheline_log2());
1131 pci_conf_write (tag, PCI_BHLC_REG, misc);
1132
1133 pci_device_setup (tag); /* hook for post setup */
1134 }
1135 }
1136
1137
1138 static void
1139 pci_configure_tree (int port, pci_flags_t flags)
1140 {
1141 int bus;
1142
1143 pciarg = NULL;
1144
1145 lhb_secondary_bus = lhb_subordinate_bus = -1;
1146
1147 /* initialise the host bridge(s) */
1148 SBD_DISPLAY ("PCIH");
1149 if (pci_hwinit(port, flags) < 0)
1150 return;
1151
1152 /* initialise any PCI-PCI bridges, discover and number buses */
1153 SBD_DISPLAY ("PCIB");
1154 pci_nbus = pci_maxbus(port) + 1;
1155 pcindev = 0;
1156 pci_businit(port, 0, flags);
1157
1158 /* scan configuration space of all devices to collect attributes */
1159 SBD_DISPLAY ("PCIS");
1160 pcimaxdev = pcindev;
1161 pciarg = (struct pci_attach_args *) KMALLOC (pcimaxdev * sizeof(struct pci_attach_args), 0);
1162 if (pciarg == NULL) {
1163 PRINTF ("pci: no memory for device table\n");
1164 pcimaxdev = 0;
1165 } else {
1166 pcidev = (struct pcidev *) KMALLOC (pcimaxdev * sizeof(struct pcidev), 0);
1167 if (pcidev == NULL) {
1168 KFREE (pciarg); pciarg = NULL;
1169 PRINTF ("pci: no memory for device attribute table\n");
1170 pcimaxdev = 0;
1171 }
1172 }
1173 pcindev = 0;
1174
1175 pcimaxmemwin = PCIMAX_DEV * PCIMAX_MEMWIN;
1176 pcimemwin = (struct pciwin *) KMALLOC (pcimaxmemwin * sizeof(struct pciwin), 0);
1177 if (pcimemwin == NULL) {
1178 PRINTF ("pci: no memory for window table\n");
1179 pcimaxmemwin = 0;
1180 }
1181 pcimaxiowin = PCIMAX_DEV * PCIMAX_IOWIN;
1182 pciiowin = (struct pciwin *) KMALLOC (pcimaxiowin * sizeof(struct pciwin), 0);
1183 if (pciiowin == NULL) {
1184 PRINTF ("pci: no memory for window table\n");
1185 pcimaxiowin = 0;
1186 }
1187
1188 pcinmemwin = pciniowin = 0;
1189 for (bus = 0; bus < pci_nbus; bus++) {
1190 pci_query (port, bus);
1191 }
1192
1193 if (pcindev != pcimaxdev) {
1194 panic ("Inconsistent device count\n");
1195 return;
1196 }
1197
1198 /* alter PCI bridge parameters based on query data */
1199 pci_hwreinit (port, flags);
1200
1201 /* setup the individual device windows */
1202 pcimemaddr.base = pci_minmemaddr(port);
1203 pcimemaddr.limit = pci_maxmemaddr(port);
1204 pciioaddr.base = pci_minioaddr(port);
1205 pciioaddr.limit = pci_maxioaddr(port);
1206
1207 pcimemaddr.next = pcimemaddr.base;
1208 pciioaddr.next = pciioaddr.base;
1209 pci_setup_iowins (port);
1210 pci_setup_memwins (port);
1211
1212 /* set up and enable each device */
1213 if (pci_nbus > 1)
1214 pci_setup_ppb (port, flags);
1215 pci_setup_devices (port, flags);
1216
1217 KFREE (pciiowin); pciiowin = NULL;
1218 KFREE (pcimemwin); pcimemwin = NULL;
1219 KFREE (pcidev); pcidev = NULL;
1220
1221 pcitree[port].nargs = pcindev;
1222 pcitree[port].args = pciarg;
1223 }
1224
1225 void
1226 pci_configure (pci_flags_t flags)
1227 {
1228 int port;
1229
1230 if (!_pci_enumerated) {
1231 _pciverbose = (PCI_DEBUG > 1) ? 3 : (flags & PCI_FLG_VERBOSE);
1232 _pci_devinfo_func = (_pciverbose != 0) ? pci_devinfo : NULL;
1233
1234 for (port = 0; port < PCI_HOST_PORTS; port++)
1235 pci_configure_tree(port, flags);
1236
1237 _pci_enumerated = 1;
1238 }
1239 }
1240
1241
1242 int
1243 pci_foreachdev(int (*fn)(pcitag_t tag))
1244 {
1245 int port, i;
1246
1247 for (port = 0; port < PCI_HOST_PORTS; port++)
1248 for (i = 0; i < pcitree[port].nargs; i++) {
1249 int rv = (*fn)(pcitree[port].args[i].pa_tag);
1250 if (rv != 0)
1251 return rv;
1252 }
1253
1254 return 0;
1255 }
1256
1257
1258 static int
1259 dump_configuration(pcitag_t tag)
1260 {
1261 pci_tagprintf(tag, "dump of ");
1262 pci_conf_print(tag);
1263 return 0;
1264 }
1265
1266 void
1267 pci_show_configuration(void)
1268 {
1269 pci_foreachdev(dump_configuration);
1270 }
1271
1272 int
1273 pci_find_class(uint32_t class, int enumidx, pcitag_t *tag)
1274 {
1275 int port, i;
1276 struct pci_attach_args *thisdev;
1277
1278 for (port = 0; port < PCI_HOST_PORTS; port++) {
1279 thisdev = pcitree[port].args;
1280 for (i = 0; i < pcitree[port].nargs && enumidx >= 0; i++) {
1281 if (PCI_CLASS(thisdev->pa_class) == class) {
1282 if (enumidx == 0) {
1283 *tag = thisdev->pa_tag;
1284 return 0;
1285 } else {
1286 enumidx--;
1287 }
1288 }
1289 thisdev++;
1290 }
1291 }
1292
1293 return -1;
1294 }
1295
1296 int
1297 pci_find_device(uint32_t vid, uint32_t did, int enumidx, pcitag_t *tag)
1298 {
1299 int port, i;
1300 struct pci_attach_args *thisdev;
1301
1302 for (port = 0; port < PCI_HOST_PORTS; port++) {
1303 thisdev = pcitree[port].args;
1304 for (i = 0; i < pcitree[port].nargs && enumidx >= 0; i++) {
1305 if ((PCI_VENDOR(thisdev->pa_id) == vid) &&
1306 (PCI_PRODUCT(thisdev->pa_id) == did)) {
1307 if (enumidx == 0) {
1308 *tag = thisdev->pa_tag;
1309 return 0;
1310 } else {
1311 enumidx--;
1312 }
1313 }
1314 thisdev++;
1315 }
1316 }
1317
1318 return -1;
1319 }
Tomato firmware and modifications.