1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * IRQ polling File: sb1250_ircpoll.S
6 * This module contains code to poll the interrupt controller
7 * and invoke the servicing of pending, unmasked interrupts.
9 *********************************************************************
11 * Copyright 2000,2001,2002,2003
12 * Broadcom Corporation. All rights reserved.
14 * This software is furnished under license and may be used and
15 * copied only in accordance with the following terms and
16 * conditions. Subject to these conditions, you may download,
17 * copy, install, use, modify and distribute modified or unmodified
18 * copies of this software in source and/or binary form. No title
19 * or ownership is transferred hereby.
21 * 1) Any source code used, modified or distributed must reproduce
22 * and retain this copyright notice and list of conditions
23 * as they appear in the source file.
25 * 2) No right is granted to use any trade name, trademark, or
26 * logo of Broadcom Corporation. The "Broadcom Corporation"
27 * name may not be used to endorse or promote products derived
28 * from this software without the prior written permission of
29 * Broadcom Corporation.
31 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
32 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
33 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
34 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
35 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
36 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
38 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
39 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
40 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
41 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
42 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
43 * THE POSSIBILITY OF SUCH DAMAGE.
44 ********************************************************************* */
46 #include "mipsmacros.h"
49 #include "sb1250_regs.h"
50 #include "sb1250_int.h"
53 * External interrupt conventions:
54 * i5 (IP7) is reserved for sources within the CPU
55 * i0 (IP2) is used for polling and always masked
56 * i1 (IP3) is used for armed interrupts that are registered (not yet)
57 * i2-i4 are available for specific devices.
60 /* EOIs are issued when LDT interrupts are programmed as levels. */
62 #define A_LDT_EOI 0x90000000d8000000
63 #define D_EOI_MDT (0x7 << 2)
66 * Dispatch function address. Access to this function pointer assumes
67 * that gp has been initialized and any relocation has been done.
77 /* *********************************************************************
78 * sb1250_irq_install()
80 * Initialize dispatch pointer. See CALLINIT_RELOC in mipsmacros.h
81 * for the logic used here. This function should be called after
82 * any relocation is done and gp is initialized.
84 * This function should be called with interrupts disabled.
91 ********************************************************************* */
96 .extern sb1250_dispatch_irq
99 _LONG_ sb1250_dispatch_irq
101 LEAF(sb1250_irq_install)
103 move a0, ra /* LOADREL can clobber */
104 LOADREL(v0,dispatch_func)
108 beq gp, zero, 1f /* is this ever ok? */
112 1: SR v0, irq_dispatch
117 END(sb1250_irq_install)
122 /* *********************************************************************
125 * Scan the interrupt_source_status and interrupt_ldt registers.
126 * For those not masked by the interrupt_mask register, invoke
127 * cfe_dispatch_irq with the interrupt number as argument.
129 * For LDT-signaled interrupts, also clear the pending vector.
131 * For asynchronous dispatch, called with interrupts disabled.
138 ********************************************************************* */
146 /* This version also shows one way of saving 64-bit registers
147 in systems that don't necessarily preserve the high 32 bits
148 across subroutine calls. That is not an issue for CFE with
149 current compilation options but is required for, e.g., 32-bit
150 Linux and NetBSD systems. */
154 daddiu sp, -56 /* saved register space */
160 andi a0, a0, M_CAUSE_IP2
163 la v0, K1BASE + A_IMR_CPU0_BASE
164 ld a1, R_IMR_INTERRUPT_MASK(v0)
165 ld s0, R_IMR_INTERRUPT_SOURCE_STATUS(v0)
166 ld s1, R_IMR_LDT_INTERRUPT(v0)
167 nor a1, a1, zero /* Negate mask to turn it into an and mask */
168 or s0, s0, s1 /* Unified pending bits */
169 and s0, s0, a1 /* Bit vector of unmasked pending IRQs */
170 and s1, s1, a1 /* ... and unmasked LDT IRQs */
171 beqz s0, 4f /* No interrupts. Return */
174 /* Clear the accumulated LDT (edge-triggered) interrupts */
175 sd s1, R_IMR_LDT_INTERRUPT_CLR(v0)
177 /* The bit scan loop */
178 dclz s1, s0 /* Find index of the next interrupt */
184 xor s0, s0, a1 /* clear current bit */
187 dsrl32 s1, s0, 0 /* Save upper 32 bits of unified vector */
189 dsll32 s0, s0, 0 /* clear upper bits of s0 */
190 dsll32 s1, s1, 0 /* get saved back in the right place */
191 dsrl32 s0, s0, 0 /* realign s0 */
192 or s0, s0, s1 /* restore the saved bits */
193 bnez s0, 3b /* More interrupts to service? */
194 dclz s1, s0 /* unroll for branch delay slot */
196 ld ra, 48(sp) /* restore registers */
201 daddiu sp, 56 /* saved register space */
208 /* *********************************************************************
211 * Set up CP0 Status and Cause per conventions above (not really -- yet)
213 * This function should be called with interrupts disabled.
220 ********************************************************************* */
232 li t1,M_SR_IMMASK /* Mask all interrupt levels */
235 or t0,t0,M_SR_IE /* but set IE */
256 LEAF(cfe_irq_disable)
259 li t1,M_SR_IMMASK|M_SR_IE
260 li t2,~(M_SR_IMMASK|M_SR_IE)
261 and v0,t0,t1 /* current mask bits */
263 mtc0 t0,C0_SR /* all enables cleared */
285 li t1,M_SR_IMMASK|M_SR_IE
286 li t2,~(M_SR_IMMASK|M_SR_IE)
305 /* *********************************************************************
306 * sb1250_update_sr(clear,set)
308 * Upate Status.IM according to masks
310 * Caller should disable interrupts if the effect is to be atomic.
313 * a0 SR bits to be cleared
314 * a1 SR bits to be set
318 ********************************************************************* */
323 LEAF(sb1250_update_sr)
327 and t0,t0,a0 /* current mask bits */
329 mtc0 t0,C0_SR /* all enables cleared */
339 END(sb1250_update_sr)