release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/src/diag_l2cache.S

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  L2 Cache Diagnostic                      File: diag_l2cache.S
   5     *
   6     *  A diagnostic for the L2 cache.  On pass2 parts, this diag
   7     *  will disable portions of the cache as necessary.
   8     *
   9     *  Author:  Zongbo Chen (zongbo@broadcom.com)
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This software is furnished under license and may be used and
  17     *  copied only in accordance with the following terms and
  18     *  conditions.  Subject to these conditions, you may download,
  19     *  copy, install, use, modify and distribute modified or unmodified
  20     *  copies of this software in source and/or binary form.  No title
  21     *  or ownership is transferred hereby.
  22     *
  23     *  1) Any source code used, modified or distributed must reproduce
  24     *     and retain this copyright notice and list of conditions
  25     *     as they appear in the source file.
  26     *
  27     *  2) No right is granted to use any trade name, trademark, or
  28     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  29     *     name may not be used to endorse or promote products derived
  30     *     from this software without the prior written permission of
  31     *     Broadcom Corporation.
  32     *
  33     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  34     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  35     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  37     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  38     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  39     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  41     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  42     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  43     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  44     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  45     *     THE POSSIBILITY OF SUCH DAMAGE.
  46     ********************************************************************* */
  47
  48 #include "sb1250_defs.h"        /* include definitions for MAKEMASK etc. */
  49 #include "diag_l1cache.h"
  50 #include "sb1250_l2c.h"
  51 #include "sb1250_scd.h"
  52 #include "sb1250_regs.h"
  53 #include "sbmips.h"
  54 #include "diag_l2util.h"
  55 #include "mipsmacros.h"
  56 #include "sb1250_genbus.h"
  57 #include "bsp_config.h"
  58
  59 /*#define _SIMULATOR_*/
  60
  61 /*
  62  * This lets us override the WID by poking values into our PromICE
  63  */
  64 #ifdef _MAGICWID_
  65 #undef A_SCD_SYSTEM_REVISION
  66 #define A_SCD_SYSTEM_REVISION 0x1FC00508
  67 #endif
  68
  69 /* We'll always define pass2.  This routine will not be run unless
  70    we're on a pass2 cpu */
  71
  72 #ifndef _SB1250_PASS2_
  73 #define _SB1250_PASS2_
  74 #endif
  75
  76 #define C0_DEBUG $23
  77 #define C0_DataLo C0_TAGLO
  78 #define C0_DataHi C0_TAGHI
  79 #define C0_TagLo C0_TAGLO
  80 #define C0_TagHi  C0_TAGHI
  81
  82 #define DMTC0s(reg, c0reg, sel) \
  83         dmtc0   reg, c0reg, sel; \
  84         ssnop                   ; \
  85         ssnop
  86
  87 #define DMFC0s(reg, c0reg, sel) \
  88         dmfc0   reg, c0reg, sel; \
  89         ssnop                   ; \
  90         ssnop
  91
  92 #define MTC0s(reg, c0reg, sel) \
  93         mtc0   reg, c0reg, sel; \
  94         ssnop                   ; \
  95         ssnop
  96
  97 #define MFC0s(reg, c0reg, sel) \
  98         mfc0   reg, c0reg, sel; \
  99         ssnop                   ; \
 100         ssnop
 101
 102 #define DMFC0(reg, c0reg ) \
 103         dmfc0   reg, c0reg; \
 104         ssnop                   ; \
 105         ssnop
 106
 107 #define DMTC0(reg, c0reg) \
 108         dmtc0   reg, c0reg; \
 109         ssnop                   ; \
 110         ssnop
 111
 112 #undef MFC0                     /* avoid redef'n of mipsmacros.h version */
 113 #define MFC0(reg, c0reg ) \
 114         mfc0   reg, c0reg; \
 115         ssnop                   ; \
 116         ssnop
 117
 118 #undef MTC0                     /* avoid redef'n of mipsmacros.h version */
 119 #define MTC0(reg, c0reg) \
 120         mtc0   reg, c0reg; \
 121         ssnop                   ; \
 122         ssnop
 123
 124 #ifdef _SIMULATOR_
 125 #define LINES_TO_TEST 2
 126 #define LOOP_COUNT 0x16
 127 #else
 128 #define TEST_ALL_LINES
 129 #define LOOP_COUNT 0x1600000
 130 #endif
 131
 132 #define START_BLK 0
 133 #define TOTAL_BLKS 16
 134
 135 #define XKPHYS_C_COH    0x8000000000000000
 136 #define XKPHYS_U_ACC    0xb800000000000000
 137 #define XKPHYS_C_COH_EXC 0xa000000000000000
 138 #define XKPHYS_UNC      0x9000000000000000
 139
 140 #define L2_RAM_BASE_ADDR        0x00D0180000
 141 #define L2M_READ_RAW_ACCESS 0x00200000
 142 #define L2M_WRITE_LAST_ECC  0x00400000
 143 #define L2M_WRITE_TAG       0x00200000
 144 #define L2M_WRITE_TAG_LAST_ECC 0x00600000
 145
 146 #undef PHYS_TO_XKPHYS                   /* avoid redef'n of sbmips.h version */
 147 #define PHYS_TO_XKPHYS(x) (0x8000000000000000|(x))
 148 #define PHYS_TO_XKPHYS_UNC(x) (0x9000000000000000|(x))
 149
 150 #define C0_Status               $12
 151 #undef C0_SR                            /* avoid redef'n of sbmips.h version */
 152 #define C0_SR                   C0_Status
 153 #define C0_Debug                C0_DEBUG
 154 #define SR_KX                   (1 << 7)
 155
 156 #ifdef LEDS_PHYS
 157 #define USE_LEDS
 158 #endif
 159
 160 #define RUN_FROM_K0
 161
 162 #define LED_CHAR0       (32+8*3)
 163 #define LED_CHAR1       (32+8*2)
 164 #define LED_CHAR2       (32+8*1)
 165 #define LED_CHAR3       (32+8*0)
 166
 167 #define MAC2_HASH0              0x10066240
 168
 169 #define SET_LEDS(leds, temp0, temp1) \
 170         li      temp0, PHYS_TO_K1(LEDS_PHYS); \
 171         srl     temp1, leds, 24; \
 172         and     temp1, temp1, 0xFF; \
 173         sb      temp1, LED_CHAR0(temp0); \
 174         srl     temp1, leds, 16; \
 175         and     temp1, temp1, 0xFF; \
 176         sb      temp1, LED_CHAR1(temp0); \
 177         srl     temp1, leds, 8; \
 178         and     temp1, temp1, 0xFF; \
 179         sb      temp1, LED_CHAR2(temp0); \
 180         and     temp1, leds, 0xFF; \
 181         sb      temp1, LED_CHAR3(temp0)
 182
 183
 184 #define SET_LEDS_HI(leds, temp0, temp1) \
 185         li      temp0, PHYS_TO_XKPHYS_UNC(LEDS_PHYS); \
 186         srl     temp1, leds, 8; \
 187         and     temp1, temp1, 0xFF; \
 188         sb      temp1, LED_CHAR0(temp0); \
 189         and     temp1, leds, 0xFF; \
 190         sb      temp1, LED_CHAR1(temp0)
 191
 192 #define SET_LEDS_LO(leds, temp0, temp1) \
 193         li      temp0, PHYS_TO_XKPHYS_UNC(LEDS_PHYS); \
 194         srl     temp1, leds, 8; \
 195         and     temp1, temp1, 0xFF; \
 196         sb      temp1, LED_CHAR2(temp0); \
 197         and     temp1, leds, 0xFF; \
 198         sb      temp1, LED_CHAR3(temp0)
 199
 200 #define DATA_TEST
 201 #define DATA_ECC_TEST
 202
 203
 204 #define LED_CHAR0       (32+8*3)
 205 #define LED_CHAR1       (32+8*2)
 206 #define LED_CHAR2       (32+8*1)
 207 #define LED_CHAR3       (32+8*0)
 208
 209
 210
 211         .text
 212         .set mips64
 213
 214
 215 #define DISAB_TOP    0x800
 216 #define DISAB_BOT    0x400
 217 #define DISAB_RGT    0x200
 218 #define DISAB_LFT    0x100
 219 #define FAILURE      0xFFFFFFFF /* complete failure, cannot continue */
 220
 221
 222 disab_table:
 223
 224 /*
 225  * This table maps failure modes to "disable" masks.
 226  * For each combination of failed quadrants, disable half
 227  * the cache that contains those quadrants.  Note that since
 228  * we can only disable top OR bottom and left OR right, not
 229  * all combinations will work and will yield diagnostic failure.
 230  */
 231
 232         .word   0                       /* Entire cache functional */
 233         .word   DISAB_LFT               /* BR=Good TR=Good BL=Good TL=BAD  */
 234         .word   DISAB_LFT               /* BR=Good TR=Good BL=BAD  TL=Good */
 235         .word   DISAB_LFT               /* BR=Good TR=Good BL=BAD  TL=BAD  */
 236         .word   DISAB_RGT               /* BR=Good TR=BAD  BL=Good TL=Good */
 237         .word   DISAB_TOP|DISAB_RGT     /* BR=Good TR=BAD  BL=Good TL=BAD  */
 238         .word   DISAB_RGT|DISAB_BOT     /* BR=Good TR=BAD  BL=BAD  TL=Good */
 239         .word   DISAB_LFT|DISAB_TOP     /* BR=Good TR=BAD  BL=BAD  TL=BAD  */
 240         .word   DISAB_RGT               /* BR=BAD  TR=Good BL=Good TL=Good */
 241         .word   DISAB_LFT|DISAB_BOT     /* BR=BAD  TR=Good BL=Good TL=BAD  */
 242         .word   DISAB_BOT|DISAB_RGT     /* BR=BAD  TR=Good BL=BAD  TL=Good */
 243         .word   DISAB_LFT|DISAB_BOT     /* BR=BAD  TR=Good BL=BAD  TL=BAD  */
 244         .word   DISAB_RGT               /* BR=BAD  TR=BAD  BL=Good TL=Good */
 245         .word   DISAB_RGT|DISAB_TOP     /* BR=BAD  TR=BAD  BL=Good TL=BAD  */
 246         .word   DISAB_RGT|DISAB_BOT     /* BR=BAD  TR=BAD  BL=BAD  TL=Good */
 247         .word   FAILURE                 /* BR=BAD  TR=BAD  BL=BAD  TL=BAD  */
 248
 249
 250
 251
 252 LEAF(diag_main)
 253
 254         move    fp, ra
 255
 256         /*
 257          * Don't do any of this diagnostic unless we're greater than PASS2 SB1250.
 258          */
 259
 260         la      t0,PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
 261         ld      t0,0(t0)                /* get system revision */
 262
 263         and     t1,t0,(0xF0FF << S_SYS_PART)   /* ignore CPU count */
 264         li      t2,V_SYS_PART(0x1050)          /* test against ignored count */
 265         bne     t2,t1,2f                        /* go if not a sb1x50 */
 266          nop
 267
 268         and     t1,t0,M_SYS_REVISION
 269         li      t2,V_SYS_REVISION(K_SYS_REVISION_PASS3)
 270         bge     t1,t2,3f                        /* run diags if >= pass3 (0x20) */
 271          nop
 272         li      t2,V_SYS_REVISION(K_SYS_REVISION_PASS2)
 273         bge     t1,t2,1f                        /* go if pass2 or better (>= 0x03) */
 274          nop
 275 2:      j       ra
 276          nop
 277
 278 1:      dsrl    t1,t0,S_SYS_WID                 /* Get Wafer ID register */
 279         bne     t1,zero,2b                      /* leave if register is set (no diags) */
 280         /* Otherwise, run the diagnostic if the wafer ID is not set. */
 281         /* Special case of A6 parts (revid==4 && wid!=0) will NOT run diags */
 282
 283 3:
 284
 285 #ifdef USE_LEDS
 286         dli     t8, (('J'<<24)|('U'<<16)|('M'<<8)|'P')
 287         SET_LEDS(t8, t6, t7)
 288 #endif
 289
 290 #ifdef RUN_FROM_K0
 291         MFC0    (t2,C0_CONFIG)
 292         dsrl    t2, t2, 3
 293         dsll    t2, t2, 3
 294         or      t2, t2, 1
 295         MTC0    (t2,C0_CONFIG)
 296         jal     to_kseg0
 297         nop
 298 #endif
 299
 300 #ifdef USE_LEDS
 301         dli     t8, (('C'<<24)|('A'<<16)|('S'<<8)|'H')
 302         SET_LEDS(t8, t6, t7)
 303 #endif
 304
 305 #ifdef RUN_FROM_K0
 306         li      t0, LOOP_COUNT
 307 1:      addi    t0, t0, -1
 308         bne     t0, zero, 1b
 309 #endif
 310
 311 /* set up for 64 bit addressing */
 312         DMFC0   (t2,C0_SR)
 313         or      t1,t2,SR_KX
 314         DMTC0   (t1,C0_SR)
 315
 316         MFC0s  (t2,C0_Debug,2)
 317         or      t1, t2, 0x3004
 318         MTC0s  (t1,C0_Debug,2)
 319
 320         /* initialize the cache */
 321         jal     sb1250_l2cache_init1
 322
 323         /* use mac2 hash0 reg as result reg, init it to 0 */
 324         li      t0, PHYS_TO_XKPHYS_UNC(MAC2_HASH0)
 325         move    t1, zero
 326         sd      t1, 0(t0)
 327
 328         /* init quarter number to 0 */
 329         move    k0, $0
 330
 331 next_quarter:
 332         move    v0, $0
 333 #ifdef DATA_TEST
 334         jal     l2dtest_bg_rw_uac
 335         nop
 336         or      t0, v0, v1
 337         or      t0, t0, s4
 338         or      t0, t0, s5
 339         bne     t0, $0, test_fail
 340 data_fail:
 341         /*bne   v0, $0, data_fail*/
 342         nop
 343
 344 #ifdef RUN_FROM_K0
 345         li      t0, LOOP_COUNT
 346 1:      addi    t0, t0, -1
 347         bne     t0, zero, 1b
 348 #endif
 349
 350 #ifdef DATA_ECC_TEST
 351         jal     l2dtest_data_ecc
 352         nop
 353         or      t0, v0, v1
 354         or      t0, t0, s4
 355         or      t0, t0, s5
 356         bne     t0, $0, test_fail
 357 ecc_fail:
 358         /*bne   v0, $0, ecc_fail*/
 359         nop
 360 #endif
 361
 362 /*
 363 #else
 364 */
 365
 366 #ifdef RUN_FROM_K0
 367         li      t0, LOOP_COUNT
 368 1:      addi    t0, t0, -1
 369         bne     t0, zero, 1b
 370 #endif
 371
 372         jal     l2dtest_tag_data
 373         nop
 374         or      t0, v0, v1
 375         or      t0, t0, s4
 376         or      t0, t0, s5
 377         bne     t0, $0, test_fail
 378 tag_fail:
 379         /*bne   v0, $0, tag_fail*/
 380         nop
 381
 382 #ifdef RUN_FROM_K0
 383         li      t0, LOOP_COUNT
 384 1:      addi    t0, t0, -1
 385         bne     t0, zero, 1b
 386 #endif
 387
 388         jal     l2dtest_tag_ecc
 389         nop
 390         or      t0, v0, v1
 391         or      t0, t0, s4
 392         or      t0, t0, s5
 393         bne     t0, $0, test_fail
 394 tagecc_fail:
 395         /*bne   v0, $0, tagecc_fail*/
 396         nop
 397         j       test_success
 398         nop
 399 #endif
 400
 401 #ifdef RUN_FROM_K0
 402         li      t0, LOOP_COUNT
 403 1:      addi    t0, t0, -1
 404         bne     t0, zero, 1b
 405         nop
 406 #endif
 407
 408 test_fail:
 409         addi    t0, zero, 1
 410         sll     t0, t0, k0
 411         li      t1, PHYS_TO_XKPHYS_UNC(MAC2_HASH0)
 412         ld      t2, 0(t1)
 413         or      t0, t0, t2
 414         sd      t0, 0(t1)
 415
 416 test_success:
 417         addi    k0, k0, 1
 418         slt     t0, k0, 4
 419         bne     t0, zero, next_quarter
 420
 421     DMFC0       (t2,C0_SR)
 422     li  t0, SR_KX
 423     not t0, t0
 424     and t1,t2,t0
 425     DMTC0       (t1,C0_SR)
 426
 427
 428 /*
 429  * Disable the bad quadrant(s) of the cache
 430  */
 431
 432         li      t1,PHYS_TO_K1(MAC2_HASH0)
 433         ld      t1,0(t1)
 434         LOADREL(t2,disab_table)
 435         sll     t1,2                    /* make a word offset */
 436         add     t2,t2,t1                /* into the table */
 437         lw      t0,(t2)                 /* this is the disable mask */
 438         blt     t0,zero,diag_fail       /* go if total failure */
 439          nop
 440
 441         li      t1,PHYS_TO_K1(A_L2_CACHE_DISABLE)
 442         or      t1,t1,t0                /* OR in appropriate disable bits */
 443
 444 #ifdef _SB1250_PASS2_
 445         sd      t0,0(t1)                /* disable the cache */
 446 #else
 447         bne     t0,zero,diag_fail       /* on pass1, any failure is bad */
 448          nop
 449 #endif
 450
 451         MFC0s  (t2,C0_Debug,2)          /* turn off things we defeatured */
 452         and      t1, t2, ~0x3004
 453         MTC0s  (t1,C0_Debug,2)
 454
 455 #ifdef USE_LEDS
 456
 457         dli     t8, (('D'<<24)|('O'<<16)|('N'<<8)|'E')
 458         SET_LEDS(t8, t6, t7)
 459 #endif
 460
 461         move    ra, fp
 462         j               ra
 463          nop
 464
 465 diag_fail:
 466
 467         li      t1,PHYS_TO_K1(MAC2_HASH0)
 468         ld      t1,0(t1)
 469         add     t1,t1,'0'
 470         ble     t1,'9',1f
 471          nop
 472         add     t1,t1,('A'-('9'+1))
 473 1:
 474         dli     t8, (('L'<<24)|('2'<<16)|(' '<<8)|0)
 475         or      t8,t8,t1
 476 #ifdef USE_LEDS
 477         SET_LEDS(t8, t6, t7)
 478 #endif
 479
 480 1:      b            1b
 481
 482
 483 END(diag_main)
 484
 485 #ifdef TEST_ALL_LINES
 486 #define L2_LINES_PER_BLOCK 256
 487 #else
 488 #define L2_LINES_PER_BLOCK LINES_TO_TEST
 489 #endif
 490
 491 #define R_WRBC_RBLK     s1
 492 #define R_WRBC_LINE     s2
 493 #define R_WRBC_NEXT_WAY s3
 494 #define R_WRBC_RADDR    t5
 495 #define R_WRBC_SCRATCH0 t6
 496 #define R_WRBC_SCRATCH1 t7
 497 #define R_WRBC_SCRATCH2 s6
 498 #define R_WRBC_SCRATCH3 s7
 499
 500 #define R_PASS_FAIL     t4
 501
 502 /********************************************************
 503  *  l2test_wr_uac_allblocks                             *
 504  *      Write all blocks of the L2 using uncached       *
 505  *      accelerated writes in mgmt mode.                *
 506  *      This also marks all blocks as valid and dirty.  *
 507  *                                                      *
 508  ********************************************************/
 509
 510 #define R_BG_PAT0_0       a0
 511 #define R_BG_PAT0_1       a1
 512 #define R_BG_PAT0_2       a2
 513 #define R_BG_PAT0_3       a3
 514
 515 #define R_BG_PAT1_0       t0
 516 #define R_BG_PAT1_1       t1
 517 /*
 518 #define R_BG_PAT1_2       t2
 519 #define R_BG_PAT1_3       t3
 520 */
 521 #define R_INV_0           t2
 522 #define R_INV_1           t3
 523
 524 #define R_PATTERN_IND   s0
 525 #define R_BG_LINE       s2
 526 #define R_BG_NEXT_WAY   s3
 527 #define R_BG_BLOCK      s1
 528 #define R_BG_WADDR      t5
 529 #define R_BG_RADDR      t5
 530
 531 #define R_BG_SCRATCH0   t6
 532 #define R_BG_SCRATCH1   t7
 533 #define R_BG_SCRATCH2   t8
 534 #define R_BG_SCRATCH3   t9
 535 #define R_BG_SCRATCH4   s6
 536 #define R_BG_SCRATCH5   s7
 537
 538 #define R_ERR_TABLE_0   v0
 539 #define R_ERR_TABLE_1   v1
 540 #define R_ERR_TABLE_2   s4
 541 #define R_ERR_TABLE_3   s5
 542
 543 #define DATA_PATTERN0_0 0
 544 #define DATA_PATTERN0_1 0
 545 #define DATA_PATTERN0_2 0
 546 #define DATA_PATTERN0_3 0
 547 #define PATTERN0_INV0   0
 548 #define PATTERN0_INV1   0
 549
 550 #define DATA_PATTERN1_0 0xffffffffffffffff
 551 #define DATA_PATTERN1_1 0xffffffffffffffff
 552 #define DATA_PATTERN1_2 0xffffffffffffffff
 553 #define DATA_PATTERN1_3 0xffffffffffffffff
 554 #define PATTERN1_INV0   0xffffffffffffffff
 555 #define PATTERN1_INV1   0xffffffffffffffff
 556
 557 #define DATA_PATTERN2_0 0xffffffffffffffff
 558 #define DATA_PATTERN2_1 0xffffffffffffffff
 559 #define DATA_PATTERN2_2 0xffffffffffffffff
 560 #define DATA_PATTERN2_3 0xffffffffffffffff
 561 #define PATTERN2_INV0   0
 562 #define PATTERN2_INV1   0xffffffffffffffff
 563
 564 #define DATA_PATTERN3_0 0x5555555555555555
 565 #define DATA_PATTERN3_1 0x5555555555555555
 566 #define DATA_PATTERN3_2 0x5555555555555555
 567 #define DATA_PATTERN3_3 0x5555555555555555
 568 #define PATTERN3_INV0   0
 569 #define PATTERN3_INV1   0
 570
 571 #define DATA_PATTERN4_0 0x3333333333333333
 572 #define DATA_PATTERN4_1 0x3333333333333333
 573 #define DATA_PATTERN4_2 0x3333333333333333
 574 #define DATA_PATTERN4_3 0x3333333333333333
 575 #define PATTERN4_INV0   0
 576 #define PATTERN4_INV1   0
 577
 578 #define DATA_PATTERN5_0 0x0f0f0f0f0f0f0f0f
 579 #define DATA_PATTERN5_1 0x0f0f0f0f0f0f0f0f
 580 #define DATA_PATTERN5_2 0x0f0f0f0f0f0f0f0f
 581 #define DATA_PATTERN5_3 0x0f0f0f0f0f0f0f0f
 582 #define PATTERN5_INV0   0
 583 #define PATTERN5_INV1   0
 584
 585 #define DATA_PATTERN6_0 0x00ff00ff00ff00ff
 586 #define DATA_PATTERN6_1 0x00ff00ff00ff00ff
 587 #define DATA_PATTERN6_2 0x00ff00ff00ff00ff
 588 #define DATA_PATTERN6_3 0x00ff00ff00ff00ff
 589 #define PATTERN6_INV0   0
 590 #define PATTERN6_INV1   0
 591
 592 #define DATA_PATTERN7_0 0x0000ffff0000ffff
 593 #define DATA_PATTERN7_1 0x0000ffff0000ffff
 594 #define DATA_PATTERN7_2 0x0000ffff0000ffff
 595 #define DATA_PATTERN7_3 0x0000ffff0000ffff
 596 #define PATTERN7_INV0   0
 597 #define PATTERN7_INV1   0
 598
 599 #define DATA_PATTERN8_0 0x00000000ffffffff
 600 #define DATA_PATTERN8_1 0x00000000ffffffff
 601 #define DATA_PATTERN8_2 0x00000000ffffffff
 602 #define DATA_PATTERN8_3 0x00000000ffffffff
 603 #define PATTERN8_INV0   0
 604 #define PATTERN8_INV1   0
 605
 606 #define DATA_PATTERN9_0 0xffffffffffffffff
 607 #define DATA_PATTERN9_1 0x0000000000000000
 608 #define DATA_PATTERN9_2 0xffffffffffffffff
 609 #define DATA_PATTERN9_3 0x0000000000000000
 610 #define PATTERN9_INV0   0
 611 #define PATTERN9_INV1   0
 612
 613 #define DATA_PATTERNa_0 0xffffffffffffffff
 614 #define DATA_PATTERNa_1 0xffffffffffffffff
 615 #define DATA_PATTERNa_2 0x0000000000000000
 616 #define DATA_PATTERNa_3 0x0000000000000000
 617 #define PATTERNa_INV0   0
 618 #define PATTERNa_INV1   0
 619
 620 #undef MAX_PATTERN              /* avoid redef'n of diag_l1cache.h version */
 621 #define MAX_PATTERN     11
 622
 623 #define BG_WRITE_PAT(addr,pattern0,pattern1,pattern2,pattern3,inv0,inv1)                \
 624         li      R_BG_SCRATCH0, 2;       \
 625 1:      sd      pattern0, 0(addr);      \
 626         sd      pattern1, 8(addr);      \
 627         sd      pattern2, 16(addr);     \
 628         sd      pattern3, 24(addr); \
 629         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr); \
 630         xor     pattern0, pattern0, inv0; \
 631         xor     pattern1, pattern1, inv0; \
 632         xor     pattern2, pattern2, inv0; \
 633         xor     pattern3, pattern3, inv0; \
 634         daddu   addr, addr, R_BG_NEXT_WAY; \
 635         sd      pattern0, 0(addr);      \
 636         sd      pattern1, 8(addr);      \
 637         sd      pattern2, 16(addr);     \
 638         sd      pattern3, 24(addr); \
 639         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr); \
 640         xor     pattern0, pattern0, inv1; \
 641         xor     pattern1, pattern1, inv1; \
 642         xor     pattern2, pattern2, inv1; \
 643         xor     pattern3, pattern3, inv1; \
 644         addi    R_BG_SCRATCH0, R_BG_SCRATCH0, -1; \
 645         bne     R_BG_SCRATCH0, zero, 1b;   \
 646         daddu   addr, addr, R_BG_NEXT_WAY; \
 647         li      R_BG_SCRATCH0, -4*2*65536; \
 648         dadd    addr, addr, R_BG_SCRATCH0       /* next line */
 649
 650 #define BG_INVAL_L1(addr)               \
 651         move    R_BG_SCRATCH0, addr;    \
 652         cache   L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \
 653         daddu   R_BG_SCRATCH0, R_BG_SCRATCH0, R_BG_NEXT_WAY; \
 654         cache   L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \
 655         daddu   R_BG_SCRATCH0, R_BG_SCRATCH0, R_BG_NEXT_WAY; \
 656         cache   L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0); \
 657         daddu   R_BG_SCRATCH0, R_BG_SCRATCH0, R_BG_NEXT_WAY; \
 658         cache   L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(R_BG_SCRATCH0)
 659
 660 #define BG_CHECK_PAT(addr,pattern0,pattern1,pattern2,pattern3,inv0,inv1)                \
 661         li      R_BG_SCRATCH4, 2;       \
 662         dli     R_BG_SCRATCH5, L2M_READ_RAW_ACCESS; \
 663         or      addr, addr, R_BG_SCRATCH5; \
 664 1:      ld      R_BG_SCRATCH0, 0(addr); \
 665         ld      R_BG_SCRATCH1, 8(addr); \
 666         sne     R_BG_SCRATCH0, R_BG_SCRATCH0, pattern0;     \
 667         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH0; \
 668         ld      R_BG_SCRATCH2, 16(addr);\
 669         sne     R_BG_SCRATCH1, R_BG_SCRATCH1, pattern1;     \
 670         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH1; \
 671         ld      R_BG_SCRATCH3, 24(addr);\
 672         sne     R_BG_SCRATCH2, R_BG_SCRATCH2, pattern2;     \
 673         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH2; \
 674         sne     R_BG_SCRATCH3, R_BG_SCRATCH3, pattern3;     \
 675         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH3; \
 676         xor     pattern0, pattern0, inv0; \
 677         xor     pattern1, pattern1, inv0; \
 678         xor     pattern2, pattern2, inv0; \
 679         xor     pattern3, pattern3, inv0; \
 680         daddu   addr, addr, R_BG_NEXT_WAY; \
 681         ld      R_BG_SCRATCH0, 0(addr); \
 682         ld      R_BG_SCRATCH1, 8(addr); \
 683         sne     R_BG_SCRATCH0, R_BG_SCRATCH0, pattern0;     \
 684         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH0; \
 685         ld      R_BG_SCRATCH2, 16(addr);\
 686         sne     R_BG_SCRATCH1, R_BG_SCRATCH1, pattern1;     \
 687         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH1; \
 688         ld      R_BG_SCRATCH3, 24(addr);\
 689         sne     R_BG_SCRATCH2, R_BG_SCRATCH2, pattern2;     \
 690         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH2; \
 691         sne     R_BG_SCRATCH3, R_BG_SCRATCH3, pattern3;     \
 692         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH3; \
 693         xor     pattern0, pattern0, inv1; \
 694         xor     pattern1, pattern1, inv1; \
 695         xor     pattern2, pattern2, inv1; \
 696         xor     pattern3, pattern3, inv1; \
 697         addi    R_BG_SCRATCH4, R_BG_SCRATCH4, -1; \
 698         bne     R_BG_SCRATCH4, zero, 1b;   \
 699         daddu   addr, addr, R_BG_NEXT_WAY; \
 700         li      R_BG_SCRATCH0, -4*2*65536; \
 701         dadd    addr, addr, R_BG_SCRATCH0;      \
 702         nor     R_BG_SCRATCH5, R_BG_SCRATCH5, $0; \
 703         and     addr, addr, R_BG_SCRATCH5
 704
 705 #define BG_CHECK_PAT1(addr,pattern0,pattern1,pattern2,pattern3,inv0,inv1)               \
 706         li      R_BG_SCRATCH4, 2;       \
 707         dli     R_BG_SCRATCH5, 0x00200000; \
 708         or      addr, addr, R_BG_SCRATCH5; \
 709 1:      ld      R_BG_SCRATCH0, 0(addr); \
 710         cache   L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \
 711         ld      R_BG_SCRATCH0, 0(addr); \
 712         ld      R_BG_SCRATCH1, 8(addr); \
 713         sne     R_BG_SCRATCH0, R_BG_SCRATCH0, pattern0;     \
 714         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH0; \
 715         ld      R_BG_SCRATCH2, 16(addr);\
 716         sne     R_BG_SCRATCH1, R_BG_SCRATCH1, pattern1;     \
 717         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH1; \
 718         ld      R_BG_SCRATCH3, 24(addr);\
 719         sne     R_BG_SCRATCH2, R_BG_SCRATCH2, pattern2;     \
 720         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH2; \
 721         sne     R_BG_SCRATCH3, R_BG_SCRATCH3, pattern3;     \
 722         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH3; \
 723         xor     pattern0, pattern0, inv0; \
 724         xor     pattern1, pattern1, inv0; \
 725         xor     pattern2, pattern2, inv0; \
 726         xor     pattern3, pattern3, inv0; \
 727         daddu   addr, addr, R_BG_NEXT_WAY; \
 728         ld      R_BG_SCRATCH0, 0(addr); \
 729         cache   L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \
 730         ld      R_BG_SCRATCH0, 0(addr); \
 731         ld      R_BG_SCRATCH1, 8(addr); \
 732         sne     R_BG_SCRATCH0, R_BG_SCRATCH0, pattern0;     \
 733         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH0; \
 734         ld      R_BG_SCRATCH2, 16(addr);\
 735         sne     R_BG_SCRATCH1, R_BG_SCRATCH1, pattern1;     \
 736         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH1; \
 737         ld      R_BG_SCRATCH3, 24(addr);\
 738         sne     R_BG_SCRATCH2, R_BG_SCRATCH2, pattern2;     \
 739         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH2; \
 740         sne     R_BG_SCRATCH3, R_BG_SCRATCH3, pattern3;     \
 741         or      R_PASS_FAIL, R_PASS_FAIL, R_BG_SCRATCH3; \
 742         xor     pattern0, pattern0, inv1; \
 743         xor     pattern1, pattern1, inv1; \
 744         xor     pattern2, pattern2, inv1; \
 745         xor     pattern3, pattern3, inv1; \
 746         addi    R_BG_SCRATCH4, R_BG_SCRATCH4, -1; \
 747         bne     R_BG_SCRATCH4, zero, 1b;   \
 748         daddu   addr, addr, R_BG_NEXT_WAY; \
 749         li      R_BG_SCRATCH0, -4*2*65536; \
 750         dadd    addr, addr, R_BG_SCRATCH0;      \
 751         nor     R_BG_SCRATCH5, R_BG_SCRATCH5, $0; \
 752         and     addr, addr, R_BG_SCRATCH5
 753
 754 #define INV_PAT(pattern0, pattern1, pattern2, pattern3) \
 755         not     pattern0, pattern0; \
 756         not     pattern1, pattern1; \
 757         not     pattern2, pattern2; \
 758         not     pattern3, pattern3
 759
 760 #define SET_ERR_TABLE(pass_fail, line)  \
 761         li      R_BG_SCRATCH0, 0x3f;    \
 762         and     R_BG_SCRATCH0, R_BG_SCRATCH0, line;     \
 763         dsll    R_BG_SCRATCH0, pass_fail, R_BG_SCRATCH0;        \
 764         dsrl    R_BG_SCRATCH1, line, 6; \
 765         bne     R_BG_SCRATCH1, zero, 1f;        \
 766         li      R_BG_SCRATCH2, 1;       \
 767         or      R_ERR_TABLE_0, R_ERR_TABLE_0, R_BG_SCRATCH0;    \
 768         b       4f;     \
 769         nop;    \
 770 1:      bne     R_BG_SCRATCH1, R_BG_SCRATCH2, 2f;       \
 771         li      R_BG_SCRATCH2, 2;       \
 772         or      R_ERR_TABLE_1, R_ERR_TABLE_1, R_BG_SCRATCH0;    \
 773         b       4f;     \
 774         nop;    \
 775 2:      bne     R_BG_SCRATCH1, R_BG_SCRATCH2, 3f;       \
 776         li      R_BG_SCRATCH2, 3;       \
 777         or      R_ERR_TABLE_2, R_ERR_TABLE_2, R_BG_SCRATCH0;    \
 778         b       4f;     \
 779         nop;    \
 780 3:      or      R_ERR_TABLE_3, R_ERR_TABLE_3, R_BG_SCRATCH0;    \
 781 4:
 782
 783 #ifdef DATA_TEST
 784 LEAF(l2dtest_bg_rw_uac)
 785         /*li    R_BG_BLOCK, START_BLK */
 786         sll     R_BG_BLOCK, k0, 2
 787         li      R_BG_NEXT_WAY,0x20000
 788         move    R_ERR_TABLE_0, $0
 789         move    R_ERR_TABLE_1, $0
 790         move    R_ERR_TABLE_2, $0
 791         move    R_ERR_TABLE_3, $0
 792
 793
 794 bg_next_block:
 795         /* form address */
 796 #ifdef USE_LEDS
 797         addi    R_BG_SCRATCH2, R_BG_BLOCK, '0'
 798         or      R_BG_SCRATCH2, R_BG_SCRATCH2, ('D' << 8)
 799         SET_LEDS_HI(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1)
 800 #endif
 801
 802         move    R_PATTERN_IND, $0
 803
 804 bg_next_patt:
 805 #ifdef USE_LEDS
 806         addi    R_BG_SCRATCH2, R_PATTERN_IND, '0'
 807         or      R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8)
 808         SET_LEDS_LO(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1)
 809 #endif
 810
 811         bne     R_PATTERN_IND, $0, pattern_ne_0
 812         dli     R_BG_PAT0_0, DATA_PATTERN0_0     # data_pattern = pattern[0]
 813         dli     R_BG_PAT0_1, DATA_PATTERN0_1
 814         dli     R_BG_PAT0_2, DATA_PATTERN0_2
 815         dli     R_BG_PAT0_3, DATA_PATTERN0_3
 816         dli     R_INV_0, PATTERN0_INV0
 817         dli     R_INV_1, PATTERN0_INV1
 818         j       test_0
 819         nop
 820 pattern_ne_0:
 821         li      R_BG_SCRATCH0, 1
 822         bne     R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_1
 823         dli     R_BG_PAT0_0, DATA_PATTERN1_0     # data_pattern = pattern[0]
 824         dli     R_BG_PAT0_1, DATA_PATTERN1_1
 825         dli     R_BG_PAT0_2, DATA_PATTERN1_2
 826         dli     R_BG_PAT0_3, DATA_PATTERN1_3
 827         dli     R_INV_0, PATTERN1_INV0
 828         dli     R_INV_1, PATTERN1_INV1
 829         j       test_0
 830         nop
 831 pattern_ne_1:
 832         li      R_BG_SCRATCH0, 2
 833         bne     R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_2
 834         dli     R_BG_PAT0_0, DATA_PATTERN2_0     # data_pattern = pattern[0]
 835         dli     R_BG_PAT0_1, DATA_PATTERN2_1
 836         dli     R_BG_PAT0_2, DATA_PATTERN2_2
 837         dli     R_BG_PAT0_3, DATA_PATTERN2_3
 838         dli     R_INV_0, PATTERN2_INV0
 839         dli     R_INV_1, PATTERN2_INV1
 840         j       test_0
 841         nop
 842 pattern_ne_2:
 843         li      R_BG_SCRATCH0, 3
 844         bne     R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_3
 845         dli     R_BG_PAT0_0, DATA_PATTERN3_0     # data_pattern = pattern[0]
 846         dli     R_BG_PAT0_1, DATA_PATTERN3_1
 847         dli     R_BG_PAT0_2, DATA_PATTERN3_2
 848         dli     R_BG_PAT0_3, DATA_PATTERN3_3
 849         dli     R_INV_0, PATTERN3_INV0
 850         dli     R_INV_1, PATTERN3_INV1
 851         j       test_0
 852         nop
 853 pattern_ne_3:
 854         li      R_BG_SCRATCH0, 4
 855         bne     R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_4
 856         dli     R_BG_PAT0_0, DATA_PATTERN4_0     # data_pattern = pattern[0]
 857         dli     R_BG_PAT0_1, DATA_PATTERN4_1
 858         dli     R_BG_PAT0_2, DATA_PATTERN4_2
 859         dli     R_BG_PAT0_3, DATA_PATTERN4_3
 860         dli     R_INV_0, PATTERN4_INV0
 861         dli     R_INV_1, PATTERN4_INV1
 862         j       test_0
 863         nop
 864 pattern_ne_4:
 865         li      R_BG_SCRATCH0, 5
 866         bne     R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_5
 867         dli     R_BG_PAT0_0, DATA_PATTERN5_0     # data_pattern = pattern[0]
 868         dli     R_BG_PAT0_1, DATA_PATTERN5_1
 869         dli     R_BG_PAT0_2, DATA_PATTERN5_2
 870         dli     R_BG_PAT0_3, DATA_PATTERN5_3
 871         dli     R_INV_0, PATTERN5_INV0
 872         dli     R_INV_1, PATTERN5_INV1
 873         j       test_0
 874         nop
 875 pattern_ne_5:
 876         li      R_BG_SCRATCH0, 6
 877         bne     R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_6
 878         dli     R_BG_PAT0_0, DATA_PATTERN6_0     # data_pattern = pattern[0]
 879         dli     R_BG_PAT0_1, DATA_PATTERN6_1
 880         dli     R_BG_PAT0_2, DATA_PATTERN6_2
 881         dli     R_BG_PAT0_3, DATA_PATTERN6_3
 882         dli     R_INV_0, PATTERN6_INV0
 883         dli     R_INV_1, PATTERN6_INV1
 884         j       test_0
 885         nop
 886 pattern_ne_6:
 887         li      R_BG_SCRATCH0, 7
 888         bne     R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_7
 889         dli     R_BG_PAT0_0, DATA_PATTERN7_0     # data_pattern = pattern[0]
 890         dli     R_BG_PAT0_1, DATA_PATTERN7_1
 891         dli     R_BG_PAT0_2, DATA_PATTERN7_2
 892         dli     R_BG_PAT0_3, DATA_PATTERN7_3
 893         dli     R_INV_0, PATTERN7_INV0
 894         dli     R_INV_1, PATTERN7_INV1
 895         j       test_0
 896         nop
 897 pattern_ne_7:
 898         li      R_BG_SCRATCH0, 8
 899         bne     R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_8
 900         dli     R_BG_PAT0_0, DATA_PATTERN8_0     # data_pattern = pattern[0]
 901         dli     R_BG_PAT0_1, DATA_PATTERN8_1
 902         dli     R_BG_PAT0_2, DATA_PATTERN8_2
 903         dli     R_BG_PAT0_3, DATA_PATTERN8_3
 904         dli     R_INV_0, PATTERN8_INV0
 905         dli     R_INV_1, PATTERN8_INV1
 906         j       test_0
 907         nop
 908 pattern_ne_8:
 909         li      R_BG_SCRATCH0, 9
 910         bne     R_PATTERN_IND, R_BG_SCRATCH0, pattern_ne_9
 911         dli     R_BG_PAT0_0, DATA_PATTERN9_0     # data_pattern = pattern[0]
 912         dli     R_BG_PAT0_1, DATA_PATTERN9_1
 913         dli     R_BG_PAT0_2, DATA_PATTERN9_2
 914         dli     R_BG_PAT0_3, DATA_PATTERN9_3
 915         dli     R_INV_0, PATTERN9_INV0
 916         dli     R_INV_1, PATTERN9_INV1
 917         j       test_0
 918         nop
 919 pattern_ne_9:
 920         dli     R_BG_PAT0_0, DATA_PATTERNa_0     # data_pattern = pattern[0]
 921         dli     R_BG_PAT0_1, DATA_PATTERNa_1
 922         dli     R_BG_PAT0_2, DATA_PATTERNa_2
 923         dli     R_BG_PAT0_3, DATA_PATTERNa_3
 924         dli     R_INV_0, PATTERNa_INV0
 925         dli     R_INV_1, PATTERNa_INV1
 926         j       test_0
 927         nop
 928
 929 test_0:
 930         dli     R_BG_WADDR, XKPHYS_C_COH_EXC    /* uncached accelerated */
 931         dli     R_BG_SCRATCH0, L2_RAM_BASE_ADDR /* mgmt mode */
 932         or      R_BG_WADDR,R_BG_WADDR,R_BG_SCRATCH0
 933         sll     R_BG_SCRATCH0, R_BG_BLOCK, L2_BLOCK_SHIFT /* block number */
 934         or      R_BG_WADDR, R_BG_WADDR, R_BG_SCRATCH0
 935
 936         .set    noreorder
 937         move    R_BG_LINE, zero
 938 bg_init_next_line:
 939         /*BG_WRITE_PAT0(R_BG_WADDR) */
 940         BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
 941 /*   for (line = 0;  line < max_lines_per_block; line++)  */
 942         .set    noreorder
 943         li      R_BG_SCRATCH0, (32)
 944         dadd    R_BG_WADDR, R_BG_WADDR, R_BG_SCRATCH0   /* next line */
 945         slt     R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1
 946         bne     R_BG_SCRATCH0,$0, bg_init_next_line
 947         add     R_BG_LINE,R_BG_LINE,1
 948
 949
 950 /* march element 1 */
 951         dli     R_WRBC_RADDR, XKPHYS_C_COH_EXC
 952         dli     R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR
 953         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0
 954         /* form address for block to be read/written */
 955         sll     R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT
 956         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1
 957         li      R_WRBC_NEXT_WAY, 0x20000
 958
 959         /* way = 0; */
 960         /* for (line = 0;  line < lines_per_block; line++) {*/
 961         move    R_BG_LINE, zero
 962 march1_w0:
 963         move    R_PASS_FAIL, zero
 964         BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
 965         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
 966         BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
 967         BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
 968         BG_INVAL_L1(R_BG_WADDR)
 969         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
 970         SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE)
 971         daddiu  R_WRBC_RADDR, R_WRBC_RADDR, 0x20
 972
 973         slt     R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1
 974         bne     R_BG_SCRATCH0,$0,march1_w0
 975         add     R_BG_LINE,R_BG_LINE,1
 976
 977 /* march element 2 */
 978         dli     R_WRBC_RADDR, XKPHYS_C_COH_EXC
 979         dli     R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR
 980         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0
 981         /* form address for block to be read/written */
 982         sll     R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT
 983         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1
 984         li      R_WRBC_NEXT_WAY, 0x20000
 985         /* way = 0; */
 986         /* for (line = 0;  line < lines_per_block; line++) {*/
 987         move    R_BG_LINE,zero
 988 march2_w0:
 989         move    R_PASS_FAIL, zero
 990         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
 991         BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
 992         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
 993         BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
 994         BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
 995         BG_INVAL_L1(R_BG_WADDR)
 996         SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE)
 997         daddiu  R_WRBC_RADDR, R_WRBC_RADDR, 0x20
 998
 999         slt     R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1
1000         bne     R_BG_SCRATCH0,$0,march2_w0
1001         add     R_BG_LINE,R_BG_LINE,1
1002
1003 /* march element 3 */
1004         dli     R_WRBC_RADDR, XKPHYS_C_COH_EXC
1005         dli     R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR
1006         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0
1007         /* form address for block to be read/written */
1008         addi    R_WRBC_SCRATCH0, R_WRBC_RBLK, 1
1009 #ifdef TEST_ALL_LINES
1010         sll     R_WRBC_SCRATCH1, R_WRBC_SCRATCH0, L2_BLOCK_SHIFT
1011 #else
1012         sll     R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT
1013 #endif
1014         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1
1015 #ifdef TEST_ALL_LINES
1016         daddiu  R_WRBC_RADDR, R_WRBC_RADDR, -32
1017 #else
1018         daddiu  R_WRBC_RADDR, R_WRBC_RADDR, L2_LINES_PER_BLOCK*32-32
1019 #endif
1020         li      R_WRBC_NEXT_WAY, 0x20000
1021         /* way = 0; */
1022         /* for (line = 0;  line < lines_per_block; line++) {*/
1023         li      R_WRBC_LINE,L2_LINES_PER_BLOCK-1
1024 march3_w0:
1025         move    R_PASS_FAIL, zero
1026         BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
1027         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
1028         BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
1029         BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
1030         BG_INVAL_L1(R_BG_WADDR)
1031         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
1032         SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE)
1033         daddiu  R_WRBC_RADDR, R_WRBC_RADDR, -32
1034
1035         bne     R_WRBC_LINE,$0, march3_w0
1036         add     R_WRBC_LINE,R_WRBC_LINE,-1
1037
1038 /* march element 4 */
1039         dli     R_WRBC_RADDR, XKPHYS_C_COH_EXC
1040         dli     R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR
1041         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0
1042         /* form address for block to be read/written */
1043         addi    R_WRBC_SCRATCH0, R_WRBC_RBLK, 1
1044 #ifdef TEST_ALL_LINES
1045         sll     R_WRBC_SCRATCH1, R_WRBC_SCRATCH0, L2_BLOCK_SHIFT
1046 #else
1047         sll     R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT
1048 #endif
1049         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1
1050 #ifdef TEST_ALL_LINES
1051         daddiu  R_WRBC_RADDR, R_WRBC_RADDR, -32
1052 #else
1053         daddiu  R_WRBC_RADDR, R_WRBC_RADDR, L2_LINES_PER_BLOCK*32-32
1054 #endif
1055         li      R_WRBC_NEXT_WAY, 0x20000
1056         /* way = 0; */
1057         /* for (line = 0;  line < lines_per_block; line++) {*/
1058         li      R_WRBC_LINE,L2_LINES_PER_BLOCK-1
1059 march4_w0:
1060         move    R_PASS_FAIL, zero
1061         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
1062         BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
1063         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
1064         BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
1065         BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
1066         BG_INVAL_L1(R_BG_WADDR)
1067         SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE)
1068         daddiu  R_WRBC_RADDR, R_WRBC_RADDR, -32
1069
1070         bne     R_WRBC_LINE,$0, march4_w0
1071         add     R_WRBC_LINE,R_WRBC_LINE,-1
1072
1073 /*
1074         bne     R_BG_PAT0_0, $0, 0f
1075         nop
1076         dli     R_BG_PAT0_0, 0x5555555555555555
1077         move    R_BG_PAT0_1, R_BG_PAT0_0
1078         move    R_BG_PAT0_2, R_BG_PAT0_0
1079         move    R_BG_PAT0_3, R_BG_PAT0_0
1080         b       bg_next_patt
1081         nop
1082 0:
1083         beq     R_BG_PAT0_2, $0, 3f
1084         nop
1085         bne     R_BG_PAT0_3, $0, 4f
1086         nop
1087         move    R_BG_PAT0_1, R_BG_PAT0_0
1088         move    R_BG_PAT0_2, R_BG_PAT0_3
1089         b       bg_next_patt
1090 4:
1091         dli     R_BG_SCRATCH2, 0
1092         move    R_BG_SCRATCH0, R_BG_PAT0_0
1093 1:
1094         dsrl    R_BG_SCRATCH0, R_BG_SCRATCH0, 1
1095         and     R_BG_SCRATCH1, R_BG_SCRATCH0, 1
1096         addi    R_BG_SCRATCH2, R_BG_SCRATCH2, 1
1097         bne     R_BG_SCRATCH1, $0, 1b
1098         nop
1099
1100         dsll    R_BG_SCRATCH2, R_BG_SCRATCH2, 1
1101         bne     R_BG_SCRATCH2, 0x40, 6f
1102         dli     R_BG_PAT0_0, -1
1103         move    R_BG_PAT0_1, $0
1104         move    R_BG_PAT0_2, R_BG_PAT0_0
1105         move    R_BG_PAT0_3, $0
1106         b       bg_next_patt
1107 6:
1108         dli     R_BG_SCRATCH3, 1
1109         dsll    R_BG_SCRATCH3, R_BG_SCRATCH3, R_BG_SCRATCH2
1110         daddiu  R_BG_SCRATCH3, R_BG_SCRATCH3, -1
1111
1112         dsll    R_BG_SCRATCH2, R_BG_SCRATCH2, 1
1113         move    R_BG_PAT0_0, R_BG_SCRATCH3
1114         beq     R_BG_SCRATCH2, 0x40, 5f
1115 2:
1116         dsll    R_BG_SCRATCH3, R_BG_SCRATCH3, R_BG_SCRATCH2
1117         or      R_BG_PAT0_0, R_BG_PAT0_0, R_BG_SCRATCH3
1118         bne     R_BG_SCRATCH3, $0, 2b
1119         nop
1120
1121 5:
1122         move    R_BG_PAT0_1, R_BG_PAT0_0
1123         move    R_BG_PAT0_2, R_BG_PAT0_0
1124         move    R_BG_PAT0_3, R_BG_PAT0_0
1125         b       bg_next_patt
1126         nop
1127
1128 3:
1129 */
1130         addu    R_PATTERN_IND, R_PATTERN_IND, 1
1131         slt     R_BG_SCRATCH0, R_PATTERN_IND, MAX_PATTERN
1132         bne     R_BG_SCRATCH0, $0, bg_next_patt
1133
1134         li      R_BG_SCRATCH0, 2
1135 1:
1136         dli     R_BG_SCRATCH1, 2
1137 2:
1138         daddiu  R_BG_SCRATCH1, R_BG_SCRATCH1, -1
1139         bne     R_BG_SCRATCH1, $0, 2b
1140         nop
1141         daddiu  R_BG_SCRATCH0, R_BG_SCRATCH0, -1
1142         bne     R_BG_SCRATCH0, $0, 1b
1143         nop
1144
1145 /* march element 5 */
1146         dli     R_WRBC_RADDR, XKPHYS_C_COH_EXC
1147         dli     R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR
1148         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0
1149         /* form address for block to be read/written */
1150         sll     R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT
1151         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1
1152         li      R_WRBC_NEXT_WAY, 0x20000
1153         move    R_WRBC_LINE,zero
1154 march5_w0:
1155         move    R_PASS_FAIL, zero
1156         BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
1157         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
1158         BG_WRITE_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
1159         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
1160         SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE)
1161         daddiu  R_WRBC_RADDR, R_WRBC_RADDR, 32
1162
1163         slt     R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1
1164         bne     R_BG_SCRATCH0,$0,march5_w0
1165         add     R_BG_LINE,R_BG_LINE,1
1166
1167         li      R_BG_SCRATCH0, 2
1168 1:
1169         dli     R_BG_SCRATCH1, 2
1170 2:
1171         daddiu  R_BG_SCRATCH1, R_BG_SCRATCH1, -1
1172         bne     R_BG_SCRATCH1, $0, 2b
1173         nop
1174         daddiu  R_BG_SCRATCH0, R_BG_SCRATCH0, -1
1175         bne     R_BG_SCRATCH0, $0, 1b
1176         nop
1177
1178 /* march element 6 */
1179         dli     R_WRBC_RADDR, XKPHYS_C_COH_EXC
1180         dli     R_WRBC_SCRATCH0, L2_RAM_BASE_ADDR
1181         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH0
1182         /* form address for block to be read/written */
1183         sll     R_WRBC_SCRATCH1, R_WRBC_RBLK, L2_BLOCK_SHIFT
1184         or      R_WRBC_RADDR, R_WRBC_RADDR, R_WRBC_SCRATCH1
1185         li      R_WRBC_NEXT_WAY, 0x20000
1186         move    R_WRBC_LINE,zero
1187 march6_w0:
1188         move    R_PASS_FAIL, zero
1189         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
1190         BG_CHECK_PAT(R_BG_WADDR,R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3,R_INV_0,R_INV_1)
1191         INV_PAT(R_BG_PAT0_0,R_BG_PAT0_1,R_BG_PAT0_2,R_BG_PAT0_3)
1192         SET_ERR_TABLE(R_PASS_FAIL, R_WRBC_LINE)
1193         daddiu  R_WRBC_RADDR, R_WRBC_RADDR, 32
1194
1195         slt     R_BG_SCRATCH0,R_BG_LINE,L2_LINES_PER_BLOCK-1
1196         bne     R_BG_SCRATCH0,$0,march6_w0
1197         add     R_BG_LINE,R_BG_LINE,1
1198
1199         /* if error, put test block info into s0 and return */
1200         or      R_BG_SCRATCH0, R_ERR_TABLE_0, R_ERR_TABLE_1
1201         or      R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_2
1202         or      R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_3
1203         beq     R_BG_SCRATCH0, zero, 1f
1204         nop
1205         move    s0, R_BG_BLOCK
1206         or      s0, s0, 1 << 8
1207         jr      ra
1208         nop
1209 1:
1210
1211         addu    R_BG_BLOCK,R_BG_BLOCK,1
1212         /*slt   R_BG_SCRATCH0, R_BG_BLOCK, (L2_BLOCKS_PER_ROW * L2_BLOCK_ROWS)*/
1213         addi    R_BG_SCRATCH1, k0, 1
1214         sll     R_BG_SCRATCH1, R_BG_SCRATCH1, 2
1215         /*slt   R_BG_SCRATCH0, R_BG_BLOCK, (START_BLK + TOTAL_BLKS)*/
1216         slt     R_BG_SCRATCH0, R_BG_BLOCK, R_BG_SCRATCH1
1217         bne     R_BG_SCRATCH0,$0, bg_next_block
1218         nop
1219
1220         .set    noreorder
1221         jr      ra
1222         nop
1223
1224 bg_err:
1225         li      v0, 1
1226         jr      ra
1227         nop
1228
1229 END(l2dtest_bg_rw_uac)
1230 #endif
1231
1232
1233 #define SCD_BW_BASE        0x0010020880
1234 #define L2_BASE            0x0010040000
1235 #define L2_READ_TAG        0x18
1236 #define L2_ECC_TAG         0x38
1237 #define BUS_ERR_STATUS     0x00
1238 #define BUS_L2_ERRORS      0x40
1239
1240 #define R_ECC_PAT0_0       a0
1241 #define R_ECC_PAT0_1       a1
1242 #define R_ECC_PAT0_2       a2
1243 #define R_ECC_PAT0_3       a3
1244
1245 #define R_ECC_PAT1_0       t0
1246 #define R_ECC_PAT1_1       t1
1247 #define R_ECC_PAT1_2       t2
1248 #define R_ECC_PAT1_3       t3
1249
1250 #define R_ECC_PATT_IND   s0
1251 #define R_ECC_LINE       s2
1252 #define R_ECC_NEXT_WAY   s3
1253 #define R_ECC_BLOCK      s1
1254 #define R_ECC_WADDR      t5
1255 #define R_ECC_RADDR      t5
1256
1257 #define R_ECC_SCRATCH0   t6
1258 #define R_ECC_SCRATCH1   t7
1259 #define R_ECC_SCRATCH2   t8
1260 #define R_ECC_SCRATCH3   t9
1261 #define R_ECC_SCRATCH4   s6
1262 #define R_ECC_SCRATCH5   s7
1263
1264 /*
1265 #define DATA_FOR_ECC_PATT0 0x0000
1266 #define DATA_FOR_ECC_PATT1 0x0020
1267 #define DATA_FOR_ECC_PATT2 0x1032
1268 #define DATA_FOR_ECC_PATT3 0x0017
1269 #define DATA_FOR_ECC_PATT4 0x1822
1270
1271 #define DATA_FOR_ECC_INVPATT0 0x0036
1272 #define DATA_FOR_ECC_INVPATT1 0x0016
1273 #define DATA_FOR_ECC_INVPATT2 0x1004
1274 #define DATA_FOR_ECC_INVPATT3 0x0021
1275 #define DATA_FOR_ECC_INVPATT4 0x1814
1276 */
1277 #define       DATA_FOR_ECC_PATT0 0x0000
1278 #define       DATA_FOR_ECC_PATT1 0x00ba
1279 #define       DATA_FOR_ECC_PATT2 0x0438
1280 #define       DATA_FOR_ECC_PATT3 0x05be
1281 #define       DATA_FOR_ECC_PATT4 0x0099
1282
1283 #define       DATA_FOR_ECC_INVPATT0 0x059c
1284 #define       DATA_FOR_ECC_INVPATT1 0x0526
1285 #define       DATA_FOR_ECC_INVPATT2 0x01a4
1286 #define       DATA_FOR_ECC_INVPATT3 0x0022
1287 #define       DATA_FOR_ECC_INVPATT4 0x0505
1288
1289 #define ECC_WRITE_PAT(addr, pattern0, pattern1, pattern2, pattern3)\
1290         dli     R_ECC_SCRATCH2, 4; \
1291         /*dli   R_ECC_SCRATCH0, 0x00400000;*/ \
1292         /*nor   R_ECC_SCRATCH1, R_ECC_SCRATCH0, $0;*/ \
1293 1:      sd      pattern0, 0(addr); \
1294         sd      zero, 8(addr); \
1295         sd      zero, 16(addr); \
1296         sd      zero, 24(addr); \
1297         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr); \
1298         /*or    addr, R_ECC_SCRATCH0, addr;*/ \
1299         /*sd    pattern0, 0(addr);*/ \
1300         /*sd    zero, 8(addr);*/ \
1301         /*sd    zero, 16(addr);*/ \
1302         /*sd    zero, 24(addr);*/ \
1303         /*cache L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(addr);*/ \
1304         /*and   addr, addr, R_ECC_SCRATCH1;*/ \
1305         move    R_ECC_SCRATCH3, pattern0;       \
1306         move    pattern0, pattern1;     \
1307         move    pattern1, pattern2;     \
1308         move    pattern2, pattern3;     \
1309         move    pattern3, R_ECC_SCRATCH3;       \
1310         addi    R_ECC_SCRATCH2, R_ECC_SCRATCH2, -1; \
1311         bne     R_ECC_SCRATCH2, zero, 1b;   \
1312         daddu   addr, addr, R_BG_NEXT_WAY; \
1313         li      R_ECC_SCRATCH0, -4*2*65536; \
1314         dadd    addr, addr, R_ECC_SCRATCH0
1315
1316 #define ECC_CHECK_PAT(addr,pattern0,pattern1,pattern2,pattern3,fail)            \
1317         dli     R_ECC_SCRATCH4, XKPHYS_UNC; \
1318         dli     R_ECC_SCRATCH5, SCD_BW_BASE; \
1319         or      R_ECC_SCRATCH4, R_ECC_SCRATCH4, R_ECC_SCRATCH5; \
1320         li      R_ECC_SCRATCH5, 4;      \
1321         sd      zero, BUS_L2_ERRORS(R_ECC_SCRATCH4); \
1322         sync;   \
1323 1:      ld      R_ECC_SCRATCH0, 0(addr);        \
1324         ld      R_ECC_SCRATCH1, 8(addr);        \
1325         sne     R_ECC_SCRATCH0, R_ECC_SCRATCH0, pattern0;     \
1326         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \
1327         ld      R_ECC_SCRATCH2, 16(addr);\
1328         sne     R_ECC_SCRATCH1, R_ECC_SCRATCH1, zero;     \
1329         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH1; \
1330         ld      R_ECC_SCRATCH3, 24(addr);\
1331         sne     R_ECC_SCRATCH2, R_ECC_SCRATCH2, zero;     \
1332         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH2; \
1333         ld      R_ECC_SCRATCH0, BUS_L2_ERRORS(R_ECC_SCRATCH4); \
1334         sne     R_ECC_SCRATCH3, R_ECC_SCRATCH3, zero;     \
1335         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH3; \
1336         li      R_ECC_SCRATCH2, 0xffff; \
1337         and     R_ECC_SCRATCH0, R_ECC_SCRATCH2, R_ECC_SCRATCH0; \
1338         sne     R_ECC_SCRATCH0, R_ECC_SCRATCH0, zero;     \
1339         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \
1340         move    R_ECC_SCRATCH3, pattern0;       \
1341         move    pattern0, pattern1;     \
1342         move    pattern1, pattern2;     \
1343         move    pattern2, pattern3;     \
1344         move    pattern3, R_ECC_SCRATCH3;       \
1345         addi    R_BG_SCRATCH5, R_BG_SCRATCH5, -1; \
1346         bne     R_BG_SCRATCH5, zero, 1b;   \
1347         daddu   addr, addr, R_ECC_NEXT_WAY; \
1348         li      R_ECC_SCRATCH0, -4*2*65536; \
1349         dadd    addr, addr, R_ECC_SCRATCH0
1350
1351 #define ECC_CHECK_PAT1(addr,pattern0,pattern1,pattern2,pattern3,fail)           \
1352         dli     R_ECC_SCRATCH4, XKPHYS_UNC; \
1353         dli     R_ECC_SCRATCH5, SCD_BW_BASE; \
1354         or      R_ECC_SCRATCH4, R_ECC_SCRATCH4, R_ECC_SCRATCH5; \
1355         li      R_ECC_SCRATCH5, 4;      \
1356 1:      sd      zero, BUS_L2_ERRORS(R_ECC_SCRATCH4); \
1357         ld      R_ECC_SCRATCH0, 0(addr);        \
1358         cache   L1CACHEOP(L1C_D,L1C_OP_HITINVAL),0(addr); \
1359         ld      R_ECC_SCRATCH0, 0(addr);        \
1360         ld      R_ECC_SCRATCH1, 8(addr);        \
1361         sne     R_ECC_SCRATCH0, R_ECC_SCRATCH0, pattern0;     \
1362         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \
1363         ld      R_ECC_SCRATCH2, 16(addr);\
1364         sne     R_ECC_SCRATCH1, R_ECC_SCRATCH1, zero;     \
1365         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH1; \
1366         ld      R_ECC_SCRATCH3, 24(addr);\
1367         sne     R_ECC_SCRATCH2, R_ECC_SCRATCH2, zero;     \
1368         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH2; \
1369         ld      R_ECC_SCRATCH0, BUS_L2_ERRORS(R_ECC_SCRATCH4); \
1370         sne     R_ECC_SCRATCH3, R_ECC_SCRATCH3, zero;     \
1371         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH3; \
1372         sne     R_ECC_SCRATCH0, R_ECC_SCRATCH0, zero;     \
1373         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH0; \
1374         move    R_ECC_SCRATCH3, pattern0;       \
1375         move    pattern0, pattern1;     \
1376         move    pattern1, pattern2;     \
1377         move    pattern2, pattern3;     \
1378         move    pattern3, R_ECC_SCRATCH3;       \
1379         addi    R_BG_SCRATCH5, R_BG_SCRATCH5, -1; \
1380         bne     R_BG_SCRATCH5, zero, 1b;   \
1381         daddu   addr, addr, R_ECC_NEXT_WAY; \
1382         li      R_ECC_SCRATCH0, -4*2*65536; \
1383         dadd    addr, addr, R_ECC_SCRATCH0
1384
1385 #ifdef DATA_TEST
1386 #ifdef DATA_ECC_TEST
1387 LEAF(l2dtest_data_ecc)
1388
1389         /*li    R_ECC_BLOCK, START_BLK*/
1390         sll     R_ECC_BLOCK, k0, 2
1391         li      R_ECC_NEXT_WAY,0x20000
1392 ecc_next_block:
1393 #ifdef USE_LEDS
1394         addi    R_BG_SCRATCH2, R_BG_BLOCK, '0'
1395         or      R_BG_SCRATCH2, R_BG_SCRATCH2, ('E' << 8)
1396         SET_LEDS_HI(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1)
1397 #endif
1398
1399         move    R_ECC_PATT_IND, $0
1400         dli     R_ECC_PAT0_0, DATA_FOR_ECC_PATT0
1401         dli     R_ECC_PAT0_1, DATA_FOR_ECC_PATT0
1402         dli     R_ECC_PAT0_2, DATA_FOR_ECC_PATT0
1403         dli     R_ECC_PAT0_3, DATA_FOR_ECC_PATT0
1404         dli     R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT0
1405         dli     R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT0
1406         dli     R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT0
1407         dli     R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT0
1408
1409 ecc_next_pattern:
1410 #ifdef USE_LEDS
1411         addi    R_BG_SCRATCH2, R_ECC_PATT_IND, '0'
1412         or      R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8)
1413         SET_LEDS_LO(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1)
1414 #endif
1415
1416         dli     R_ECC_WADDR, XKPHYS_C_COH_EXC   /* uncached accelerated */
1417         dli     R_ECC_SCRATCH0, L2_RAM_BASE_ADDR        /* mgmt mode */
1418         or      R_ECC_WADDR,R_ECC_WADDR,R_BG_SCRATCH0
1419         sll     R_ECC_SCRATCH0, R_ECC_BLOCK, L2_BLOCK_SHIFT /* block number */
1420         or      R_ECC_WADDR, R_ECC_WADDR, R_ECC_SCRATCH0
1421
1422
1423         .set    noreorder
1424         move    R_ECC_LINE, zero
1425 ecc_init_next_line:
1426         ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3)
1427         li      R_ECC_SCRATCH0, (32)
1428         dadd    R_ECC_WADDR, R_ECC_WADDR, R_ECC_SCRATCH0        /* next line */
1429
1430         slt     R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1
1431         bne     R_ECC_SCRATCH0, $0, ecc_init_next_line
1432         add     R_ECC_LINE, R_ECC_LINE,1
1433
1434         dli     R_ECC_RADDR, XKPHYS_C_COH_EXC
1435         dli     R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
1436         or      R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0
1437         sll     R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
1438         or      R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
1439         li      R_ECC_NEXT_WAY, 0x20000
1440
1441         move    R_ECC_LINE, zero
1442 ecc_march1:
1443         move    R_PASS_FAIL, zero
1444         ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err)
1445         ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3)
1446         ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err)
1447         BG_INVAL_L1(R_BG_WADDR)
1448         SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
1449         daddiu  R_ECC_RADDR, R_ECC_RADDR, 0x20
1450
1451         slt     R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1
1452         bne     R_ECC_SCRATCH0, $0, ecc_march1
1453         add     R_ECC_LINE, R_ECC_LINE,1
1454
1455         dli     R_ECC_RADDR, XKPHYS_C_COH_EXC
1456         dli     R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
1457         or      R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0
1458         sll     R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
1459         or      R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
1460         li      R_ECC_NEXT_WAY, 0x20000
1461
1462         move    R_ECC_LINE, zero
1463 ecc_march2:
1464         move    R_PASS_FAIL, zero
1465         ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err)
1466         ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3)
1467         ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err)
1468         BG_INVAL_L1(R_BG_WADDR)
1469         SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
1470         daddiu  R_ECC_RADDR, R_ECC_RADDR, 0x20
1471
1472         slt     R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1
1473         bne     R_ECC_SCRATCH0, $0, ecc_march2
1474         add     R_ECC_LINE, R_ECC_LINE,1
1475
1476         dli     R_ECC_RADDR, XKPHYS_C_COH_EXC
1477         dli     R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
1478         or      R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH0
1479         addi    R_ECC_SCRATCH0, R_ECC_BLOCK, 1
1480 #ifdef TEST_ALL_LINES
1481         sll     R_ECC_SCRATCH1, R_ECC_SCRATCH0, L2_BLOCK_SHIFT
1482 #else
1483         sll     R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
1484 #endif
1485         or      R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
1486 #ifdef TEST_ALL_LINES
1487         daddiu  R_ECC_RADDR, R_ECC_RADDR, -32
1488 #else
1489         daddiu  R_ECC_RADDR, R_ECC_RADDR, L2_LINES_PER_BLOCK*32-32
1490 #endif
1491         li      R_ECC_LINE,L2_LINES_PER_BLOCK-1
1492 ecc_march3:
1493         move    R_PASS_FAIL, zero
1494         ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err)
1495         ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3)
1496         ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err)
1497         BG_INVAL_L1(R_BG_WADDR)
1498         SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
1499         daddiu  R_ECC_RADDR, R_ECC_RADDR, -32
1500
1501         bne     R_ECC_LINE,$0, ecc_march3
1502         add     R_ECC_LINE,R_ECC_LINE,-1
1503
1504         dli     R_ECC_RADDR, XKPHYS_C_COH_EXC
1505         dli     R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
1506         or      R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH0
1507         addi    R_ECC_SCRATCH0, R_ECC_BLOCK, 1
1508 #ifdef TEST_ALL_LINES
1509         sll     R_ECC_SCRATCH1, R_ECC_SCRATCH0, L2_BLOCK_SHIFT
1510 #else
1511         sll     R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
1512 #endif
1513         or      R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
1514 #ifdef TEST_ALL_LINES
1515         daddiu  R_ECC_RADDR, R_ECC_RADDR, -32
1516 #else
1517         daddiu  R_ECC_RADDR, R_ECC_RADDR, L2_LINES_PER_BLOCK*32-32
1518 #endif
1519         li      R_ECC_LINE,L2_LINES_PER_BLOCK-1
1520 ecc_march4:
1521         move    R_PASS_FAIL, zero
1522         ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err)
1523         ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3)
1524         ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err)
1525         BG_INVAL_L1(R_BG_WADDR)
1526         SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
1527         daddiu  R_ECC_RADDR, R_ECC_RADDR, -32
1528
1529         bne     R_ECC_LINE,$0, ecc_march4
1530         add     R_ECC_LINE,R_ECC_LINE,-1
1531
1532         addi    R_ECC_PATT_IND, R_ECC_PATT_IND, 1
1533         li      R_ECC_SCRATCH0, 1
1534         bne     R_ECC_SCRATCH0, R_ECC_PATT_IND, 2f
1535         nop
1536         dli     R_ECC_PAT0_0, DATA_FOR_ECC_INVPATT0
1537         dli     R_ECC_PAT0_1, DATA_FOR_ECC_PATT0
1538         dli     R_ECC_PAT0_2, DATA_FOR_ECC_INVPATT0
1539         dli     R_ECC_PAT0_3, DATA_FOR_ECC_PATT0
1540         dli     R_ECC_PAT1_0, DATA_FOR_ECC_PATT0
1541         dli     R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT0
1542         dli     R_ECC_PAT1_2, DATA_FOR_ECC_PATT0
1543         dli     R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT0
1544         b       ecc_next_pattern
1545 2:
1546         li      R_ECC_SCRATCH0, 2
1547         bne     R_ECC_SCRATCH0, R_ECC_PATT_IND, 3f
1548         nop
1549         dli     R_ECC_PAT0_0, DATA_FOR_ECC_INVPATT0
1550         dli     R_ECC_PAT0_1, DATA_FOR_ECC_INVPATT0
1551         dli     R_ECC_PAT0_2, DATA_FOR_ECC_PATT0
1552         dli     R_ECC_PAT0_3, DATA_FOR_ECC_PATT0
1553         dli     R_ECC_PAT1_0, DATA_FOR_ECC_PATT0
1554         dli     R_ECC_PAT1_1, DATA_FOR_ECC_PATT0
1555         dli     R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT0
1556         dli     R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT0
1557         b       ecc_next_pattern
1558         nop
1559 3:
1560         li      R_ECC_SCRATCH0, 3
1561         bne     R_ECC_SCRATCH0, R_ECC_PATT_IND, 4f
1562         nop
1563         dli     R_ECC_PAT0_0, DATA_FOR_ECC_PATT1
1564         dli     R_ECC_PAT0_1, DATA_FOR_ECC_PATT1
1565         dli     R_ECC_PAT0_2, DATA_FOR_ECC_PATT1
1566         dli     R_ECC_PAT0_3, DATA_FOR_ECC_PATT1
1567         dli     R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT1
1568         dli     R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT1
1569         dli     R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT1
1570         dli     R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT1
1571         b       ecc_next_pattern
1572         nop
1573 4:
1574         li      R_ECC_SCRATCH0, 4
1575         bne     R_ECC_SCRATCH0, R_ECC_PATT_IND, 5f
1576         nop
1577         dli     R_ECC_PAT0_0, DATA_FOR_ECC_PATT2
1578         dli     R_ECC_PAT0_1, DATA_FOR_ECC_PATT2
1579         dli     R_ECC_PAT0_2, DATA_FOR_ECC_PATT2
1580         dli     R_ECC_PAT0_3, DATA_FOR_ECC_PATT2
1581         dli     R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT2
1582         dli     R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT2
1583         dli     R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT2
1584         dli     R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT2
1585         b       ecc_next_pattern
1586         nop
1587 5:
1588         li      R_ECC_SCRATCH0, 5
1589         bne     R_ECC_SCRATCH0, R_ECC_PATT_IND, 6f
1590         nop
1591         dli     R_ECC_PAT0_0, DATA_FOR_ECC_PATT3
1592         dli     R_ECC_PAT0_1, DATA_FOR_ECC_PATT3
1593         dli     R_ECC_PAT0_2, DATA_FOR_ECC_PATT3
1594         dli     R_ECC_PAT0_3, DATA_FOR_ECC_PATT3
1595         dli     R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT3
1596         dli     R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT3
1597         dli     R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT3
1598         dli     R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT3
1599         b       ecc_next_pattern
1600         nop
1601 6:
1602         li      R_ECC_SCRATCH0, 6
1603         bne     R_ECC_SCRATCH0, R_ECC_PATT_IND, 7f
1604         nop
1605         dli     R_ECC_PAT0_0, DATA_FOR_ECC_PATT4
1606         dli     R_ECC_PAT0_1, DATA_FOR_ECC_PATT4
1607         dli     R_ECC_PAT0_2, DATA_FOR_ECC_PATT4
1608         dli     R_ECC_PAT0_3, DATA_FOR_ECC_PATT4
1609         dli     R_ECC_PAT1_0, DATA_FOR_ECC_INVPATT4
1610         dli     R_ECC_PAT1_1, DATA_FOR_ECC_INVPATT4
1611         dli     R_ECC_PAT1_2, DATA_FOR_ECC_INVPATT4
1612         dli     R_ECC_PAT1_3, DATA_FOR_ECC_INVPATT4
1613         b       ecc_next_pattern
1614         nop
1615 7:
1616
1617         li      R_BG_SCRATCH0, 2
1618 1:
1619         dli     R_BG_SCRATCH1, 2
1620 2:
1621         daddiu  R_BG_SCRATCH1, R_BG_SCRATCH1, -1
1622         bne     R_BG_SCRATCH1, $0, 2b
1623         nop
1624         daddiu  R_BG_SCRATCH0, R_BG_SCRATCH0, -1
1625         bne     R_BG_SCRATCH0, $0, 1b
1626         nop
1627
1628         dli     R_ECC_RADDR, XKPHYS_C_COH_EXC
1629         dli     R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
1630         or      R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0
1631         sll     R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
1632         or      R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
1633         li      R_ECC_NEXT_WAY, 0x20000
1634
1635         move    R_ECC_LINE,zero
1636 ecc_march5:
1637         move    R_PASS_FAIL, zero
1638         ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT0_0,R_ECC_PAT0_1,R_ECC_PAT0_2,R_ECC_PAT0_3,ecc_err)
1639         ECC_WRITE_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3)
1640         SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
1641         daddiu  R_ECC_RADDR, R_ECC_RADDR, 0x20
1642
1643         slt     R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1
1644         bne     R_ECC_SCRATCH0, $0, ecc_march5
1645         add     R_ECC_LINE, R_ECC_LINE,1
1646
1647         dli     R_ECC_RADDR, XKPHYS_C_COH_EXC
1648         dli     R_ECC_SCRATCH0, L2_RAM_BASE_ADDR
1649         or      R_ECC_RADDR, R_ECC_RADDR, R_WRBC_SCRATCH0
1650         sll     R_ECC_SCRATCH1, R_ECC_BLOCK, L2_BLOCK_SHIFT
1651         or      R_ECC_RADDR, R_ECC_RADDR, R_ECC_SCRATCH1
1652         li      R_ECC_NEXT_WAY, 0x20000
1653
1654         li      R_BG_SCRATCH0, 2
1655 1:
1656         dli     R_BG_SCRATCH1, 2
1657 2:
1658         daddiu  R_BG_SCRATCH1, R_BG_SCRATCH1, -1
1659         bne     R_BG_SCRATCH1, $0, 2b
1660         nop
1661         daddiu  R_BG_SCRATCH0, R_BG_SCRATCH0, -1
1662         bne     R_BG_SCRATCH0, $0, 1b
1663         nop
1664
1665         move    R_ECC_LINE,zero
1666 ecc_march6:
1667         move    R_PASS_FAIL, zero
1668         ECC_CHECK_PAT(R_ECC_WADDR,R_ECC_PAT1_0,R_ECC_PAT1_1,R_ECC_PAT1_2,R_ECC_PAT1_3,ecc_err)
1669         SET_ERR_TABLE(R_PASS_FAIL, R_ECC_LINE)
1670         daddiu  R_ECC_RADDR, R_ECC_RADDR, 0x20
1671
1672         slt     R_ECC_SCRATCH0,R_ECC_LINE,L2_LINES_PER_BLOCK-1
1673         bne     R_ECC_SCRATCH0, $0, ecc_march6
1674         add     R_ECC_LINE, R_ECC_LINE,1
1675
1676         /* if error, put test block info into s0 and return */
1677         or      R_BG_SCRATCH0, R_ERR_TABLE_0, R_ERR_TABLE_1
1678         or      R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_2
1679         or      R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_3
1680         beq     R_BG_SCRATCH0, zero, 1f
1681         nop
1682         move    s0, R_BG_BLOCK
1683         or      s0, s0, 2 << 8
1684         jr      ra
1685         nop
1686 1:
1687
1688         addi    R_ECC_BLOCK, R_ECC_BLOCK, 1
1689         /*slt   R_ECC_SCRATCH0, R_ECC_BLOCK, (L2_BLOCKS_PER_ROW * L2_BLOCK_ROWS)*/
1690         addi    R_ECC_SCRATCH1, k0, 1
1691         sll     R_ECC_SCRATCH1, R_ECC_SCRATCH1, 2
1692         slt     R_ECC_SCRATCH0, R_ECC_BLOCK, R_ECC_SCRATCH1
1693         /*slt   R_ECC_SCRATCH0, R_ECC_BLOCK, (START_BLK + TOTAL_BLKS)*/
1694         bne     R_ECC_SCRATCH0,$0, ecc_next_block
1695         nop
1696
1697         .set    noreorder
1698         move    v0, v0
1699         jr      ra
1700         nop
1701
1702 ecc_err:
1703         li      v0, 1
1704         jr      ra
1705         nop
1706
1707 END(l2dtest_data_ecc)
1708 #endif
1709 #endif
1710
1711
1712 #ifdef DATA_TEST
1713
1714 #define L2_TAG_LINES       256
1715 #define L2_TAG_BLOCKS      8
1716
1717 #define R_PAT0_0       a0
1718 #define R_PAT0_1       a1
1719 #define R_PAT0_2       a2
1720 #define R_PAT0_3       a3
1721
1722 #define R_PAT1_0       t0
1723 #define R_PAT1_1       t1
1724 #define R_PAT1_2       t2
1725 #define R_PAT1_3       t3
1726
1727 #define R_PATT_IND       s0
1728 #define R_LINE       s2
1729 #define R_NEXT_WAY   s3
1730 #define R_BLOCK      s1
1731 #define R_WADDR      t5
1732 #define R_RADDR      t5
1733
1734 #define R_SCRATCH0   t6
1735 #define R_SCRATCH1   t7
1736 #define R_SCRATCH2   t8
1737 #define R_SCRATCH3   t9
1738 #define R_SCRATCH4   s6
1739 #define R_SCRATCH5   s7
1740
1741 #ifndef _SB1250_PASS2_
1742 #define L2_READ_TAG_MASK        0x300fffffe0000
1743 #else
1744 #define L2_READ_TAG_MASK        0x3007fffff8000
1745 #endif
1746
1747 #ifndef _SB1250_PASS2_
1748
1749 #define TAG_PATT0 0x0
1750 #define TAG_PATT1 0x1555555
1751 #define TAG_PATT2 0x1333333
1752 #define TAG_PATT3 0x10f0f0f
1753 #define TAG_PATT4 0x0ff00ff
1754 #define TAG_PATT5 0x0ffff
1755
1756 #define TAG_INVPATT0 0x1ffffff
1757 #define TAG_INVPATT1 0x0aaaaaa
1758 #define TAG_INVPATT2 0x0cccccc
1759 #define TAG_INVPATT3 0x0f0f0f0
1760 #define TAG_INVPATT4 0x100ff00
1761 #define TAG_INVPATT5 0x1ff0000
1762
1763 #else
1764
1765 #define TAG_PATT0 0x0
1766 #define TAG_PATT1 0x1555555
1767 #define TAG_PATT2 0x3333333
1768 #define TAG_PATT3 0x10f0f0f
1769 #define TAG_PATT4 0x0ff00ff
1770 #define TAG_PATT5 0x0ffff
1771
1772 #define TAG_INVPATT0 0x3ffffff
1773 #define TAG_INVPATT1 0x2aaaaaa
1774 #define TAG_INVPATT2 0x0cccccc
1775 #define TAG_INVPATT3 0x0f0f0f0
1776 #define TAG_INVPATT4 0x300ff00
1777 #define TAG_INVPATT5 0x3ff0000
1778
1779 #endif
1780
1781
1782 #define TAG_WRITE_PAT(addr, pattern0, pattern1)\
1783         dli     R_SCRATCH0, L2M_WRITE_TAG; \
1784         or      R_SCRATCH0, addr, R_SCRATCH0; \
1785         sd      pattern0, 0x18(R_SCRATCH0); \
1786         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \
1787         sd      pattern1, 0x2018(R_SCRATCH0); \
1788         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0); \
1789         daddu   R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \
1790         sd      pattern0, 0x18(R_SCRATCH0); \
1791         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \
1792         sd      pattern1, 0x2018(R_SCRATCH0); \
1793         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0); \
1794         daddu   R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \
1795         sd      pattern0, 0x18(R_SCRATCH0); \
1796         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \
1797         sd      pattern1, 0x2018(R_SCRATCH0); \
1798         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0); \
1799         daddu   R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \
1800         sd      pattern0, 0x18(R_SCRATCH0); \
1801         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \
1802         sd      pattern1, 0x2018(R_SCRATCH0); \
1803         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0)
1804
1805 #ifndef _SB1250_PASS2_
1806 #define TAG_MAKE_PAT(pattern0, pattern1)\
1807         li      R_SCRATCH4, 0x800000;\
1808         and     R_SCRATCH2, R_SCRATCH4, pattern0;\
1809         dsll    R_SCRATCH2, R_SCRATCH2, 26;\
1810         li      R_SCRATCH4, 0x1000000;\
1811         and     R_SCRATCH4, R_SCRATCH4, pattern0;\
1812         dsll    R_SCRATCH4, R_SCRATCH4, 24;\
1813         or      R_SCRATCH2, R_SCRATCH2, R_SCRATCH4;\
1814         li      R_SCRATCH4, 0x7fffff;\
1815         and     R_SCRATCH4, R_SCRATCH4, pattern0;\
1816         dsll    R_SCRATCH4, R_SCRATCH4, 17;\
1817         or      R_SCRATCH2, R_SCRATCH2, R_SCRATCH4;\
1818         dli     R_SCRATCH4, L2_READ_TAG_MASK; \
1819         and     pattern1, R_SCRATCH2, R_SCRATCH4;
1820
1821 #else
1822
1823 #define TAG_MAKE_PAT(pattern0, pattern1)\
1824         li      R_SCRATCH4, 0x1000000;\
1825         and     R_SCRATCH2, R_SCRATCH4, pattern0;\
1826         dsll    R_SCRATCH2, R_SCRATCH2, 25;\
1827         li      R_SCRATCH4, 0x2000000;\
1828         and     R_SCRATCH4, R_SCRATCH4, pattern0;\
1829         dsll    R_SCRATCH4, R_SCRATCH4, 23;\
1830         or      R_SCRATCH2, R_SCRATCH2, R_SCRATCH4;\
1831         li      R_SCRATCH4, 0x3fffff;\
1832         and     R_SCRATCH4, R_SCRATCH4, pattern0;\
1833         dsll    R_SCRATCH4, R_SCRATCH4, 17;\
1834         or      R_SCRATCH2, R_SCRATCH2, R_SCRATCH4;\
1835         li      R_SCRATCH4, 0xc00000;\
1836         and     R_SCRATCH4, R_SCRATCH4, pattern0;\
1837         dsrl    R_SCRATCH4, R_SCRATCH4, 7;\
1838         or      R_SCRATCH2, R_SCRATCH2, R_SCRATCH4;\
1839         dli     R_SCRATCH4, L2_READ_TAG_MASK; \
1840         and     pattern1, R_SCRATCH2, R_SCRATCH4;
1841
1842 #endif
1843
1844 #define TAG_CHECK_PAT(addr, pattern0, pattern1)\
1845         li      R_SCRATCH2, 4;\
1846         dli     R_SCRATCH4, XKPHYS_UNC; \
1847         dli     R_SCRATCH5, L2_BASE; \
1848         or      R_SCRATCH4, R_SCRATCH4, R_SCRATCH5; \
1849         dli     R_SCRATCH5, L2_READ_TAG_MASK;\
1850         dli     R_SCRATCH0, L2M_READ_RAW_ACCESS; \
1851         or      R_SCRATCH0, addr, R_SCRATCH0; \
1852 1:      ld      R_SCRATCH1, (R_SCRATCH0); \
1853         sync; \
1854         ld      R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \
1855         and     R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \
1856         sne     R_SCRATCH1, R_SCRATCH1, pattern0; \
1857         or      R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1;   \
1858         ld      R_SCRATCH1, 0x2000(R_SCRATCH0); \
1859         sync; \
1860         ld      R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \
1861         and     R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \
1862         sne     R_SCRATCH1, R_SCRATCH1, pattern1; \
1863         or      R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1;   \
1864         addi    R_SCRATCH2, R_SCRATCH2, -1;     \
1865         bne     R_SCRATCH2, zero, 1b;   \
1866         daddu   R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY
1867
1868 #define TAG_CHECK_PAT1(addr, pattern0, pattern1)\
1869         li      R_SCRATCH2, 4;\
1870         dli     R_SCRATCH4, XKPHYS_UNC; \
1871         dli     R_SCRATCH5, L2_BASE; \
1872         or      R_SCRATCH4, R_SCRATCH4, R_SCRATCH5; \
1873         dli     R_SCRATCH5, L2_READ_TAG_MASK;\
1874         dli     R_SCRATCH0, 0x00200000; \
1875         or      R_SCRATCH0, addr, R_SCRATCH0; \
1876 1:      ld      R_SCRATCH1, (R_SCRATCH0); \
1877         sync; \
1878         ld      R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \
1879         and     R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \
1880         sne     R_SCRATCH1, R_SCRATCH1, pattern0; \
1881         or      R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1;   \
1882         ld      R_SCRATCH1, 0x2000(R_SCRATCH0); \
1883         sync; \
1884         ld      R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \
1885         and     R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \
1886         sne     R_SCRATCH1, R_SCRATCH1, pattern1; \
1887         or      R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1;   \
1888         addi    R_SCRATCH2, R_SCRATCH2, -1;     \
1889         bne     R_SCRATCH2, zero, 1b;   \
1890         daddu   R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY
1891
1892
1893 LEAF(l2dtest_tag_data)
1894 /*
1895         move    R_ERR_TABLE_0, $0
1896         move    R_ERR_TABLE_1, $0
1897         move    R_ERR_TABLE_2, $0
1898         move    R_ERR_TABLE_3, $0
1899 */
1900         /*li    R_BLOCK, START_BLK*/
1901         sll     R_BLOCK, k0, 1
1902         li      R_NEXT_WAY,0x20000
1903 tag_next_block:
1904 #ifdef USE_LEDS
1905         addi    R_BG_SCRATCH2, R_BG_BLOCK, '0'
1906         or      R_BG_SCRATCH2, R_BG_SCRATCH2, ('T' << 8)
1907         SET_LEDS_HI(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1)
1908 #endif
1909
1910         move    R_PATT_IND, $0
1911         dli     R_PAT0_0, TAG_PATT0
1912         dli     R_PAT0_1, TAG_PATT0
1913         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
1914         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
1915         dli     R_PAT1_0, TAG_INVPATT0
1916         dli     R_PAT1_1, TAG_INVPATT0
1917         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
1918         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
1919
1920 tag_next_pattern:
1921 #ifdef USE_LEDS
1922         addi    R_BG_SCRATCH2, R_PATT_IND, '0'
1923         or      R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8)
1924         SET_LEDS_LO(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1)
1925 #endif
1926
1927         dli     R_WADDR, XKPHYS_C_COH_EXC       /* uncached accelerated */
1928         dli     R_SCRATCH0, L2_RAM_BASE_ADDR    /* mgmt mode */
1929         or      R_WADDR,R_ECC_WADDR,R_BG_SCRATCH0
1930         sll     R_SCRATCH0, R_BLOCK, L2_BLOCK_ROW_SHIFT /* block number */
1931         or      R_WADDR, R_WADDR, R_SCRATCH0
1932
1933         .set    noreorder
1934         move    R_LINE, zero
1935 tag_init_next_line:
1936         TAG_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1)
1937         li      R_SCRATCH0, (32)
1938         dadd    R_WADDR, R_WADDR, R_SCRATCH0    /* next line */
1939
1940         slt     R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1
1941         bne     R_SCRATCH0, $0, tag_init_next_line
1942         add     R_LINE, R_LINE,1
1943
1944         dli     R_RADDR, XKPHYS_C_COH_EXC
1945         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
1946         or      R_RADDR, R_RADDR, R_SCRATCH0
1947         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
1948         or      R_RADDR, R_RADDR, R_SCRATCH1
1949         li      R_NEXT_WAY, 0x20000
1950
1951         move    R_LINE, zero
1952 tag_march1:
1953         move    R_PASS_FAIL, zero
1954         TAG_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3)
1955         TAG_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1)
1956         TAG_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3)
1957         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
1958         daddiu  R_RADDR, R_RADDR, 0x20
1959
1960         slt     R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1
1961         bne     R_SCRATCH0, $0, tag_march1
1962         add     R_LINE, R_LINE,1
1963
1964         dli     R_RADDR, XKPHYS_C_COH_EXC
1965         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
1966         or      R_RADDR, R_RADDR, R_SCRATCH0
1967         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
1968         or      R_RADDR, R_RADDR, R_SCRATCH1
1969
1970         move    R_LINE,zero
1971 tag_march2:
1972         move    R_PASS_FAIL, zero
1973         TAG_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3)
1974         TAG_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1)
1975         TAG_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3)
1976         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
1977         daddiu  R_RADDR, R_RADDR, 0x20
1978
1979         slt     R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1
1980         bne     R_SCRATCH0, $0, tag_march2
1981         add     R_LINE, R_LINE,1
1982
1983         dli     R_RADDR, XKPHYS_C_COH_EXC
1984         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
1985         or      R_RADDR, R_RADDR, R_SCRATCH0
1986 #ifdef TEST_ALL_LINES
1987         sll     R_SCRATCH0, R_BLOCK, 1
1988         addi    R_SCRATCH0, R_SCRATCH0, 1
1989         sll     R_SCRATCH1, R_SCRATCH0, L2_BLOCK_SHIFT
1990 #else
1991         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
1992 #endif
1993         or      R_RADDR, R_RADDR, R_SCRATCH1
1994 #ifdef TEST_ALL_LINES
1995         daddiu  R_RADDR, R_RADDR, -32
1996 #else
1997         daddiu  R_RADDR, R_RADDR, L2_LINES_PER_BLOCK*32-32
1998 #endif
1999         li      R_LINE,L2_LINES_PER_BLOCK-1
2000 tag_march3:
2001         move    R_PASS_FAIL, zero
2002         TAG_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3)
2003         TAG_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1)
2004         TAG_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3)
2005         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
2006         daddiu  R_RADDR, R_RADDR, -32
2007
2008         bne     R_LINE,$0, tag_march3
2009         add     R_LINE,R_LINE,-1
2010
2011         dli     R_RADDR, XKPHYS_C_COH_EXC
2012         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
2013         or      R_RADDR, R_RADDR, R_SCRATCH0
2014 #ifdef TEST_ALL_LINES
2015         sll     R_SCRATCH0, R_BLOCK, 1
2016         addi    R_SCRATCH0, R_SCRATCH0, 1
2017         sll     R_SCRATCH1, R_SCRATCH0, L2_BLOCK_SHIFT
2018 #else
2019         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
2020 #endif
2021         or      R_RADDR, R_RADDR, R_SCRATCH1
2022 #ifdef TEST_ALL_LINES
2023         daddiu  R_RADDR, R_RADDR, -32
2024 #else
2025         daddiu  R_RADDR, R_RADDR, L2_LINES_PER_BLOCK*32-32
2026 #endif
2027         li      R_LINE,L2_LINES_PER_BLOCK-1
2028 tag_march4:
2029         move    R_PASS_FAIL, zero
2030         TAG_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3)
2031         TAG_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1)
2032         TAG_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3)
2033         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
2034         daddiu  R_RADDR, R_RADDR, -32
2035
2036         bne     R_LINE,$0, tag_march4
2037         add     R_LINE,R_LINE,-1
2038
2039         addi    R_PATT_IND, R_PATT_IND, 1
2040         li      R_SCRATCH0, 1
2041         bne     R_SCRATCH0, R_PATT_IND, 2f
2042         nop
2043         dli     R_PAT0_0, TAG_INVPATT0
2044         dli     R_PAT0_1, TAG_PATT0
2045         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
2046         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
2047         dli     R_PAT1_0, TAG_PATT0
2048         dli     R_PAT1_1, TAG_INVPATT0
2049         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
2050         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
2051
2052         b       tag_next_pattern
2053 2:
2054         li      R_SCRATCH0, 2
2055         bne     R_SCRATCH0, R_PATT_IND, 3f
2056         nop
2057
2058         dli     R_PAT0_0, TAG_PATT2
2059         dli     R_PAT0_1, TAG_PATT2
2060         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
2061         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
2062         dli     R_PAT1_0, TAG_INVPATT2
2063         dli     R_PAT1_1, TAG_INVPATT2
2064         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
2065         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
2066         b       tag_next_pattern
2067 3:
2068         li      R_SCRATCH0, 3
2069         bne     R_SCRATCH0, R_PATT_IND, 4f
2070         nop
2071
2072         dli     R_PAT0_0, TAG_PATT3
2073         dli     R_PAT0_1, TAG_PATT3
2074         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
2075         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
2076         dli     R_PAT1_0, TAG_INVPATT3
2077         dli     R_PAT1_1, TAG_INVPATT3
2078         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
2079         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
2080         b       tag_next_pattern
2081 4:
2082         li      R_SCRATCH0, 4
2083         bne     R_SCRATCH0, R_PATT_IND, 5f
2084         nop
2085
2086         dli     R_PAT0_0, TAG_PATT4
2087         dli     R_PAT0_1, TAG_PATT4
2088         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
2089         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
2090         dli     R_PAT1_0, TAG_INVPATT4
2091         dli     R_PAT1_1, TAG_INVPATT4
2092         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
2093         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
2094         b       tag_next_pattern
2095 5:
2096         li      R_SCRATCH0, 5
2097         bne     R_SCRATCH0, R_PATT_IND, 6f
2098         nop
2099
2100         dli     R_PAT0_0, TAG_PATT5
2101         dli     R_PAT0_1, TAG_PATT5
2102         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
2103         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
2104         dli     R_PAT1_0, TAG_INVPATT5
2105         dli     R_PAT1_1, TAG_INVPATT5
2106         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
2107         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
2108         b       tag_next_pattern
2109         nop
2110 6:
2111         li      R_SCRATCH0, 2
2112 1:
2113         dli     R_SCRATCH1, 2
2114 2:
2115         daddiu  R_SCRATCH1, R_SCRATCH1, -1
2116         bne     R_SCRATCH1, $0, 2b
2117         nop
2118         daddiu  R_SCRATCH0, R_SCRATCH0, -1
2119         bne     R_SCRATCH0, $0, 1b
2120         nop
2121
2122         dli     R_RADDR, XKPHYS_C_COH_EXC
2123         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
2124         or      R_RADDR, R_RADDR, R_SCRATCH0
2125         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
2126         or      R_RADDR, R_RADDR, R_SCRATCH1
2127         li      R_NEXT_WAY, 0x20000
2128
2129         move    R_LINE,zero
2130 tag_march5:
2131         move    R_PASS_FAIL, zero
2132         TAG_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3)
2133         TAG_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1)
2134         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
2135         daddiu  R_RADDR, R_RADDR, 0x20
2136
2137         slt     R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1
2138         bne     R_SCRATCH0, $0, tag_march5
2139         add     R_LINE, R_LINE,1
2140
2141         li      R_SCRATCH0, 2
2142 1:
2143         dli     R_SCRATCH1, 2
2144 2:
2145         daddiu  R_SCRATCH1, R_SCRATCH1, -1
2146         bne     R_SCRATCH1, $0, 2b
2147         nop
2148         daddiu  R_SCRATCH0, R_SCRATCH0, -1
2149         bne     R_SCRATCH0, $0, 1b
2150         nop
2151
2152         dli     R_RADDR, XKPHYS_C_COH_EXC
2153         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
2154         or      R_RADDR, R_RADDR, R_SCRATCH0
2155         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
2156         or      R_RADDR, R_RADDR, R_SCRATCH1
2157
2158         move    R_LINE,zero
2159 tag_march6:
2160         move    R_PASS_FAIL, zero
2161         TAG_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3)
2162         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
2163         daddiu  R_RADDR, R_RADDR, 0x20
2164
2165         slt     R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1
2166         bne     R_SCRATCH0, $0, tag_march6
2167         add     R_LINE, R_LINE,1
2168
2169         /* if error, put test block info into s0 and return */
2170         or      R_BG_SCRATCH0, R_ERR_TABLE_0, R_ERR_TABLE_1
2171         or      R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_2
2172         or      R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_3
2173         beq     R_BG_SCRATCH0, zero, 1f
2174         nop
2175         move    s0, R_BG_BLOCK
2176         or      s0, s0, 3 << 8
2177         jr      ra
2178         nop
2179 1:
2180
2181         addi    R_BLOCK, R_BLOCK, 1
2182         addi    R_SCRATCH1, k0, 1
2183         sll     R_SCRATCH1, R_SCRATCH1, 1
2184         /*slt   R_SCRATCH0, R_BLOCK, START_BLK+TOTAL_BLKS/2*/
2185         slt     R_SCRATCH0, R_BLOCK, R_SCRATCH1
2186         bne     R_SCRATCH0,$0, tag_next_block
2187         nop
2188         .set    noreorder
2189         jr      ra
2190         nop
2191
2192 tag_err:
2193         li      v0, 1
2194         jr      ra
2195         nop
2196
2197 END(l2dtest_tag_data)
2198
2199 #define TAG_ECC_PATT0 0x0
2200 #define TAG_ECC_PATT1 0x0000003d
2201 #define TAG_ECC_PATT2 0x00000009
2202 #define TAG_ECC_PATT3 0x0000001d
2203
2204 #define TAG_ECC_INVPATT0 0x0000000f
2205 #define TAG_ECC_INVPATT1 0x00000032
2206 #define TAG_ECC_INVPATT2 0x00000006
2207 #define TAG_ECC_INVPATT3 0x00000012
2208
2209
2210 #define TAG_ECC_WRITE_PAT(addr, pattern0, pattern1)\
2211         dli     R_SCRATCH0, L2M_WRITE_TAG; \
2212         or      R_SCRATCH0, addr, R_SCRATCH0; \
2213         sd      pattern0, 0x18(R_SCRATCH0); \
2214         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \
2215         sync;   \
2216         sd      pattern1, 0x2018(R_SCRATCH0); \
2217         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \
2218         sync;   \
2219         daddu   R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \
2220         sd      pattern0, 0x18(R_SCRATCH0); \
2221         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \
2222         sync;   \
2223         sd      pattern1, 0x2018(R_SCRATCH0); \
2224         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0); \
2225         sync;   \
2226         daddu   R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \
2227         sd      pattern0, 0x18(R_SCRATCH0); \
2228         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \
2229         sync;   \
2230         sd      pattern1, 0x2018(R_SCRATCH0); \
2231         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0); \
2232         sync;   \
2233         daddu   R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY; \
2234         sd      pattern0, 0x18(R_SCRATCH0); \
2235         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0(R_SCRATCH0); \
2236         sync;   \
2237         sd      pattern1, 0x2018(R_SCRATCH0); \
2238         cache   L1CACHEOP(L1C_D,L1C_OP_HIT_WB_INVAL),0x2000(R_SCRATCH0);\
2239         sync
2240
2241 #define TAG_ECC_CHECK_PAT(addr, pattern0, pattern1)\
2242         li      R_SCRATCH2, 2;\
2243         dli     R_SCRATCH5, XKPHYS_UNC; \
2244         dli     R_SCRATCH3, SCD_BW_BASE; \
2245         or      R_SCRATCH3, R_SCRATCH3, R_SCRATCH5; \
2246         sd      zero, BUS_L2_ERRORS(R_SCRATCH3); \
2247         sync;   \
2248         dli     R_SCRATCH4, L2_BASE; \
2249         or      R_SCRATCH4, R_SCRATCH4, R_SCRATCH5; \
2250         move    R_SCRATCH0, addr;       \
2251 1:      dli     R_SCRATCH5, L2_READ_TAG_MASK;\
2252         ld      R_SCRATCH1, (R_SCRATCH0); \
2253         sync; \
2254         ld      R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \
2255         and     R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \
2256         sne     R_SCRATCH1, R_SCRATCH1, pattern0; \
2257         or      R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1;   \
2258         ld      R_SCRATCH1, 0x2000(R_SCRATCH0); \
2259         sync; \
2260         ld      R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \
2261         and     R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \
2262         sne     R_SCRATCH1, R_SCRATCH1, pattern1; \
2263         or      R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1;   \
2264         daddu   R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY;\
2265         ld      R_SCRATCH1, (R_SCRATCH0); \
2266         sync; \
2267         ld      R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \
2268         and     R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \
2269         sne     R_SCRATCH1, R_SCRATCH1, pattern0; \
2270         or      R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1;   \
2271         ld      R_SCRATCH1, 0x2000(R_SCRATCH0); \
2272         sync; \
2273         ld      R_SCRATCH1, L2_READ_TAG(R_SCRATCH4); \
2274         and     R_SCRATCH1, R_SCRATCH1, R_SCRATCH5; \
2275         sne     R_SCRATCH1, R_SCRATCH1, pattern1; \
2276         or      R_PASS_FAIL, R_PASS_FAIL, R_SCRATCH1;   \
2277         addi    R_SCRATCH2, R_SCRATCH2, -1;     \
2278         bne     R_SCRATCH2, zero, 1b;   \
2279         daddu   R_SCRATCH0, R_SCRATCH0, R_NEXT_WAY;\
2280         /*TAG_CHECK_PAT(addr, pattern0, pattern1) ;*/ \
2281         dli     R_SCRATCH5, XKPHYS_UNC; \
2282         dli     R_SCRATCH3, SCD_BW_BASE; \
2283         or      R_SCRATCH3, R_SCRATCH3, R_SCRATCH5; \
2284         ld      R_SCRATCH5, BUS_L2_ERRORS(R_SCRATCH3); \
2285         dsrl    R_SCRATCH5, R_SCRATCH5, 16;     \
2286         sne     R_SCRATCH5, R_ECC_SCRATCH5, $0; \
2287         or      R_PASS_FAIL, R_PASS_FAIL, R_ECC_SCRATCH5
2288
2289 LEAF(l2dtest_tag_ecc)
2290
2291         /*li    R_BLOCK, START_BLK*/
2292         sll     R_BLOCK, k0, 1
2293         li      R_NEXT_WAY,0x20000
2294 tag_ecc_next_block:
2295 #ifdef USE_LEDS
2296         addi    R_BG_SCRATCH2, R_BG_BLOCK, '0'
2297         or      R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8)
2298         SET_LEDS_HI(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1)
2299 #endif
2300
2301         move    R_PATT_IND, $0
2302         dli     R_PAT0_0, TAG_ECC_PATT0
2303         dli     R_PAT0_1, TAG_ECC_PATT0
2304         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
2305         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
2306         dli     R_PAT1_0, TAG_ECC_INVPATT0
2307         dli     R_PAT1_1, TAG_ECC_INVPATT0
2308         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
2309         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
2310
2311 tag_ecc_next_pattern:
2312 #ifdef USE_LEDS
2313         addi    R_BG_SCRATCH2, R_PATT_IND, '0'
2314         or      R_BG_SCRATCH2, R_BG_SCRATCH2, ('P' << 8)
2315         SET_LEDS_LO(R_BG_SCRATCH2, R_BG_SCRATCH0, R_BG_SCRATCH1)
2316 #endif
2317
2318         dli     R_WADDR, XKPHYS_C_COH_EXC       /* uncached accelerated */
2319         dli     R_SCRATCH0, L2_RAM_BASE_ADDR    /* mgmt mode */
2320         or      R_WADDR,R_ECC_WADDR,R_BG_SCRATCH0
2321         sll     R_SCRATCH0, R_BLOCK, L2_BLOCK_ROW_SHIFT /* block number */
2322         or      R_WADDR, R_WADDR, R_SCRATCH0
2323
2324         .set    noreorder
2325         move    R_LINE, zero
2326 tag_ecc_init_next_line:
2327         TAG_ECC_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1)
2328         li      R_SCRATCH0, (32)
2329         dadd    R_WADDR, R_WADDR, R_SCRATCH0    /* next line */
2330
2331         slt     R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1
2332         bne     R_SCRATCH0, $0, tag_ecc_init_next_line
2333         add     R_LINE, R_LINE,1
2334
2335         dli     R_RADDR, XKPHYS_C_COH_EXC
2336         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
2337         or      R_RADDR, R_RADDR, R_SCRATCH0
2338         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
2339         or      R_RADDR, R_RADDR, R_SCRATCH1
2340         li      R_NEXT_WAY, 0x20000
2341
2342         move    R_LINE,zero
2343 tag_ecc_march1:
2344         move    R_PASS_FAIL, zero
2345         TAG_ECC_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3)
2346         TAG_ECC_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1)
2347         TAG_ECC_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3)
2348         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
2349         daddiu  R_RADDR, R_RADDR, 0x20
2350
2351         slt     R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1
2352         bne     R_SCRATCH0, $0, tag_ecc_march1
2353         add     R_LINE, R_LINE,1
2354
2355         /* march2 */
2356         dli     R_RADDR, XKPHYS_C_COH_EXC
2357         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
2358         or      R_RADDR, R_RADDR, R_SCRATCH0
2359         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
2360         or      R_RADDR, R_RADDR, R_SCRATCH1
2361
2362         move    R_LINE,zero
2363 tag_ecc_march2:
2364         move    R_PASS_FAIL, zero
2365         TAG_ECC_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3)
2366         TAG_ECC_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1)
2367         TAG_ECC_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3)
2368         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
2369         daddiu  R_RADDR, R_RADDR, 0x20
2370
2371         slt     R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1
2372         bne     R_SCRATCH0, $0,  tag_ecc_march2
2373         add     R_LINE, R_LINE,1
2374
2375         /* march 3 */
2376         dli     R_RADDR, XKPHYS_C_COH_EXC
2377         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
2378         or      R_RADDR, R_RADDR, R_SCRATCH0
2379 #ifdef TEST_ALL_LINES
2380         sll     R_SCRATCH0, R_BLOCK, 1
2381         addi    R_SCRATCH0, R_SCRATCH0, 1
2382         sll     R_SCRATCH1, R_SCRATCH0, L2_BLOCK_SHIFT
2383 #else
2384         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
2385 #endif
2386         or      R_RADDR, R_RADDR, R_SCRATCH1
2387 #ifdef TEST_ALL_LINES
2388         daddiu  R_RADDR, R_RADDR, -32
2389 #else
2390         daddiu  R_RADDR, R_RADDR, L2_LINES_PER_BLOCK*32-32
2391 #endif
2392         li      R_LINE,L2_LINES_PER_BLOCK-1
2393 tag_ecc_march3:
2394         move    R_PASS_FAIL, zero
2395         TAG_ECC_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3)
2396         TAG_ECC_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1)
2397         TAG_ECC_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3)
2398         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
2399         daddiu  R_RADDR, R_RADDR, -32
2400
2401         bne     R_LINE,$0, tag_ecc_march3
2402         add     R_LINE,R_LINE,-1
2403
2404         /* march 4 */
2405         dli     R_RADDR, XKPHYS_C_COH_EXC
2406         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
2407         or      R_RADDR, R_RADDR, R_SCRATCH0
2408 #ifdef TEST_ALL_LINES
2409         sll     R_SCRATCH0, R_BLOCK, 1
2410         addi    R_SCRATCH0, R_SCRATCH0, 1
2411         sll     R_SCRATCH1, R_SCRATCH0, L2_BLOCK_SHIFT
2412 #else
2413         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
2414 #endif
2415         or      R_RADDR, R_RADDR, R_SCRATCH1
2416 #ifdef TEST_ALL_LINES
2417         daddiu  R_RADDR, R_RADDR, -32
2418 #else
2419         daddiu  R_RADDR, R_RADDR, L2_LINES_PER_BLOCK*32-32
2420 #endif
2421         li      R_LINE,L2_LINES_PER_BLOCK-1
2422 tag_ecc_march4:
2423         move    R_PASS_FAIL, zero
2424         TAG_ECC_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3)
2425         TAG_ECC_WRITE_PAT(R_WADDR,R_PAT0_0,R_PAT0_1)
2426         TAG_ECC_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3)
2427         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
2428         daddiu  R_RADDR, R_RADDR, -32
2429
2430         bne     R_LINE,$0, tag_ecc_march4
2431         add     R_LINE,R_LINE,-1
2432
2433         addi    R_PATT_IND, R_PATT_IND, 1
2434         li      R_SCRATCH0, 1
2435         bne     R_SCRATCH0, R_PATT_IND, 2f
2436         nop
2437         dli     R_PAT0_0, TAG_ECC_INVPATT0
2438         dli     R_PAT0_1, TAG_ECC_PATT0
2439         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
2440         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
2441         dli     R_PAT1_0, TAG_ECC_PATT0
2442         dli     R_PAT1_1, TAG_ECC_INVPATT0
2443         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
2444         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
2445         b       tag_ecc_next_pattern
2446 2:
2447         li      R_SCRATCH0, 2
2448         bne     R_SCRATCH0, R_PATT_IND, 3f
2449         nop
2450         dli     R_PAT0_0, TAG_ECC_PATT1
2451         dli     R_PAT0_1, TAG_ECC_PATT1
2452         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
2453         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
2454         dli     R_PAT1_0, TAG_ECC_INVPATT1
2455         dli     R_PAT1_1, TAG_ECC_INVPATT1
2456         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
2457         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
2458         b       tag_ecc_next_pattern
2459         nop
2460 3:
2461         li      R_SCRATCH0, 3
2462         bne     R_SCRATCH0, R_PATT_IND, 4f
2463         nop
2464         dli     R_PAT0_0, TAG_ECC_PATT2
2465         dli     R_PAT0_1, TAG_ECC_PATT2
2466         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
2467         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
2468         dli     R_PAT1_0, TAG_ECC_INVPATT2
2469         dli     R_PAT1_1, TAG_ECC_INVPATT2
2470         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
2471         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
2472         b       tag_ecc_next_pattern
2473         nop
2474 4:
2475         li      R_SCRATCH0, 4
2476         bne     R_SCRATCH0, R_PATT_IND, 5f
2477         nop
2478         dli     R_PAT0_0, TAG_ECC_PATT3
2479         dli     R_PAT0_1, TAG_ECC_PATT3
2480         TAG_MAKE_PAT(R_PAT0_0, R_PAT0_2)
2481         TAG_MAKE_PAT(R_PAT0_1, R_PAT0_3)
2482         dli     R_PAT1_0, TAG_ECC_INVPATT3
2483         dli     R_PAT1_1, TAG_ECC_INVPATT3
2484         TAG_MAKE_PAT(R_PAT1_0, R_PAT1_2)
2485         TAG_MAKE_PAT(R_PAT1_1, R_PAT1_3)
2486         b       tag_ecc_next_pattern
2487         nop
2488 5:
2489         li      R_SCRATCH0, 2
2490 1:
2491         dli     R_SCRATCH1, 2
2492 2:
2493         daddiu  R_SCRATCH1, R_SCRATCH1, -1
2494         bne     R_SCRATCH1, $0, 2b
2495         nop
2496         daddiu  R_SCRATCH0, R_SCRATCH0, -1
2497         bne     R_SCRATCH0, $0, 1b
2498         nop
2499
2500         dli     R_RADDR, XKPHYS_C_COH_EXC
2501         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
2502         or      R_RADDR, R_RADDR, R_SCRATCH0
2503         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
2504         or      R_RADDR, R_RADDR, R_SCRATCH1
2505         li      R_NEXT_WAY, 0x20000
2506
2507         move    R_LINE,zero
2508 tag_ecc_march5:
2509         move    R_PASS_FAIL, zero
2510         TAG_ECC_CHECK_PAT(R_WADDR,R_PAT0_2,R_PAT0_3)
2511         TAG_ECC_WRITE_PAT(R_WADDR,R_PAT1_0,R_PAT1_1)
2512         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
2513         daddiu  R_RADDR, R_RADDR, 0x20
2514
2515         slt     R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1
2516         bne     R_SCRATCH0, $0,  tag_ecc_march5
2517         add     R_LINE, R_LINE,1
2518
2519         li      R_SCRATCH0, 2
2520 1:
2521         dli     R_SCRATCH1, 2
2522 2:
2523         daddiu  R_SCRATCH1, R_SCRATCH1, -1
2524         bne     R_SCRATCH1, $0, 2b
2525         nop
2526         daddiu  R_SCRATCH0, R_SCRATCH0, -1
2527         bne     R_SCRATCH0, $0, 1b
2528         nop
2529
2530         dli     R_RADDR, XKPHYS_C_COH_EXC
2531         dli     R_SCRATCH0, L2_RAM_BASE_ADDR
2532         or      R_RADDR, R_RADDR, R_SCRATCH0
2533         sll     R_SCRATCH1, R_BLOCK, L2_BLOCK_ROW_SHIFT
2534         or      R_RADDR, R_RADDR, R_SCRATCH1
2535
2536         move    R_LINE,zero
2537 tag_ecc_march6:
2538         move    R_PASS_FAIL, zero
2539         TAG_ECC_CHECK_PAT(R_WADDR,R_PAT1_2,R_PAT1_3)
2540         SET_ERR_TABLE(R_PASS_FAIL, R_LINE)
2541         daddiu  R_RADDR, R_RADDR, 0x20
2542
2543         slt     R_SCRATCH0,R_LINE,L2_LINES_PER_BLOCK-1
2544         bne     R_SCRATCH0, $0, tag_ecc_march6
2545         add     R_LINE, R_LINE,1
2546
2547         /* if error, put test block info into s0 and return */
2548         or      R_BG_SCRATCH0, R_ERR_TABLE_0, R_ERR_TABLE_1
2549         or      R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_2
2550         or      R_BG_SCRATCH0, R_BG_SCRATCH0, R_ERR_TABLE_3
2551         beq     R_BG_SCRATCH0, zero, 1f
2552         nop
2553         move    s0, R_BG_BLOCK
2554         or      s0, s0, 4 << 8
2555         jr      ra
2556         nop
2557 1:
2558
2559         addi    R_BLOCK, R_BLOCK, 1
2560         addi    R_SCRATCH1, k0, 1
2561         sll     R_SCRATCH1, R_SCRATCH1, 1
2562         slt     R_SCRATCH0, R_BLOCK, R_SCRATCH1
2563         /*slt   R_SCRATCH0, R_BLOCK, START_BLK+TOTAL_BLKS/2*/
2564         bne     R_SCRATCH0,$0,  tag_ecc_next_block
2565         nop
2566
2567         .set    noreorder
2568         jr      ra
2569         nop
2570
2571 tag_ecc_err:
2572         li      v0, 1
2573         jr      ra
2574         nop
2575
2576 END(l2dtest_tag_ecc)
2577
2578 #endif
2579
2580 LEAF(sb1250_l2cache_init1)
2581 #define CACHE_LINE_SIZE   32
2582
2583         # Save the old status register, and set the KX bit.
2584 /*
2585                 dmfc0   t2,C0_SR
2586                 or      t1,t2,SR_KX
2587                 dmtc0   t1,C0_SR
2588 */
2589         # Start the index at the base of the cache management
2590         # area, but leave the address bit for "Valid" zero.
2591         # Note that the management tags are at 00_D000_0000,
2592         # which cannot be expressed with the PHYS_TO_K1 macro,
2593         # so well need to use a 64-bit address to get to it.
2594
2595
2596 #               dli     t0,PHYS_TO_XKPHYS_UNC(L2C_MGMT_TAG_BASE)
2597                 dli     t8,PHYS_TO_XKPHYS_UNC(A_L2C_MGMT_TAG_BASE)
2598                 dli     t7, START_BLK
2599 3:              dsll    t4, t7, 13
2600                 dadd    t4, t8, t4
2601
2602         # Loop through each entry and each way
2603
2604                 /* li   t1,L2_LINES_PER_BLOCK*L2C_NUM_WAYS */
2605                 li      t5, L2C_NUM_WAYS
2606
2607         # Write a zero to the cache management register at each
2608         # address.
2609 2:              move    t0, t4
2610                 li      t1, L2_LINES_PER_BLOCK
2611 1:              sd      zero,(t0)
2612                 nop
2613                 daddu   t0,(CACHE_LINE_SIZE) # size of a cache line
2614                 subu    t1,1
2615                 bne     t1,0,1b
2616                 nop
2617
2618                 dli     t6, 0x20000
2619                 dadd    t4, t4, t6
2620                 subu    t5, 1
2621                 bne     t5, 0, 2b
2622                 nop
2623
2624                 addu    t7, t7, 1
2625                 slt     t0, t7, START_BLK+TOTAL_BLKS
2626                 bne     t0, zero, 3b
2627                 nop
2628
2629         #
2630         # Restore old KX bit setting
2631         #
2632 /*
2633                 dmtc0   t2,C0_SR
2634 */
2635                 j       ra              # return to caller
2636
2637                 .set noreorder
2638                 nop;nop;nop;nop
2639
2640 END(sb1250_l2cache_init1)
2641
2642 #ifdef RUN_FROM_K0
2643
2644 LEAF(to_kseg0)
2645         li      v0, ~K1BASE
2646         and     ra, ra, v0
2647         li      v0, K0BASE
2648         or      ra, ra, v0
2649         jr      ra;
2650         nop
2651 END(to_kseg0)
2652
2653 #endif