release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/sbmips.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  MIPS64 CPU definitions                   File: sbmips.h
   5     *
   6     *  This module contains constants and macros specific to the
   7     *  SB1 MIPS64 core.
   8     *
   9     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This software is furnished under license and may be used and
  17     *  copied only in accordance with the following terms and
  18     *  conditions.  Subject to these conditions, you may download,
  19     *  copy, install, use, modify and distribute modified or unmodified
  20     *  copies of this software in source and/or binary form.  No title
  21     *  or ownership is transferred hereby.
  22     *
  23     *  1) Any source code used, modified or distributed must reproduce
  24     *     and retain this copyright notice and list of conditions
  25     *     as they appear in the source file.
  26     *
  27     *  2) No right is granted to use any trade name, trademark, or
  28     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  29     *     name may not be used to endorse or promote products derived
  30     *     from this software without the prior written permission of
  31     *     Broadcom Corporation.
  32     *
  33     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  34     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  35     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  37     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  38     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  39     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  41     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  42     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  43     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  44     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  45     *     THE POSSIBILITY OF SUCH DAMAGE.
  46     ********************************************************************* */
  47
  48 #ifndef _SB_MIPS_H
  49 #define _SB_MIPS_H
  50
  51 /*  *********************************************************************
  52     *  Configure language
  53     ********************************************************************* */
  54
  55 #if defined(__ASSEMBLER__)
  56 #define _ATYPE_
  57 #define _ATYPE32_
  58 #define _ATYPE64_
  59 #else
  60 #define _ATYPE_         (__SIZE_TYPE__)
  61 #define _ATYPE32_       (int)
  62 #define _ATYPE64_       (long long)
  63 #endif
  64
  65
  66 /*  *********************************************************************
  67     *  Bitfield macros
  68     ********************************************************************* */
  69
  70 /*
  71  * Make a mask for 1 bit at position 'n'
  72  */
  73
  74 #define _MM_MAKEMASK1(n) (1 << (n))
  75
  76 /*
  77  * Make a mask for 'v' bits at position 'n'
  78  */
  79
  80 #define _MM_MAKEMASK(v,n) (((1<<(v))-1) << (n))
  81
  82 /*
  83  * Make a value at 'v' at bit position 'n'
  84  */
  85
  86 #define _MM_MAKEVALUE(v,n) ((v) << (n))
  87
  88 /*
  89  * Retrieve a value from 'v' at bit position 'n' with 'm' mask bits
  90  */
  91
  92 #define _MM_GETVALUE(v,n,m) (((v) & (m)) >> (n))
  93
  94
  95
  96 /*  *********************************************************************
  97     *  32-bit MIPS Address Spaces
  98     ********************************************************************* */
  99
 100 #ifdef __ASSEMBLER__
 101
 102 #ifdef __mips64             /* If 64-bit GPRs, need to sign extend.  */
 103 #define _ACAST32_       0xffffffff00000000 |
 104 #else
 105 #define _ACAST32_
 106 #endif /* __mips64  */
 107 #define _ACAST64_
 108
 109 #else
 110
 111 #define _ACAST32_       _ATYPE_ _ATYPE32_       /* widen if necessary */
 112 #define _ACAST64_               _ATYPE64_       /* do _not_ narrow */
 113
 114 #endif
 115
 116 /* 32-bit address map */
 117 #define UBASE           0x00000000              /* user+ mapped */
 118 #define USIZE           0x80000000
 119 #define K0BASE          (_ACAST32_ 0x80000000)  /* kernel unmapped cached */
 120 #define K0SIZE          0x20000000
 121 #define K1BASE          (_ACAST32_ 0xa0000000)  /* kernel unmapped uncached */
 122 #define K1SIZE          0x20000000
 123 #define KSBASE          (_ACAST32_ 0xc0000000)  /* supervisor+ mapped */
 124 #define KSSIZE          0x20000000
 125 #define K3BASE          (_ACAST32_ 0xe0000000)  /* kernel mapped */
 126 #define K3SIZE          0x20000000
 127
 128 /* 64-bit address map additions to the above (sign-extended) ranges */
 129 #define XUBASE          (_ACAST64_ 0x0000000080000000)  /* user+ mapped */
 130 #define XUSIZE          (_ACAST64_ 0x00000FFF80000000)
 131 #define XSSEGBASE       (_ACAST64_ 0x4000000000000000)  /* supervisor+ mapped */
 132 #define XSSEGSIZE       (_ACAST64_ 0x0000100000000000)
 133 #define XKPHYSBASE      (_ACAST64_ 0x8000000000000000)  /* kernel unmapped */
 134 #define XKPHYSSIZE      (_ACAST64_ 0x0000100000000000)
 135 #define XKSEGBASE       (_ACAST64_ 0xC000000000000000)  /* kernel mapped */
 136 #define XKSEGSIZE       (_ACAST64_ 0x00000FFF80000000)
 137
 138 #define GEN_VECT        (_ACAST32_ 0x80000080)
 139 #define UTLB_VECT       (_ACAST32_ 0x80000000)
 140
 141 /*  *********************************************************************
 142     *  Address space coercion macros
 143     ********************************************************************* */
 144
 145 #define PHYS_TO_K0(pa)  (K0BASE | (pa))
 146 #define PHYS_TO_K1(pa)  (K1BASE | (pa))
 147 #define K0_TO_PHYS(va)  ((va) & (K0SIZE-1))
 148 #define K1_TO_PHYS(va)  ((va) & (K1SIZE-1))
 149 #define K0_TO_K1(va)    ((va) | K1SIZE)
 150 #define K1_TO_K0(va)    ((va) & ~K1SIZE)
 151
 152 #define PHYS_TO_XK1(p) (_ACAST64_ (0xffffffffa0000000 | (p)))
 153 #define XK1_TO_PHYS(p) ((p) & (K1SIZE-1))
 154 #define PHYS_TO_XKPHYS(cca,p) (_SB_MAKEMASK1(63) | (_SB_MAKE64(cca) << 59) | (p))
 155 #define PHYS_TO_XKSEG_UNCACHED(p)  PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
 156 #define PHYS_TO_XKSEG_CACHED(p)    PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
 157 #define XKPHYS_TO_PHYS(p) ((p) & _SB_MAKEMASK(0,59))
 158
 159
 160 #if !defined(__ASSEMBLER__)
 161 #define mips_wbflush()  __asm__ __volatile__ ("sync" : : : "memory")
 162 #define ISK0SEG(va)     ((va) >= K0BASE && (va) <= (K0BASE + K0SIZE - 1))
 163 #define ISK1SEG(va)     ((va) >= K1BASE && (va) <= (K1BASE + K1SIZE - 1))
 164 #endif
 165
 166 /*  *********************************************************************
 167     *  Register aliases
 168     ********************************************************************* */
 169
 170 #if defined(__ASSEMBLER__)
 171 #define zero            $0
 172 #define AT              $1              /* assembler temporaries */
 173 #define v0              $2              /* value holders */
 174 #define v1              $3
 175 #define a0              $4              /* arguments */
 176 #define a1              $5
 177 #define a2              $6
 178 #define a3              $7
 179 #define t0              $8              /* temporaries */
 180 #define t1              $9
 181 #define t2              $10
 182 #define t3              $11
 183 #define t4              $12
 184 #define t5              $13
 185 #define t6              $14
 186 #define t7              $15
 187 #define ta0             $12
 188 #define ta1             $13
 189 #define ta2             $14
 190 #define ta3             $15
 191 #define s0              $16             /* saved registers */
 192 #define s1              $17
 193 #define s2              $18
 194 #define s3              $19
 195 #define s4              $20
 196 #define s5              $21
 197 #define s6              $22
 198 #define s7              $23
 199 #define t8              $24             /* temporaries */
 200 #define t9              $25
 201 #define k0              $26             /* kernel registers */
 202 #define k1              $27
 203 #define gp              $28             /* global pointer */
 204 #define sp              $29             /* stack pointer */
 205 #define s8              $30             /* saved register */
 206 #define fp              $30             /* frame pointer */
 207 #define ra              $31             /* return address */
 208 #endif
 209
 210 /*  *********************************************************************
 211     *  CP0 Registers
 212     ********************************************************************* */
 213
 214 #if defined(__ASSEMBLER__)
 215 #define C0_INX          $0              /* CP0: TLB Index */
 216 #define C0_RAND         $1              /* CP0: TLB Random */
 217 #define C0_TLBLO0       $2              /* CP0: TLB EntryLo0 */
 218 #define C0_TLBLO        C0_TLBLO0       /* CP0: TLB EntryLo0 */
 219 #define C0_TLBLO1       $3              /* CP0: TLB EntryLo1 */
 220 #define C0_CTEXT        $4              /* CP0: Context */
 221 #define C0_PGMASK       $5              /* CP0: TLB PageMask */
 222 #define C0_WIRED        $6              /* CP0: TLB Wired */
 223 #define C0_BADVADDR     $8              /* CP0: Bad Virtual Address */
 224 #define C0_COUNT        $9              /* CP0: Count */
 225 #define C0_TLBHI        $10             /* CP0: TLB EntryHi */
 226 #define C0_COMPARE      $11             /* CP0: Compare */
 227 #define C0_SR           $12             /* CP0: Processor Status */
 228 #define C0_CAUSE        $13             /* CP0: Exception Cause */
 229 #define C0_EPC          $14             /* CP0: Exception PC */
 230 #define C0_PRID         $15             /* CP0: Processor Revision Indentifier */
 231 #define C0_CONFIG       $16             /* CP0: Config */
 232 #define C0_LLADDR       $17             /* CP0: LLAddr */
 233 #define C0_WATCHLO      $18             /* CP0: WatchpointLo */
 234 #define C0_WATCHHI      $19             /* CP0: WatchpointHi */
 235 #define C0_XCTEXT       $20             /* CP0: XContext */
 236 #define C0_DEBUG        $23             /* CP0: debug */
 237 #define C0_DEPC         $24             /* CP0: depc */
 238 #define C0_PERFCONT     $25             /* CP0: Performance counters */
 239 #define C0_ECC          $26             /* CP0: ECC */
 240 #define C0_CACHEERR     $27             /* CP0: CacheErr */
 241 #define C0_TAGLO        $28             /* CP0: TagLo */
 242 #define C0_TAGHI        $29             /* CP0: TagHi */
 243 #define C0_ERREPC       $30             /* CP0: ErrorEPC */
 244 #define C0_DESAVE       $31             /* CP0: JTAG debug exception
 245                                            save register */
 246
 247 #else
 248
 249 #define C0_INX          0               /* CP0: TLB Index */
 250 #define C0_RAND         1               /* CP0: TLB Random */
 251 #define C0_TLBLO0       2               /* CP0: TLB EntryLo0 */
 252 #define C0_TLBLO        C0_TLBLO0       /* CP0: TLB EntryLo0 */
 253 #define C0_TLBLO1       3               /* CP0: TLB EntryLo1 */
 254 #define C0_CTEXT        4               /* CP0: Context */
 255 #define C0_PGMASK       5               /* CP0: TLB PageMask */
 256 #define C0_WIRED        6               /* CP0: TLB Wired */
 257 #define C0_BADVADDR     8               /* CP0: Bad Virtual Address */
 258 #define C0_COUNT        9               /* CP0: Count */
 259 #define C0_TLBHI        10              /* CP0: TLB EntryHi */
 260 #define C0_COMPARE      11              /* CP0: Compare */
 261 #define C0_SR           12              /* CP0: Processor Status */
 262 #define C0_CAUSE        13              /* CP0: Exception Cause */
 263 #define C0_EPC          14              /* CP0: Exception PC */
 264 #define C0_PRID         15              /* CP0: Processor Revision Indentifier */
 265 #define C0_CONFIG       16              /* CP0: Config */
 266 #define C0_LLADDR       17              /* CP0: LLAddr */
 267 #define C0_WATCHLO      18              /* CP0: WatchpointLo */
 268 #define C0_WATCHHI      19              /* CP0: WatchpointHi */
 269 #define C0_XCTEXT       20              /* CP0: XContext */
 270 #define C0_DEBUG        23              /* CP0: debug */
 271 #define C0_DEPC         24              /* CP0: depc */
 272 #define C0_PERFCONT     25              /* CP0: Performance counters */
 273 #define C0_ECC          26              /* CP0: ECC */
 274 #define C0_CACHEERR     27              /* CP0: CacheErr */
 275 #define C0_TAGLO        28              /* CP0: TagLo */
 276 #define C0_TAGHI        29              /* CP0: TagHi */
 277 #define C0_ERREPC       30              /* CP0: ErrorEPC */
 278 #define C0_DESAVE       31              /* CP0: JTAG debug exception
 279                                            save register */
 280
 281 #endif
 282
 283 /* Aliases to match MIPS manuals.  */
 284 #define C0_INDEX        C0_INX
 285 #define C0_RANDOM       C0_RAND
 286 #define C0_ENTRYLO0     C0_TLBLO0
 287 #define C0_ENTRYLO1     C0_TLBLO1
 288 #define C0_CONTEXT      C0_CTEXT
 289 #define C0_PAGEMASK     C0_PGMASK
 290 #define C0_ENTRYHI      C0_TLBHI
 291 #define C0_STATUS       C0_SR
 292 #define C0_XCONTEXT     C0_XCTEXT
 293 #define C0_PERFCNT      C0_PERFCONT
 294 #define C0_ERRCTL       C0_ECC
 295 #define C0_ERROREPC     C0_ERREPC
 296
 297 #ifndef __LANGUAGE_ASSEMBLY
 298
 299 /* Functions to get/set all CP0 registers via inline asms.
 300    Note that the functions which access 64-bit CP0 register are
 301    only provided if __mips64 is defined (i.e., if compiling with
 302    "-mips3", "-mips4", or "-mips64".
 303
 304    The functions are of the form:
 305      cp0_get_<name>
 306      cp0_set_<name>
 307    where <name> is the register name as it appears in MIPS
 308    architecture manuals.
 309
 310    For example, the functions
 311      cp0_get_index
 312      cp0_set_index
 313    get and set the CP0 Index register.  */
 314
 315 #define _cp0_get_reg(name, num, sel, type, d)                         \
 316   static inline type                                                  \
 317   cp0_get_ ## name (void)                                             \
 318   {                                                                   \
 319     type val;                                                         \
 320     __asm__ __volatile__ (".set push;"                                \
 321                           ".set mips64;"                              \
 322                           d "mfc0 %0, $%1, %2;"                       \
 323                           ".set pop;"                                 \
 324                           : "=r"(val) : "i"(num), "i"(sel));          \
 325     return val;                                                       \
 326   }
 327
 328 #define _cp0_set_reg(name, num, sel, type, d)                         \
 329   static inline void                                                  \
 330   cp0_set_ ## name (type val)                                         \
 331   {                                                                   \
 332     __asm__ __volatile__ (".set push;"                                \
 333                           ".set mips64;"                              \
 334                           d "mtc0 %0, $%1, %2;"                       \
 335                           ".set pop;"                                 \
 336                           : : "r"(val), "i"(num), "i"(sel));          \
 337   }
 338
 339 /* Get and set 32-bit CP0 registers which are treated as unsigned values.  */
 340 #define _cp0_get_reg_u32(name, num, sel) \
 341   _cp0_get_reg (name, (num), (sel), unsigned int, "")
 342 #define _cp0_set_reg_u32(name, num, sel) \
 343   _cp0_set_reg (name, (num), (sel), unsigned int, "")
 344
 345 /* Get and set 32-bit CP0 registers which are treated as signed values
 346    so the high bit can be tested easily.  */
 347 #define _cp0_get_reg_s32(name, num, sel) \
 348   _cp0_get_reg (name, (num), (sel), int, "")
 349 #define _cp0_set_reg_s32(name, num, sel) \
 350   _cp0_set_reg (name, (num), (sel), int, "")
 351
 352 #if defined(__mips64)
 353 /* Get and set 64-bit CP0 registers which are treated as unsigned values.
 354    Note that these functions are only provided if compiling for with
 355    64-bit GPRs.  */
 356 #define _cp0_get_reg_u64(name, num, sel) \
 357   _cp0_get_reg (name, (num), (sel), unsigned long long, "d")
 358 #define _cp0_set_reg_u64(name, num, sel) \
 359   _cp0_set_reg (name, (num), (sel), unsigned long long, "d")
 360 #else
 361 #define _cp0_get_reg_u64(name, num, sel)
 362 #define _cp0_set_reg_u64(name, num, sel)
 363 #endif
 364
 365 /* CP0 register 0: index. */
 366 _cp0_get_reg_s32 (index, C0_INDEX, 0)
 367 _cp0_set_reg_s32 (index, C0_INDEX, 0)
 368
 369 /* CP0 register 1: random. */
 370 _cp0_get_reg_u32 (random, C0_RANDOM, 0)
 371
 372 /* CP0 register 2: entrylo0. */
 373 _cp0_get_reg_u64 (entrylo0, C0_ENTRYLO0, 0)
 374 _cp0_set_reg_u64 (entrylo0, C0_ENTRYLO0, 0)
 375
 376 /* CP0 register 3: entrylo1. */
 377 _cp0_get_reg_u64 (entrylo1, C0_ENTRYLO1, 0)
 378 _cp0_set_reg_u64 (entrylo1, C0_ENTRYLO1, 0)
 379
 380 /* CP0 register 4: context. */
 381 _cp0_get_reg_u64 (context, C0_CONTEXT, 0)
 382 _cp0_set_reg_u64 (context, C0_CONTEXT, 0)
 383
 384 /* CP0 register 5: pagemask. */
 385 _cp0_get_reg_u32 (pagemask, C0_PAGEMASK, 0)
 386 _cp0_set_reg_u32 (pagemask, C0_PAGEMASK, 0)
 387
 388 /* CP0 register 6: wired. */
 389 _cp0_get_reg_u32 (wired, C0_WIRED, 0)
 390 _cp0_set_reg_u32 (wired, C0_WIRED, 0)
 391
 392 /* CP0 register 7: reserved. */
 393
 394 /* CP0 register 8: badvaddr. */
 395 _cp0_get_reg_u64 (badvaddr, C0_BADVADDR, 0)
 396
 397 /* CP0 register 9: count. */
 398 _cp0_get_reg_u32 (count, C0_COUNT, 0)
 399 _cp0_set_reg_u32 (count, C0_COUNT, 0)
 400
 401 /* CP0 register 10: entryhi. */
 402 _cp0_get_reg_u64 (entryhi, C0_ENTRYHI, 0)
 403 _cp0_set_reg_u64 (entryhi, C0_ENTRYHI, 0)
 404
 405 /* CP0 register 11: compare. */
 406 _cp0_get_reg_u32 (compare, C0_COMPARE, 0)
 407 _cp0_set_reg_u32 (compare, C0_COMPARE, 0)
 408
 409 /* CP0 register 12: status. */
 410 _cp0_get_reg_u32 (status, C0_STATUS, 0)
 411 _cp0_set_reg_u32 (status, C0_STATUS, 0)
 412
 413 /* CP0 register 13: cause. */
 414 _cp0_get_reg_u32 (cause, C0_CAUSE, 0)
 415 _cp0_set_reg_u32 (cause, C0_CAUSE, 0)
 416
 417 /* CP0 register 14: epc. */
 418 _cp0_get_reg_u64 (epc, C0_EPC, 0)
 419 _cp0_set_reg_u64 (epc, C0_EPC, 0)
 420
 421 /* CP0 register 15: prid. */
 422 _cp0_get_reg_u32 (prid, C0_PRID, 0)
 423
 424 /* CP0 register 16: config. */
 425 _cp0_get_reg_u32 (config, C0_CONFIG, 0)
 426 _cp0_set_reg_u32 (config, C0_CONFIG, 0)
 427
 428 /* CP0 register 16 sel 1: config1. */
 429 _cp0_get_reg_u32 (config1, C0_CONFIG, 1)
 430
 431 /* CP0 register 16 sel 2: config2. */
 432 _cp0_get_reg_u32 (config2, C0_CONFIG, 2)
 433
 434 /* CP0 register 16 sel 3: config3. */
 435 _cp0_get_reg_u32 (config3, C0_CONFIG, 3)
 436
 437 /* CP0 register 17: lladdr. */
 438 _cp0_get_reg_u64 (lladdr, C0_LLADDR, 0)
 439
 440 /* CP0 register 18: watchlo. */
 441 _cp0_get_reg_u64 (watchlo, C0_WATCHLO, 0)
 442 _cp0_set_reg_u64 (watchlo, C0_WATCHLO, 0)
 443
 444 /* CP0 register 18 sel 1: watchlo1. */
 445 _cp0_get_reg_u64 (watchlo1, C0_WATCHLO, 1)
 446 _cp0_set_reg_u64 (watchlo1, C0_WATCHLO, 1)
 447
 448 /* CP0 register 19: watchhi. */
 449 _cp0_get_reg_u32 (watchhi, C0_WATCHHI, 0)
 450 _cp0_set_reg_u32 (watchhi, C0_WATCHHI, 0)
 451
 452 /* CP0 register 19 sel 1: watchhi1. */
 453 _cp0_get_reg_u32 (watchhi1, C0_WATCHHI, 1)
 454 _cp0_set_reg_u32 (watchhi1, C0_WATCHHI, 1)
 455
 456 /* CP0 register 20: xcontext. */
 457 _cp0_get_reg_u64 (xcontext, C0_XCONTEXT, 0)
 458 _cp0_set_reg_u64 (xcontext, C0_XCONTEXT, 0)
 459
 460 /* CP0 register 21: reserved. */
 461
 462 /* CP0 register 22: implementation dependent use. */
 463
 464 /* CP0 register 23: debug. */
 465 _cp0_get_reg_u32 (debug, C0_DEBUG, 0)
 466 _cp0_set_reg_u32 (debug, C0_DEBUG, 0)
 467 /* CP0 register 23 sel 3: edebug. */
 468 _cp0_get_reg_u32 (edebug, C0_DEBUG, 3)
 469 _cp0_set_reg_u32 (edebug, C0_DEBUG, 3)
 470
 471 /* CP0 register 24: depc. */
 472 _cp0_get_reg_u64 (depc, C0_DEPC, 0)
 473 _cp0_set_reg_u64 (depc, C0_DEPC, 0)
 474
 475 /* CP0 register 25: perfcnt. */
 476 _cp0_get_reg_u32 (perfcnt, C0_PERFCNT, 0)
 477 _cp0_set_reg_u32 (perfcnt, C0_PERFCNT, 0)
 478
 479 /* CP0 register 25 sel 1: perfcnt1. */
 480 _cp0_get_reg_u32 (perfcnt1, C0_PERFCNT, 1)
 481 _cp0_set_reg_u32 (perfcnt1, C0_PERFCNT, 1)
 482
 483 /* CP0 register 25 sel 2: perfcnt2. */
 484 _cp0_get_reg_u32 (perfcnt2, C0_PERFCNT, 2)
 485 _cp0_set_reg_u32 (perfcnt2, C0_PERFCNT, 2)
 486
 487 /* CP0 register 25 sel 3: perfcnt3. */
 488 _cp0_get_reg_u32 (perfcnt3, C0_PERFCNT, 3)
 489 _cp0_set_reg_u32 (perfcnt3, C0_PERFCNT, 3)
 490
 491 /* CP0 register 25 sel 4: perfcnt4. */
 492 _cp0_get_reg_u32 (perfcnt4, C0_PERFCNT, 4)
 493 _cp0_set_reg_u32 (perfcnt4, C0_PERFCNT, 4)
 494
 495 /* CP0 register 25 sel 5: perfcnt5. */
 496 _cp0_get_reg_u32 (perfcnt5, C0_PERFCNT, 5)
 497 _cp0_set_reg_u32 (perfcnt5, C0_PERFCNT, 5)
 498
 499 /* CP0 register 25 sel 6: perfcnt6. */
 500 _cp0_get_reg_u32 (perfcnt6, C0_PERFCNT, 6)
 501 _cp0_set_reg_u32 (perfcnt6, C0_PERFCNT, 6)
 502
 503 /* CP0 register 25 sel 7: perfcnt7. */
 504 _cp0_get_reg_u32 (perfcnt7, C0_PERFCNT, 7)
 505 _cp0_set_reg_u32 (perfcnt7, C0_PERFCNT, 7)
 506
 507 /* CP0 register 26: errctl. */
 508 _cp0_get_reg_u32 (errctl, C0_ERRCTL, 0)
 509 _cp0_get_reg_u32 (buserr_pa, C0_ERRCTL, 1)
 510
 511 /* CP0 register 27: cacheerr_i. */
 512 _cp0_get_reg_u32 (cacheerr_i, C0_CACHEERR, 0)
 513
 514 /* CP0 register 27 sel 1: cacheerr_d. */
 515 _cp0_get_reg_u32 (cacheerr_d, C0_CACHEERR, 1)
 516
 517 /* CP0 register 27 sel 3: cacheerr_d_pa. */
 518 _cp0_get_reg_u32 (cacheerr_d_pa, C0_CACHEERR, 3)
 519
 520 /* CP0 register 28: taglo_i. */
 521 _cp0_get_reg_u64 (taglo_i, C0_TAGLO, 0)
 522 _cp0_set_reg_u64 (taglo_i, C0_TAGLO, 0)
 523
 524 /* CP0 register 28 sel 1: datalo_i. */
 525 _cp0_get_reg_u64 (datalo_i, C0_TAGLO, 1)
 526
 527 /* CP0 register 28 sel 2: taglo_d. */
 528 _cp0_get_reg_u64 (taglo_d, C0_TAGLO, 2)
 529 _cp0_set_reg_u64 (taglo_d, C0_TAGLO, 2)
 530
 531 /* CP0 register 28 sel 3: datalo_d. */
 532 _cp0_get_reg_u64 (datalo_d, C0_TAGLO, 3)
 533
 534 /* CP0 register 29: taghi_i. */
 535 _cp0_get_reg_u64 (taghi_i, C0_TAGHI, 0)
 536 _cp0_set_reg_u64 (taghi_i, C0_TAGHI, 0)
 537
 538 /* CP0 register 29 sel 1: datahi_i. */
 539 _cp0_get_reg_u64 (datahi_i, C0_TAGHI, 1)
 540
 541 /* CP0 register 29 sel 2: taghi_d. */
 542 _cp0_get_reg_u64 (taghi_d, C0_TAGHI, 2)
 543 _cp0_set_reg_u64 (taghi_d, C0_TAGHI, 2)
 544
 545 /* CP0 register 29 sel 3: datahi_d. */
 546 _cp0_get_reg_u64 (datahi_d, C0_TAGHI, 3)
 547
 548 /* CP0 register 30: errorepc. */
 549 _cp0_get_reg_u64 (errorepc, C0_ERROREPC, 0)
 550 _cp0_set_reg_u64 (errorepc, C0_ERROREPC, 0)
 551
 552 /* CP0 register 31: desave. */
 553 _cp0_get_reg_u64 (desave, C0_DESAVE, 0)
 554 _cp0_set_reg_u64 (desave, C0_DESAVE, 0)
 555
 556 #endif /* __LANGUAGE_ASSEMBLY */
 557
 558 /*  *********************************************************************
 559     *  CP1 (floating point) control registers
 560     ********************************************************************* */
 561
 562 #define FPA_IRR         0               /* CP1: Implementation/Revision */
 563 #define FPA_CSR         31              /* CP1: Control/Status */
 564
 565 /*  *********************************************************************
 566     *  Macros for generating assembly language routines
 567     ********************************************************************* */
 568
 569 #if defined(__ASSEMBLER__)
 570
 571 /* global leaf function (does not call other functions) */
 572 #define LEAF(name)              \
 573         .globl  name;           \
 574         .ent    name;           \
 575 name:
 576
 577 /* global alternate entry to (local or global) leaf function */
 578 #define XLEAF(name)             \
 579         .globl  name;           \
 580         .aent   name;           \
 581 name:
 582
 583 /* end of a global function */
 584 #define END(name)               \
 585         .size   name,.-name;    \
 586         .end    name
 587
 588 /* local leaf function (does not call other functions) */
 589 #define SLEAF(name)             \
 590         .ent    name;           \
 591 name:
 592
 593 /* local alternate entry to (local or global) leaf function */
 594 #define SXLEAF(name)            \
 595         .aent   name;           \
 596 name:
 597
 598 /* end of a local function */
 599 #define SEND(name)              \
 600         END(name)
 601
 602 /* define & export a symbol */
 603 #define EXPORT(name)            \
 604         .globl name;            \
 605 name:
 606
 607 /* import a symbol */
 608 #define IMPORT(name, size)      \
 609         .extern name,size
 610
 611 /* define a zero-fill common block (BSS if not overridden) with a global name */
 612 #define COMM(name,size)         \
 613         .comm   name,size
 614
 615 /* define a zero-fill common block (BSS if not overridden) with a local name */
 616 #define LCOMM(name,size)                \
 617         .lcomm  name,size
 618
 619 #endif
 620
 621
 622 /* Floating-Point Control register bits */
 623 #define CSR_C           0x00800000
 624 #define CSR_EXC         0x0003f000
 625 #define CSR_EE          0x00020000
 626 #define CSR_EV          0x00010000
 627 #define CSR_EZ          0x00008000
 628 #define CSR_EO          0x00004000
 629 #define CSR_EU          0x00002000
 630 #define CSR_EI          0x00001000
 631 #define CSR_TV          0x00000800
 632 #define CSR_TZ          0x00000400
 633 #define CSR_TO          0x00000200
 634 #define CSR_TU          0x00000100
 635 #define CSR_TI          0x00000080
 636 #define CSR_SV          0x00000040
 637 #define CSR_SZ          0x00000020
 638 #define CSR_SO          0x00000010
 639 #define CSR_SU          0x00000008
 640 #define CSR_SI          0x00000004
 641 #define CSR_RM          0x00000003
 642
 643 /* Status Register */
 644
 645 #define S_SR_CUMASK     28                              /* coprocessor usable bits */
 646 #define M_SR_CUMASK     _MM_MAKEMASK(4,S_SR_CUMASK)
 647 #define G_SR_CUMASK(x)  _MM_GETVALUE(x,S_SR_CUMASK,M_SR_CUMASK)
 648
 649 #define M_SR_CU3        _MM_MAKEMASK1(31)       /* coprocessor 3 usable */
 650 #define M_SR_CU2        _MM_MAKEMASK1(30)       /* coprocessor 2 usable */
 651 #define M_SR_CU1        _MM_MAKEMASK1(29)       /* coprocessor 1 usable */
 652 #define M_SR_CU0        _MM_MAKEMASK1(28)       /* coprocessor 0 usable */
 653
 654 #define S_SR_RP         27                      /* reduced power mode */
 655 #define M_SR_RP         _MM_MAKEMASK1(27)       /* reduced power mode */
 656 #define G_SR_RP(x)      _MM_GETVALUE(x,S_SR_RP,M_SR_RP)
 657
 658 #define S_SR_FR         26                      /* fpu regs any data */
 659 #define M_SR_FR         _MM_MAKEMASK1(26)       /* fpu regs any data */
 660 #define G_SR_FR(x)      _MM_GETVALUE(x,S_SR_FR,M_SR_FR)
 661
 662 #define S_SR_RE         25                      /* reverse endian */
 663 #define M_SR_RE         _MM_MAKEMASK1(25)       /* reverse endian */
 664 #define G_SR_RE(x)      _MM_GETVALUE(x,S_SR_RE,M_SR_RE)
 665
 666 #define S_SR_MX         24                      /* MDMX */
 667 #define M_SR_MX         _MM_MAKEMASK1(24)       /* MDMX */
 668 #define G_SR_MX(x)      _MM_GETVALUE(x,S_SR_MX,M_SR_MX)
 669
 670 #define S_SR_PX         23                      /* 64-bit ops in user mode */
 671 #define M_SR_PX         _MM_MAKEMASK1(23)       /* 64-bit ops in user mode */
 672 #define G_SR_PX(x)      _MM_GETVALUE(x,S_SR_PX,M_SR_PX)
 673
 674 #define S_SR_BEV        22                      /* boot exception vectors */
 675 #define M_SR_BEV        _MM_MAKEMASK1(22)       /* boot exception vectors */
 676 #define G_SR_BEV(x)     _MM_GETVALUE(x,S_SR_BEV,M_SR_BEV)
 677
 678 #define S_SR_TS         21                      /* TLB is shut down */
 679 #define M_SR_TS         _MM_MAKEMASK1(21)       /* TLB is shut down */
 680 #define G_SR_TS(x)      _MM_GETVALUE(x,S_SR_TS,M_SR_TS)
 681
 682 #define S_SR_SR         20                      /* soft reset */
 683 #define M_SR_SR         _MM_MAKEMASK1(20)       /* soft reset */
 684 #define G_SR_SR(x)      _MM_GETVALUE(x,S_SR_SR,M_SR_SR)
 685
 686 #define S_SR_NMI        19                      /* nonmaskable interrupt */
 687 #define M_SR_NMI        _MM_MAKEMASK1(19)       /* nonmaskable interrupt */
 688 #define G_SR_NMI(x)     _MM_GETVALUE(x,S_SR_NMI,M_SR_NMI)
 689
 690 #define S_SR_IMASK      8                       /* all interrupt mask bits */
 691 #define M_SR_IMASK      _MM_MAKEMASK(8,8)       /* all interrupt mask bits */
 692 #define G_SR_IMASK(x)   _MM_GETVALUE(x,S_SR_IMASK,M_SR_IMASK)
 693
 694 #define M_SR_IBIT8      _MM_MAKEMASK1(15)       /* individual bits */
 695 #define M_SR_IBIT7      _MM_MAKEMASK1(14)
 696 #define M_SR_IBIT6      _MM_MAKEMASK1(13)
 697 #define M_SR_IBIT5      _MM_MAKEMASK1(12)
 698 #define M_SR_IBIT4      _MM_MAKEMASK1(11)
 699 #define M_SR_IBIT3      _MM_MAKEMASK1(10)
 700 #define M_SR_IBIT2      _MM_MAKEMASK1(9)
 701 #define M_SR_IBIT1      _MM_MAKEMASK1(8)
 702
 703 #define M_SR_IMASK8     0                       /* masks for nested int levels */
 704 #define M_SR_IMASK7     _MM_MAKEMASK(1,15)
 705 #define M_SR_IMASK6     _MM_MAKEMASK(2,14)
 706 #define M_SR_IMASK5     _MM_MAKEMASK(3,13)
 707 #define M_SR_IMASK4     _MM_MAKEMASK(4,12)
 708 #define M_SR_IMASK3     _MM_MAKEMASK(5,11)
 709 #define M_SR_IMASK2     _MM_MAKEMASK(6,10)
 710 #define M_SR_IMASK1     _MM_MAKEMASK(7,9)
 711 #define M_SR_IMASK0     _MM_MAKEMASK(8,8)
 712
 713 #define S_SR_KX         7                       /* 64-bit access for kernel */
 714 #define M_SR_KX         _MM_MAKEMASK1(7)        /* 64-bit access for kernel */
 715 #define G_SR_KX(x)      _MM_GETVALUE(x,S_SR_KX,M_SR_KX)
 716
 717 #define S_SR_SX         6                       /* .. for supervisor */
 718 #define M_SR_SX         _MM_MAKEMASK1(6)        /* .. for supervisor */
 719 #define G_SR_SX(x)      _MM_GETVALUE(x,S_SR_SX,M_SR_SX)
 720
 721 #define S_SR_UX         5                       /* .. for user */
 722 #define M_SR_UX         _MM_MAKEMASK1(5)        /* .. for user */
 723 #define G_SR_UX(x)      _MM_GETVALUE(x,S_SR_UX,M_SR_UX)
 724
 725 #define S_SR_KSU        3                       /* base operating mode mode */
 726 #define M_SR_KSU        _MM_MAKEMASK(2,S_SR_KSU)
 727 #define V_SR_KSU(x)     _MM_MAKEVALUE(x,S_SR_KSU)
 728 #define G_SR_KSU(x)     _MM_GETVALUE(x,S_SR_KSU,M_SR_KSU)
 729 #define K_SR_KSU_KERNEL 0
 730 #define K_SR_KSU_SUPR   1
 731 #define K_SR_KSU_USER   2
 732
 733 #define M_SR_UM         _MM_MAKEMASK1(4)
 734
 735 #define S_SR_ERL        2
 736 #define M_SR_ERL        _MM_MAKEMASK1(2)
 737 #define G_SR_ERL(x)     _MM_GETVALUE(x,S_SR_ERL,M_SR_ERL)
 738
 739 #define S_SR_EXL        1
 740 #define M_SR_EXL        _MM_MAKEMASK1(1)
 741 #define G_SR_EXL(x)     _MM_GETVALUE(x,S_SR_EXL,M_SR_EXL)
 742
 743 #define S_SR_IE         0
 744 #define M_SR_IE         _MM_MAKEMASK1(0)
 745 #define G_SR_IE(x)      _MM_GETVALUE(x,S_SR_IE,M_SR_IE)
 746
 747 /*
 748  * Cause Register
 749  */
 750 #define M_CAUSE_BD      _MM_MAKEMASK1(31) /* exception in BD slot */
 751
 752 #define S_CAUSE_CE      28              /* coprocessor error */
 753 #define M_CAUSE_CE      _MM_MAKEMASK(2,S_CAUSE_CE)
 754 #define V_CAUSE_CE(x)   _MM_MAKEVALUE(x,S_CAUSE_CE)
 755 #define G_CAUSE_CE(x)   _MM_GETVALUE(x,S_CAUSE_CE,M_CAUSE_CE)
 756
 757 #define M_CAUSE_IV      _MM_MAKEMASK1(23) /* special interrupt */
 758 #define M_CAUSE_WP      _MM_MAKEMASK1(22) /* watch interrupt deferred */
 759
 760 #define S_CAUSE_IPMASK  8
 761 #define M_CAUSE_IPMASK  _MM_MAKEMASK(8,S_CAUSE_IPMASK)
 762 #define M_CAUSE_IP8     _MM_MAKEMASK1(15)       /* hardware interrupts */
 763 #define M_CAUSE_IP7     _MM_MAKEMASK1(14)
 764 #define M_CAUSE_IP6     _MM_MAKEMASK1(13)
 765 #define M_CAUSE_IP5     _MM_MAKEMASK1(12)
 766 #define M_CAUSE_IP4     _MM_MAKEMASK1(11)
 767 #define M_CAUSE_IP3     _MM_MAKEMASK1(10)
 768 #define M_CAUSE_SW2     _MM_MAKEMASK1(9)        /* software interrupts */
 769 #define M_CAUSE_SW1     _MM_MAKEMASK1(8)
 770
 771 #define S_CAUSE_EXC     2
 772 #define M_CAUSE_EXC     _MM_MAKEMASK(5,S_CAUSE_EXC)
 773 #define V_CAUSE_EXC(x)  _MM_MAKEVALUE(x,S_CAUSE_EXC)
 774 #define G_CAUSE_EXC(x)  _MM_GETVALUE(x,S_CAUSE_EXC,M_CAUSE_EXC)
 775
 776 /* Exception Code */
 777 #define K_CAUSE_EXC_INT         0       /* External interrupt */
 778 #define K_CAUSE_EXC_MOD         1       /* TLB modification */
 779 #define K_CAUSE_EXC_TLBL        2       /* TLB miss (Load or Ifetch) */
 780 #define K_CAUSE_EXC_TLBS        3       /* TLB miss (Save) */
 781 #define K_CAUSE_EXC_ADEL        4       /* Address error (Load or Ifetch) */
 782 #define K_CAUSE_EXC_ADES        5       /* Address error (Save) */
 783 #define K_CAUSE_EXC_IBE         6       /* Bus error (Ifetch) */
 784 #define K_CAUSE_EXC_DBE         7       /* Bus error (data load or store) */
 785 #define K_CAUSE_EXC_SYS         8       /* System call */
 786 #define K_CAUSE_EXC_BP          9       /* Break point */
 787 #define K_CAUSE_EXC_RI          10      /* Reserved instruction */
 788 #define K_CAUSE_EXC_CPU         11      /* Coprocessor unusable */
 789 #define K_CAUSE_EXC_OVF         12      /* Arithmetic overflow */
 790 #define K_CAUSE_EXC_TRAP        13      /* Trap exception */
 791 #define K_CAUSE_EXC_VCEI        14      /* Virtual Coherency Exception (I) */
 792 #define K_CAUSE_EXC_FPE         15      /* Floating Point Exception */
 793 #define K_CAUSE_EXC_CP2         16      /* Cp2 Exception */
 794 #define K_CAUSE_EXC_WATCH       23      /* Watchpoint exception */
 795 #define K_CAUSE_EXC_VCED        31      /* Virtual Coherency Exception (D) */
 796
 797 #define K_NTLBENTRIES   64
 798
 799 #define HI_HALF(x)      ((x) >> 16)
 800 #define LO_HALF(x)      ((x) & 0xffff)
 801
 802 /* FPU stuff */
 803
 804 #if defined(__ASSEMBLER__)
 805 #define C1_CSR          $31
 806 #define C1_FRID         $0
 807 #else
 808 #define C1_CSR          31
 809 #define C1_FRID         0
 810 #endif
 811
 812 #define S_FCSR_CAUSE    12
 813 #define M_FCSR_CAUSE    _MM_MAKEMASK(5,S_FCSR_CAUSE)
 814 #define V_FCSR_CAUSE(x) _MM_MAKEVALUE(x,S_FCSR_CAUSE)
 815 #define G_FCSR_CAUSE(x) _MM_GETVALUE(x,S_FCSR_CAUSE,M_FCSR_CAUSE)
 816
 817 #define S_FCSR_ENABLES  7
 818 #define M_FCSR_ENABLES  _MM_MAKEMASK(5,S_FCSR_ENABLES)
 819 #define V_FCSR_ENABLES(x) _MM_MAKEVALUE(x,S_FCSR_ENABLES)
 820 #define G_FCSR_ENABLES(x) _MM_GETVALUE(x,S_FCSR_ENABLES,M_FCSR_ENABLES)
 821
 822 #define S_FCSR_FLAGS    2
 823 #define M_FCSR_FLAGS    _MM_MAKEMASK(5,S_FCSR_FLAGS)
 824 #define V_FCSR_FLAGS(x) _MM_MAKEVALUE(x,S_FCSR_FLAGS)
 825 #define G_FCSR_FLAGS(x) _MM_GETVALUE(x,S_FCSR_FLAGS,M_FCSR_FLAGS)
 826
 827
 828 /*
 829  * MIPS64 Config Register (select 0)
 830  */
 831 #define S_CFG_CFG1      31                      /* Config1 */
 832 #define M_CFG_CFG1      _MM_MAKEMASK1(31)       /* config1 select1 is impl */
 833 #define G_CFG_CFG1(x)   _MM_GETVALUE(x,S_CFG_CFG1,M_CFG_CFG1)
 834 #define S_CFG_BE        15                      /* Endian mode */
 835 #define M_CFG_BE        _MM_MAKEMASK1(15)       /* big-endian mode */
 836 #define G_CFG_BE(x)     _MM_GETVALUE(x,S_CFG_BE,M_CFG_BE)
 837
 838 #define S_CFG_MPV       16                      /* Multi proc. vector offset */
 839 #define M_CFG_MPV        _MM_MAKEMASK(4,S_CFG_MPV)
 840 #define V_CFG_MPV(x)    _MM_MAKEVALUE(x,S_CFG_MPV)
 841 #define G_CFG_MPV(x)    _MM_GETVALUE(x,S_CFG_MPV,M_CFG_MPV)
 842
 843 #define S_CFG_AT        13                      /* Architecture Type */
 844 #define M_CFG_AT        _MM_MAKEMASK(2,S_CFG_AT)
 845 #define V_CFG_AT(x)     _MM_MAKEVALUE(x,S_CFG_AT)
 846 #define G_CFG_AT(x)     _MM_GETVALUE(x,S_CFG_AT,M_CFG_AT)
 847 #define K_CFG_AT_MIPS32 0
 848 #define K_CFG_AT_MIPS64_32 1
 849 #define K_CFG_AT_MIPS64 2
 850
 851 #define S_CFG_AR        10                      /* Architecture Revision */
 852 #define M_CFG_AR        _MM_MAKEMASK(3,S_CFG_AR)
 853 #define V_CFG_AR(x)     _MM_MAKEVALUE(x,S_CFG_AR)
 854 #define G_CFG_AR(x)     _MM_GETVALUE(x,S_CFG_AR,M_CFG_AR)
 855 #define K_CFG_AR_REV1   0
 856
 857 #define S_CFG_MMU       7                       /* MMU Type */
 858 #define M_CFG_MMU       _MM_MAKEMASK(3,S_CFG_MMU)
 859 #define V_CFG_MMU(x)    _MM_MAKEVALUE(x,S_CFG_MMU)
 860 #define G_CFG_MMU(x)    _MM_GETVALUE(x,S_CFG_MMU,M_CFG_MMU)
 861 #define K_CFG_MMU_NONE  0
 862 #define K_CFG_MMU_TLB   1
 863 #define K_CFG_MMU_BAT   2
 864 #define K_CFG_MMU_FIXED 3
 865
 866 #define S_CFG_K0COH     0                       /* K0seg coherency */
 867 #define M_CFG_K0COH     _MM_MAKEMASK(3,S_CFG_K0COH)
 868 #define V_CFG_K0COH(x)  _MM_MAKEVALUE(x,S_CFG_K0COH)
 869 #define G_CFG_K0COH(x)  _MM_GETVALUE(x,S_CFG_K0COH,M_CFG_K0COH)
 870 #define K_CFG_K0COH_UNCACHED    2
 871 #define K_CFG_K0COH_CACHEABLE   3
 872 #define K_CFG_K0COH_COHERENT    5
 873
 874 /*
 875  * MIPS64 Config Register (select 1)
 876  */
 877
 878 #define M_CFG_CFG2      _MM_MAKEMASK1(31)       /* config2 select2 is impl */
 879
 880 #define S_CFG_MMUSIZE   25
 881 #define M_CFG_MMUSIZE   _MM_MAKEMASK(6,S_CFG_MMUSIZE)
 882 #define G_CFG_MMUSIZE(x) _MM_GETVALUE(x,S_CFG_MMUSIZE,M_CFG_MMUSIZE)
 883
 884 #define S_CFG_IS        22
 885 #define M_CFG_IS        _MM_MAKEMASK(3,S_CFG_IS)
 886 #define V_CFG_IS(x)     _MM_MAKEVALUE(x,S_CFG_IS)
 887 #define G_CFG_IS(x)     _MM_GETVALUE(x,S_CFG_IS,M_CFG_IS)
 888
 889 #define S_CFG_IL        19
 890 #define M_CFG_IL        _MM_MAKEMASK(3,S_CFG_IL)
 891 #define V_CFG_IL(x)     _MM_MAKEVALUE(x,S_CFG_IL)
 892 #define G_CFG_IL(x)     _MM_GETVALUE(x,S_CFG_IL,M_CFG_IL)
 893
 894 #define S_CFG_IA        16
 895 #define M_CFG_IA        _MM_MAKEMASK(3,S_CFG_IA)
 896 #define V_CFG_IA(x)     _MM_MAKEVALUE(x,S_CFG_IA)
 897 #define G_CFG_IA(x)     _MM_GETVALUE(x,S_CFG_IA,M_CFG_IA)
 898
 899 #define S_CFG_DS        13
 900 #define M_CFG_DS        _MM_MAKEMASK(3,S_CFG_DS)
 901 #define V_CFG_DS(x)     _MM_MAKEVALUE(x,S_CFG_DS)
 902 #define G_CFG_DS(x)     _MM_GETVALUE(x,S_CFG_DS,M_CFG_DS)
 903
 904 #define S_CFG_DL        10
 905 #define M_CFG_DL        _MM_MAKEMASK(3,S_CFG_DL)
 906 #define V_CFG_DL(x)     _MM_MAKEVALUE(x,S_CFG_DL)
 907 #define G_CFG_DL(x)     _MM_GETVALUE(x,S_CFG_DL,M_CFG_DL)
 908
 909 #define S_CFG_DA        7
 910 #define M_CFG_DA        _MM_MAKEMASK(3,S_CFG_DA)
 911 #define V_CFG_DA(x)     _MM_MAKEVALUE(x,S_CFG_DA)
 912 #define G_CFG_DA(x)     _MM_GETVALUE(x,S_CFG_DA,M_CFG_DA)
 913
 914 #define S_CFG_PC        4                       /* perf ctrs present */
 915 #define M_CFG_PC        _MM_MAKEMASK1(4)        /* perf ctrs present */
 916 #define G_CFG_PC(x)     _MM_GETVALUE(x,S_CFG_PC,M_CFG_PC)
 917
 918 #define S_CFG_WR        3                       /* watch regs present */
 919 #define M_CFG_WR        _MM_MAKEMASK1(3)        /* watch regs present */
 920 #define G_CFG_WR(x)     _MM_GETVALUE(x,S_CFG_WR,M_CFG_WR)
 921
 922 #define S_CFG_CA        2                       /* MIPS16 present */
 923 #define M_CFG_CA        _MM_MAKEMASK1(2)        /* MIPS16 present */
 924 #define G_CFG_CA(x)     _MM_GETVALUE(x,S_CFG_CA,M_CFG_CA)
 925
 926 #define S_CFG_EP        1                       /* EJTAG present */
 927 #define M_CFG_EP        _MM_MAKEMASK1(1)        /* EJTAG present */
 928 #define G_CFG_EP(x)     _MM_GETVALUE(x,S_CFG_EP,M_CFG_EP)
 929
 930 #define S_CFG_FP        0                       /* FPU present */
 931 #define M_CFG_FP        _MM_MAKEMASK1(0)        /* FPU present */
 932 #define G_CFG_FP(x)     _MM_GETVALUE(x,S_CFG_FP,M_CFG_FP)
 933
 934
 935
 936 /*
 937  * Primary Cache TagLo
 938  */
 939
 940 #define S_TAGLO_PTAG    8
 941 #define M_TAGLO_PTAG    _MM_MAKEMASK(56,S_TAGLO_PTAG)
 942
 943 #define S_TAGLO_PSTATE  6
 944 #define M_TAGLO_PSTATE  _MM_MAKEMASK(2,S_TAGLO_PSTATE)
 945 #define V_TAGLO_PSTATE(x) _MM_MAKEVALUE(x,S_TAGLO_PSTATE)
 946 #define G_TAGLO_PSTATE(x) _MM_GETVALUE(x,S_TAGLO_PSTATE,M_TAGLO_PSTATE)
 947 #define K_TAGLO_PSTATE_INVAL            0
 948 #define K_TAGLO_PSTATE_SHARED           1
 949 #define K_TAGLO_PSTATE_CLEAN_EXCL       2
 950 #define K_TAGLO_PSTATE_DIRTY_EXCL       3
 951
 952 #define M_TAGLO_LOCK    _MM_MAKEMASK1(5)
 953 #define M_TAGLO_PARITY  _MM_MAKEMASK1(0)
 954
 955
 956 /*
 957  * CP0 CacheErr register
 958  */
 959 #define M_CERR_DATA     _MM_MAKEMASK1(31)       /* err in D space */
 960 #define M_CERR_SCACHE   _MM_MAKEMASK1(30)       /* err in l2, not l1 */
 961 #define M_CERR_DERR     _MM_MAKEMASK1(29)       /* data error */
 962 #define M_CERR_TERR     _MM_MAKEMASK1(28)       /* tag error */
 963 #define M_CERR_EXTRQ    _MM_MAKEMASK1(27)       /* external req caused err */
 964 #define M_CERR_BPAR     _MM_MAKEMASK1(26)       /* bus parity err */
 965 #define M_CERR_ADATA    _MM_MAKEMASK1(25)       /* additional data */
 966 #define M_CERR_IDX      _MM_MAKEMASK(22,0)
 967
 968
 969
 970 /*
 971  * Primary Cache operations
 972  */
 973 #define Index_Invalidate_I               0x0         /* 0       0 */
 974 #define Index_Writeback_Inv_D            0x1         /* 0       1 */
 975 #define Index_Invalidate_SI              0x2         /* 0       2 */
 976 #define Index_Writeback_Inv_SD           0x3         /* 0       3 */
 977 #define Index_Load_Tag_I                 0x4         /* 1       0 */
 978 #define Index_Load_Tag_D                 0x5         /* 1       1 */
 979 #define Index_Load_Tag_SI                0x6         /* 1       2 */
 980 #define Index_Load_Tag_SD                0x7         /* 1       3 */
 981 #define Index_Store_Tag_I                0x8         /* 2       0 */
 982 #define Index_Store_Tag_D                0x9         /* 2       1 */
 983 #define Index_Store_Tag_SI               0xA         /* 2       2 */
 984 #define Index_Store_Tag_SD               0xB         /* 2       3 */
 985 #define Create_Dirty_Exc_D               0xD         /* 3       1 */
 986 #define Create_Dirty_Exc_SD              0xF         /* 3       3 */
 987 #define Hit_Invalidate_I                 0x10        /* 4       0 */
 988 #define Hit_Invalidate_D                 0x11        /* 4       1 */
 989 #define Hit_Invalidate_SI                0x12        /* 4       2 */
 990 #define Hit_Invalidate_SD                0x13        /* 4       3 */
 991 #define Fill_I                           0x14        /* 5       0 */
 992 #define Hit_Writeback_Inv_D              0x15        /* 5       1 */
 993 #define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
 994 #define Hit_Writeback_I                  0x18        /* 6       0 */
 995 #define Hit_Writeback_D                  0x19        /* 6       1 */
 996 #define Hit_Writeback_SD                 0x1B        /* 6       3 */
 997 #define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
 998 #define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
 999
1000 /* Watchpoint Register */
1001 #define M_WATCH_PA              0xfffffff8
1002 #define M_WATCH_R               0x00000002
1003 #define M_WATCH_W               0x00000001
1004
1005
1006 /* TLB entries */
1007 #define S_TLBHI_ASID            0
1008 #define M_TLBHI_ASID            _MM_MAKEMASK(8,S_TLBHI_ASID)
1009 #define V_TLBHI_ASID(x)         _MM_MAKEVALUE(x,S_TLBHI_ASID)
1010 #define G_TLBHI_ASID(x)         _MM_GETVALUE(x,S_TLBLO_ASID,M_TLBLO_ASID)
1011
1012 /* SEGBITS = 44 on sb1 */
1013 #define S_TLBHI_VPN2            13
1014 #define M_TLBHI_VPN2            _MM_MAKEMASK(31,S_TLBHI_VPN2)
1015 #define V_TLBHI_VPN2(x)         _MM_MAKEVALUE(x,S_TLBHI_VPN2)
1016 #define G_TLBHI_VPN2(x)         _MM_GETVALUE(x,S_TLBHI_VPN2,M_TLBHI_VPN2)
1017
1018 #define S_TLBLO_G               0
1019 #define M_TLBLO_G               _MM_MAKEMASK1(S_TLBLO_G)
1020 #define V_TLBLO_G(x)            _MM_MAKEVALUE(x,S_TLBLO_G)
1021 #define G_TLBLO_G(x)            _MM_GETVALUE(x,S_TLBLO_G,M_TLBLO_G)
1022
1023 #define S_TLBLO_V               1
1024 #define M_TLBLO_V               _MM_MAKEMASK1(S_TLBLO_V)
1025 #define V_TLBLO_V(x)            _MM_MAKEVALUE(x,S_TLBLO_V)
1026 #define G_TLBLO_V(x)            _MM_GETVALUE(x,S_TLBLO_V,M_TLBLO_V)
1027
1028 #define S_TLBLO_D               2
1029 #define M_TLBLO_D               _MM_MAKEMASK1(S_TLBLO_D)
1030 #define V_TLBLO_D(x)            _MM_MAKEVALUE(x,S_TLBLO_D)
1031 #define G_TLBLO_D(x)            _MM_GETVALUE(x,S_TLBLO_D,M_TLBLO_D)
1032
1033 #define S_TLBLO_CALG            3
1034 #define M_TLBLO_CALG            _MM_MAKEMASK(3,S_TLBLO_CALG)
1035 #define V_TLBLO_CALG(x)         _MM_MAKEVALUE(x,S_TLBLO_CALG)
1036 #define G_TLBLO_CALG(x)         _MM_GETVALUE(x,S_TLBLO_CALG,M_TLBLO_CALG)
1037
1038 /* PABITS = 40 on sb1 */
1039 #define S_TLBLO_PFNMASK         6
1040 #define M_TLBLO_PFNMASK         _MM_MAKEMASK(28,S_TLBLO_PFNMASK)
1041 #define V_TLBLO_PFNMASK(x)      _MM_MAKEVALUE(x,S_TLBLO_PFNMASK)
1042 #define G_TLBLO_PFNMASK(x)      _MM_GETVALUE(x,S_TLBLO_PFNMASK,M_TLBLO_PFNMASK)
1043
1044 /* support 4KB - 64MB for pass2 and beyond (14bits) */
1045 #define S_TLB_PGMSK             13
1046 #define M_TLB_PGMSK             _MM_MAKEMASK(14,S_TLB_PGMSK)
1047 #define V_TLB_PGMSK(x)          _MM_MAKEVALUE(x,S_TLB_PGMSK)
1048 #define G_TLB_PGMSK(x)          _MM_GETVALUE(x,S_TLB_PGMSK,M_TLB_PGMSK)
1049
1050 #define K_CALG_COH_EXCL1_NOL2   0
1051 #define K_CALG_COH_SHRL1_NOL2   1
1052 #define K_CALG_UNCACHED         2
1053 #define K_CALG_NONCOHERENT      3
1054 #define K_CALG_COH_EXCL         4
1055 #define K_CALG_COH_SHAREABLE    5
1056 #define K_CALG_NOTUSED          6
1057 #define K_CALG_UNCACHED_ACCEL   7
1058
1059
1060
1061 #endif /* _SB_MIPS_H */