release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/sb1250/include/sb1250_pci.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  PCI constants                            File: sb1250_pci.h
   5     *
   6     *  This module contains constants and macros to describe
   7     *  the PCI interface on the SB1250.
   8     *
   9     *  SB1250 specification level:  User's manual 1/02/02
  10     *
  11     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  12     *
  13     *********************************************************************
  14     *
  15     *  Copyright 2000,2001,2002,2003
  16     *  Broadcom Corporation. All rights reserved.
  17     *
  18     *  This software is furnished under license and may be used and
  19     *  copied only in accordance with the following terms and
  20     *  conditions.  Subject to these conditions, you may download,
  21     *  copy, install, use, modify and distribute modified or unmodified
  22     *  copies of this software in source and/or binary form.  No title
  23     *  or ownership is transferred hereby.
  24     *
  25     *  1) Any source code used, modified or distributed must reproduce
  26     *     and retain this copyright notice and list of conditions
  27     *     as they appear in the source file.
  28     *
  29     *  2) No right is granted to use any trade name, trademark, or
  30     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  31     *     name may not be used to endorse or promote products derived
  32     *     from this software without the prior written permission of
  33     *     Broadcom Corporation.
  34     *
  35     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  36     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  37     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  38     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  39     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  40     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  41     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  42     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  43     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  44     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  45     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  46     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  47     *     THE POSSIBILITY OF SUCH DAMAGE.
  48     ********************************************************************* */
  49
  50
  51 #ifndef _SB1250_PCI_H
  52 #define _SB1250_PCI_H
  53
  54 #include "sb1250_defs.h"
  55
  56 #define K_PCI_VENDOR_SIBYTE     0x166D
  57 #define K_PCI_DEVICE_SB1250     0x0001
  58
  59 /*
  60  * PCI Interface Type 0 configuration header
  61  */
  62
  63 #define R_PCI_TYPE0_DEVICEID    0x0000
  64 #define R_PCI_TYPE0_CMDSTATUS   0x0004
  65 #define R_PCI_TYPE0_CLASSREV    0x0008
  66 #define R_PCI_TYPE0_DEVHDR      0x000C
  67 #define R_PCI_TYPE0_BAR0        0x0010  /* translated via mapping table */
  68 #define R_PCI_TYPE0_BAR1        0x0014  /* reserved */
  69 #define R_PCI_TYPE0_BAR2        0x0018  /* mbox 0 */
  70 #define R_PCI_TYPE0_BAR3        0x001C  /* mbox 1 */
  71 #define R_PCI_TYPE0_BAR4        0x0020  /* low memory */
  72 #define R_PCI_TYPE0_BAR5        0x0024  /* high memory */
  73 #define R_PCI_TYPE0_CARDBUSCIS  0x0028
  74 #define R_PCI_TYPE0_SUBSYSID    0x002C
  75 #define R_PCI_TYPE0_ROMBASE     0x0030
  76 #define R_PCI_TYPE0_CAPPTR      0x0034  /* not used */
  77 #define R_PCI_TYPE0_RESERVED1   0x0038
  78 #define R_PCI_TYPE0_INTGRANT    0x003C  /* interrupt pin and grant latency */
  79 #define R_PCI_TYPE0_TIMEOUT     0x0040  /* FControl, Timeout */
  80 #define R_PCI_TYPE0_FCONTROL    0x0040  /* FControl, Timeout */
  81 #define R_PCI_TYPE0_MAPBASE     0x0044  /* 0x44 through 0x80 - map table */
  82 #define PCI_TYPE0_MAPENTRIES    32      /* 64 bytes, 32 entries */
  83 #define R_PCI_TYPE0_ERRORADDR   0x0084
  84 #define R_PCI_TYPE0_ADDSTATUS   0x0088
  85 #define R_PCI_TYPE0_SUBSYSSET   0x008C  /* only accessible from ZBBus */
  86 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
  87 #define R_PCI_TYPE0_READHOST    0x0094  /* Read Host register */
  88 #define R_PCI_TYPE0_ADXTEND     0x0098  /* Adaptive Extend register */
  89 #endif /* 1250 PASS2 || 112x PASS1 */
  90
  91 /*
  92  * PCI Device ID register
  93  */
  94
  95 #define S_PCI_DEVICEID_VENDOR           0
  96 #define M_PCI_DEVICEID_VENDOR           _SB_MAKEMASK_32(16,S_PCI_DEVICEID_VENDOR)
  97 #define V_PCI_DEVICEID_VENDOR(x)        _SB_MAKEVALUE_32(x,S_PCI_DEVICEID_VENDOR)
  98 #define G_PCI_DEVICEID_VENDOR(x)        _SB_GETVALUE_32(x,S_PCI_DEVICEID_VENDOR,M_PCI_DEVICEID_VENDOR)
  99
 100 #define S_PCI_DEVICEID_DEVICEID         16
 101 #define M_PCI_DEVICEID_DEVICEID         _SB_MAKEMASK_32(16,S_PCI_DEVICEID_DEVICEID)
 102 #define V_PCI_DEVICEID_DEVICEID(x)      _SB_MAKEVALUE_32(x,S_PCI_DEVICEID_DEVICEID)
 103 #define G_PCI_DEVICEID_DEVICEID(x)      _SB_GETVALUE_32(x,S_PCI_DEVICEID_DEVICEID,M_PCI_DEVICEID_DEVICEID)
 104
 105
 106 /*
 107  * PCI Command Register (Table 8-4)
 108  */
 109
 110 #define M_PCI_CMD_IOSPACE_EN            _SB_MAKEMASK1_32(0)
 111 #define M_PCI_CMD_MEMSPACE_EN           _SB_MAKEMASK1_32(1)
 112 #define M_PCI_CMD_MASTER_EN             _SB_MAKEMASK1_32(2)
 113 #define M_PCI_CMD_SPECCYC_EN            _SB_MAKEMASK1_32(3)
 114 #define M_PCI_CMD_MEMWRINV_EN           _SB_MAKEMASK1_32(4)
 115 #define M_PCI_CMD_VGAPALSNP_EN          _SB_MAKEMASK1_32(5)
 116 #define M_PCI_CMD_PARERRRESP            _SB_MAKEMASK1_32(6)
 117 #define M_PCI_CMD_STEPCTRL              _SB_MAKEMASK1_32(7)
 118 #define M_PCI_CMD_SERR_EN               _SB_MAKEMASK1_32(8)
 119 #define M_PCI_CMD_FASTB2B_EN            _SB_MAKEMASK1_32(9)
 120
 121 /*
 122  * PCI class and revision registers
 123  */
 124
 125 #define S_PCI_CLASSREV_REV              0
 126 #define M_PCI_CLASSREV_REV              _SB_MAKEMASK_32(8,S_PCI_CLASSREV_REV)
 127 #define V_PCI_CLASSREV_REV(x)           _SB_MAKEVALUE_32(x,S_PCI_CLASSREV_REV)
 128 #define G_PCI_CLASSREV_REV(x)           _SB_GETVALUE_32(x,S_PCI_CLASSREV_REV,M_PCI_CLASSREV_REV)
 129
 130 #define S_PCI_CLASSREV_CLASS            8
 131 #define M_PCI_CLASSREV_CLASS            _SB_MAKEMASK_32(24,S_PCI_CLASSREV_CLASS)
 132 #define V_PCI_CLASSREV_CLASS(x)         _SB_MAKEVALUE_32(x,S_PCI_CLASSREV_CLASS)
 133 #define G_PCI_CLASSREV_CLASS(x)         _SB_GETVALUE_32(x,S_PCI_CLASSREV_CLASS,M_PCI_CLASSREV_CLASS)
 134
 135 #define K_PCI_REV                       0x01
 136 #define K_PCI_CLASS                     0x060000
 137
 138 /*
 139  * Device Header (offset 0x0C)
 140  */
 141
 142 #define S_PCI_DEVHDR_CLINESZ            0
 143 #define M_PCI_DEVHDR_CLINESZ            _SB_MAKEMASK_32(8,S_PCI_DEVHDR_CLINESZ)
 144 #define V_PCI_DEVHDR_CLINESZ(x)         _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_CLINESZ)
 145 #define G_PCI_DEVHDR_CLINESZ(x)         _SB_GETVALUE_32(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ)
 146
 147 #define S_PCI_DEVHDR_LATTMR             8
 148 #define M_PCI_DEVHDR_LATTMR             _SB_MAKEMASK_32(8,S_PCI_DEVHDR_LATTMR)
 149 #define V_PCI_DEVHDR_LATTMR(x)          _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_LATTMR)
 150 #define G_PCI_DEVHDR_LATTMR(x)          _SB_GETVALUE_32(x,S_PCI_DEVHDR_LATTMR,M_PCI_DEVHDR_LATTMR)
 151
 152 #define S_PCI_DEVHDR_HDRTYPE            16
 153 #define M_PCI_DEVHDR_HDRTYPE            _SB_MAKEMASK_32(8,S_PCI_DEVHDR_HDRTYPE)
 154 #define V_PCI_DEVHDR_HDRTYPE(x)         _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_HDRTYPE)
 155 #define G_PCI_DEVHDR_HDRTYPE(x)         _SB_GETVALUE_32(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE)
 156
 157 #define K_PCI_DEVHDR_HDRTYPE_TYPE0      0
 158
 159 #define S_PCI_DEVHDR_BIST               24
 160 #define M_PCI_DEVHDR_BIST               _SB_MAKEMASK_32(8,S_PCI_DEVHDR_BIST)
 161 #define V_PCI_DEVHDR_BIST(x)            _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_BIST)
 162 #define G_PCI_DEVHDR_BIST(x)            _SB_GETVALUE_32(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST)
 163
 164 /*
 165  * PCI Status Register (Table 8-5).  Note that these constants
 166  * assume you've read the command and status register
 167  * together (32-bit read at offset 0x04)
 168  */
 169
 170 #define M_PCI_STATUS_CAPLIST            _SB_MAKEMASK1_32(20)
 171 #define M_PCI_STATUS_66MHZCAP           _SB_MAKEMASK1_32(21)
 172 #define M_PCI_STATUS_RESERVED2          _SB_MAKEMASK1_32(22)
 173 #define M_PCI_STATUS_FASTB2BCAP         _SB_MAKEMASK1_32(23)
 174 #define M_PCI_STATUS_MSTRDPARERR        _SB_MAKEMASK1_32(24)
 175
 176 #define S_PCI_STATUS_DEVSELTIMING       25
 177 #define M_PCI_STATUS_DEVSELTIMING       _SB_MAKEMASK_32(2,S_PCI_STATUS_DEVSELTIMING)
 178 #define V_PCI_STATUS_DEVSELTIMING(x)    _SB_MAKEVALUE_32(x,S_PCI_STATUS_DEVSELTIMING)
 179 #define G_PCI_STATUS_DEVSELTIMING(x)    _SB_GETVALUE_32(x,S_PCI_STATUS_DEVSELTIMING,M_PCI_STATUS_DEVSELTIMING)
 180
 181 #define M_PCI_STATUS_SIGDTGTABORT       _SB_MAKEMASK1_32(27)
 182 #define M_PCI_STATUS_RCVDTGTABORT       _SB_MAKEMASK1_32(28)
 183 #define M_PCI_STATUS_RCVDMSTRABORT      _SB_MAKEMASK1_32(29)
 184 #define M_PCI_STATUS_SIGDSERR           _SB_MAKEMASK1_32(30)
 185 #define M_PCI_STATUS_DETPARERR          _SB_MAKEMASK1_32(31)
 186
 187 /*
 188  * Device Header Register (Table 8-6, Table 8-7)
 189  */
 190
 191 #define S_PCI_DEVHDR_CLINESZ            0
 192 #define M_PCI_DEVHDR_CLINESZ            _SB_MAKEMASK_32(8,S_PCI_DEVHDR_CLINESZ)
 193 #define V_PCI_DEVHDR_CLINESZ(x)         _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_CLINESZ)
 194 #define G_PCI_DEVHDR_CLINESZ(x)         _SB_GETVALUE_32(x,S_PCI_DEVHDR_CLINESZ,M_PCI_DEVHDR_CLINESZ)
 195
 196 #define S_PCI_DEVHDR_LATTIME            8
 197 #define M_PCI_DEVHDR_LATTIME            _SB_MAKEMASK_32(8,S_PCI_DEVHDR_LATTIME)
 198 #define V_PCI_DEVHDR_LATTIME(x)         _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_LATTIME)
 199 #define G_PCI_DEVHDR_LATTIME(x)         _SB_GETVALUE_32(x,S_PCI_DEVHDR_LATTIME,M_PCI_DEVHDR_LATTIME)
 200
 201 #define S_PCI_DEVHDR_HDRTYPE            16
 202 #define M_PCI_DEVHDR_HDRTYPE            _SB_MAKEMASK_32(8,S_PCI_DEVHDR_HDRTYPE)
 203 #define V_PCI_DEVHDR_HDRTYPE(x)         _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_HDRTYPE)
 204 #define G_PCI_DEVHDR_HDRTYPE(x)         _SB_GETVALUE_32(x,S_PCI_DEVHDR_HDRTYPE,M_PCI_DEVHDR_HDRTYPE)
 205
 206 #define S_PCI_DEVHDR_BIST               24
 207 #define M_PCI_DEVHDR_BIST               _SB_MAKEMASK_32(8,S_PCI_DEVHDR_BIST)
 208 #define V_PCI_DEVHDR_BIST(x)            _SB_MAKEVALUE_32(x,S_PCI_DEVHDR_BIST)
 209 #define G_PCI_DEVHDR_BIST(x)            _SB_GETVALUE_32(x,S_PCI_DEVHDR_BIST,M_PCI_DEVHDR_BIST)
 210
 211 /*
 212  * Timeout and feature control Register (Table 8-8) (Table 8-9)
 213  * Note that these constants assume you've read the timeout/fcontrol register
 214  * together (32-bit read at offset 0x40)
 215  */
 216
 217 #define S_PCI_TIMEOUT_TRDY              0
 218 #define M_PCI_TIMEOUT_TRDY              _SB_MAKEMASK_32(8,S_PCI_TIMEOUT_TRDY)
 219 #define V_PCI_TIMEOUT_TRDY(x)           _SB_MAKEVALUE_32(x,S_PCI_TIMEOUT_TRDY)
 220 #define G_PCI_TIMEOUT_TRDY(x)           _SB_GETVALUE_32(x,S_PCI_TIMEOUT_TRDY,M_PCI_TIMEOUT_TRDY)
 221
 222 #define S_PCI_TIMEOUT_RETRY             8
 223 #define M_PCI_TIMEOUT_RETRY             _SB_MAKEMASK_32(8,S_PCI_TIMEOUT_RETRY)
 224 #define V_PCI_TIMEOUT_RETRY(x)          _SB_MAKEVALUE_32(x,S_PCI_TIMEOUT_RETRY)
 225 #define G_PCI_TIMEOUT_RETRY(x)          _SB_GETVALUE_32(x,S_PCI_TIMEOUT_RETRY,M_PCI_TIMEOUT_RETRY)
 226
 227 #define M_PCI_FCONTROL_BAR4_EN          _SB_MAKEMASK1_32(16)
 228 #define M_PCI_FCONTROL_BAR5_EN          _SB_MAKEMASK1_32(17)
 229 #define M_PCI_FCONTROL_PTP_EN           _SB_MAKEMASK1_32(18)
 230 #define M_PCI_FCONTROL_ADAPT_RETRY_EN   _SB_MAKEMASK1_32(19)
 231
 232 #define S_PCI_FCONTROL_MIN_TAR_RETRY    20
 233 #define M_PCI_FCONTROL_MIN_TAR_RETRY    _SB_MAKEMASK_32(3,S_PCI_FCONTROL_MIN_TAR_RETRY)
 234 #define V_PCI_FCONTROL_MIN_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_FCONTROL_MIN_TAR_RETRY)
 235 #define G_PCI_FCONTROL_MIN_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_FCONTROL_MIN_TAR_RETRY,M_PCI_FCONTROL_MIN_TAR_RETRY)
 236
 237 #define S_PCI_FCONTROL_NOM_TAR_RETRY    23
 238 #define M_PCI_FCONTROL_NOM_TAR_RETRY    _SB_MAKEMASK_32(4,S_PCI_FCONTROL_NOM_TAR_RETRY)
 239 #define V_PCI_FCONTROL_NOM_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_FCONTROL_NOM_TAR_RETRY)
 240 #define G_PCI_FCONTROL_NOM_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_FCONTROL_NOM_TAR_RETRY,M_PCI_FCONTROL_NOM_TAR_RETRY)
 241
 242 #define S_PCI_FCONTROL_MAX_TAR_RETRY    27
 243 #define M_PCI_FCONTROL_MAX_TAR_RETRY    _SB_MAKEMASK_32(5,S_PCI_FCONTROL_MAX_TAR_RETRY)
 244 #define V_PCI_FCONTROL_MAX_TAR_RETRY(x) _SB_MAKEVALUE_32(x,S_PCI_FCONTROL_MAX_TAR_RETRY)
 245 #define G_PCI_FCONTROL_MAX_TAR_RETRY(x) _SB_GETVALUE_32(x,S_PCI_FCONTROL_MAX_TAR_RETRY,M_PCI_FCONTROL_MAX_TAR_RETRY)
 246
 247 /*
 248  * BAR0 Map Table Entry (Offsets 0x40-0x80) (Table 8-10)
 249  */
 250
 251 #define M_PCI_BAR0MAP_ENABLE            _SB_MAKEMASK1_32(0)
 252 #define M_PCI_BAR0MAP_SENDLDT           _SB_MAKEMASK1_32(1)
 253 #define S_PCI_BAR0MAP_ADDR              12
 254 #define M_PCI_BAR0MAP_ADDR              _SB_MAKEMASK_32(20,S_PCI_BAR0MAP_ADDR)
 255
 256 /*
 257  * Additional Status Register (Table 8-11)
 258  */
 259
 260 #define M_PCI_ASTATUS_HOTPLUG_EN        _SB_MAKEMASK1_32(0)
 261 #define M_PCI_ASTATUS_SERR_DET          _SB_MAKEMASK1_32(1)
 262 #define M_PCI_ASTATUS_TRDYERR           _SB_MAKEMASK1_32(2)
 263 #define M_PCI_ASTATUS_RETRTYERR         _SB_MAKEMASK1_32(3)
 264 #define M_PCI_ASTATUS_TRDYINTMASK       _SB_MAKEMASK1_32(4)
 265 #define M_PCI_ASTATUS_RETRYINTMASK      _SB_MAKEMASK1_32(5)
 266 #define M_PCI_ASTATUS_SIGNALINTA        _SB_MAKEMASK1_32(6)
 267
 268 #if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
 269 /*
 270  * Read Host Register
 271  */
 272
 273 #define M_PCI_READHOST_RDHOST   _SB_MAKEMASK1_32(0)
 274
 275 /*
 276  * Adaptive Extend Register
 277  */
 278
 279 #define S_PCI_ADXTEND_NOM_TAR_RETRY     1
 280 #define M_PCI_ADXTEND_NOM_TAR_RETRY     _SB_MAKEMASK_32(3,S_PCI_ADXTEND_NOM_TAR_RETRY)
 281 #define V_PCI_ADXTEND_NOM_TAR_RETRY(x)  _SB_MAKEVALUE_32(x,S_PCI_ADXTEND_NOM_TAR_RETRY)
 282 #define G_PCI_ADXTEND_NOM_TAR_RETRY(x)  _SB_GETVALUE_32(x,S_PCI_ADXTEND_NOM_TAR_RETRY,M_PCI_ADXTEND_NOM_TAR_RETRY)
 283
 284 #define S_PCI_ADXTEND_MAX_TAR_RETRY     4
 285 #define M_PCI_ADXTEND_MAX_TAR_RETRY     _SB_MAKEMASK_32(2,S_PCI_ADXTEND_MAX_TAR_RETRY)
 286 #define V_PCI_ADXTEND_MAX_TAR_RETRY(x)  _SB_MAKEVALUE_32(x,S_PCI_ADXTEND_MAX_TAR_RETRY)
 287 #define G_PCI_ADXTEND_MAX_TAR_RETRY(x)  _SB_GETVALUE_32(x,S_PCI_ADXTEND_MAX_TAR_RETRY,M_PCI_ADXTEND_MAX_TAR_RETRY)
 288
 289 #define M_PCI_ADXTEND_DIS_DMAR_IOW_DEP  _SB_MAKEMASK1_32(6)
 290 #define M_PCI_ADXTEND_DIS_MEMRD_BE      _SB_MAKEMASK1_32(6)
 291 #endif /* 1250 PASS2 || 112x PASS1 */
 292
 293
 294 #endif