release/src-rt-6.x.4708/cfe/cfe/arch/mips/cpu/rm7000/include/sbmips.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  MIPS64 CPU definitions                   File: sbmips.h
   5     *
   6     *  This module contains constants and macros specific to the
   7     *  SB1 MIPS64 core.
   8     *
   9     *  Author:  Mitch Lichtenberg (mitch@sibyte.com)
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This software is furnished under license and may be used and
  17     *  copied only in accordance with the following terms and
  18     *  conditions.  Subject to these conditions, you may download,
  19     *  copy, install, use, modify and distribute modified or unmodified
  20     *  copies of this software in source and/or binary form.  No title
  21     *  or ownership is transferred hereby.
  22     *
  23     *  1) Any source code used, modified or distributed must reproduce
  24     *     and retain this copyright notice and list of conditions
  25     *     as they appear in the source file.
  26     *
  27     *  2) No right is granted to use any trade name, trademark, or
  28     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  29     *     name may not be used to endorse or promote products derived
  30     *     from this software without the prior written permission of
  31     *     Broadcom Corporation.
  32     *
  33     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  34     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  35     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  37     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  38     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  39     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  41     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  42     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  43     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  44     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  45     *     THE POSSIBILITY OF SUCH DAMAGE.
  46     ********************************************************************* */
  47
  48 #ifndef _SB_MIPS_H
  49 #define _SB_MIPS_H
  50
  51 /*  *********************************************************************
  52     *  Configure language
  53     ********************************************************************* */
  54
  55 #if defined(__ASSEMBLER__)
  56 #define _ATYPE_
  57 #define _ATYPE32_
  58 #define _ATYPE64_
  59 #else
  60 #define _ATYPE_         (__SIZE_TYPE__)
  61 #define _ATYPE32_       (int)
  62 #define _ATYPE64_       (long long)
  63 #endif
  64
  65
  66 /*  *********************************************************************
  67     *  Bitfield macros
  68     ********************************************************************* */
  69
  70 /*
  71  * Make a mask for 1 bit at position 'n'
  72  */
  73
  74 #define _MM_MAKEMASK1(n) (1 << (n))
  75
  76 /*
  77  * Make a mask for 'v' bits at position 'n'
  78  */
  79
  80 #define _MM_MAKEMASK(v,n) (((1<<(v))-1) << (n))
  81
  82 /*
  83  * Make a value at 'v' at bit position 'n'
  84  */
  85
  86 #define _MM_MAKEVALUE(v,n) ((v) << (n))
  87
  88 /*
  89  * Retrieve a value from 'v' at bit position 'n' with 'm' mask bits
  90  */
  91
  92 #define _MM_GETVALUE(v,n,m) (((v) & (m)) >> (n))
  93
  94
  95
  96 /*  *********************************************************************
  97     *  32-bit MIPS Address Spaces
  98     ********************************************************************* */
  99
 100 #ifdef __ASSEMBLER__
 101 #define _ACAST32_
 102 #define _ACAST64_
 103 #else
 104 #define _ACAST32_       _ATYPE_ _ATYPE32_       /* widen if necessary */
 105 #define _ACAST64_               _ATYPE64_       /* do _not_ narrow */
 106 #endif
 107
 108 /* 32-bit address map */
 109 #define UBASE           0x00000000              /* user+ mapped */
 110 #define USIZE           0x80000000
 111 #define K0BASE          (_ACAST32_ 0x80000000)  /* kernel unmapped cached */
 112 #define K0SIZE          0x20000000
 113 #define K1BASE          (_ACAST32_ 0xa0000000)  /* kernel unmapped uncached */
 114 #define K1SIZE          0x20000000
 115 #define KSBASE          (_ACAST32_ 0xc0000000)  /* supervisor+ mapped */
 116 #define KSSIZE          0x20000000
 117 #define K3BASE          (_ACAST32_ 0xe0000000)  /* kernel mapped */
 118 #define K3SIZE          0x20000000
 119
 120 /* 64-bit address map additions to the above (sign-extended) ranges */
 121 #define XUBASE          (_ACAST64_ 0x0000000080000000)  /* user+ mapped */
 122 #define XUSIZE          (_ACAST64_ 0x00000FFF80000000)
 123 #define XSSEGBASE       (_ACAST64_ 0x4000000000000000)  /* supervisor+ mapped */
 124 #define XSSEGSIZE       (_ACAST64_ 0x0000100000000000)
 125 #define XKPHYSBASE      (_ACAST64_ 0x8000000000000000)  /* kernel unmapped */
 126 #define XKPHYSSIZE      (_ACAST64_ 0x0000100000000000)
 127 #define XKSEGBASE       (_ACAST64_ 0xC000000000000000)  /* kernel mapped */
 128 #define XKSEGSIZE       (_ACAST64_ 0x00000FFF80000000)
 129
 130 #define GEN_VECT        (_ACAST32_ 0x80000080)
 131 #define UTLB_VECT       (_ACAST32_ 0x80000000)
 132
 133 /*  *********************************************************************
 134     *  Address space coercion macros
 135     ********************************************************************* */
 136
 137 #define PHYS_TO_K0(pa)  (K0BASE | (pa))
 138 #define PHYS_TO_K1(pa)  (K1BASE | (pa))
 139 #define K0_TO_PHYS(va)  ((va) & (K0SIZE-1))
 140 #define K1_TO_PHYS(va)  ((va) & (K1SIZE-1))
 141 #define K0_TO_K1(va)    ((va) | K1SIZE)
 142 #define K1_TO_K0(va)    ((va) & ~K1SIZE)
 143
 144 #define PHYS_TO_XK1(p) (_ACAST64_ (0xffffffffa0000000 | (p)))
 145 #define XK1_TO_PHYS(p) ((p) & (K1SIZE-1))
 146 #define PHYS_TO_XKPHYS(cca,p) (_SB_MAKEMASK1(63) | (_SB_MAKE64(cca) << 59) | (p))
 147 #define PHYS_TO_XKSEG_UNCACHED(p)  PHYS_TO_XKPHYS(K_CALG_UNCACHED,(p))
 148 #define PHYS_TO_XKSEG_CACHED(p)    PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE,(p))
 149 #define XKPHYS_TO_PHYS(p) ((p) & _SB_MAKEMASK(0,59))
 150
 151
 152 #if !defined(__ASSEMBLER__)
 153 #define mips_wbflush()  __asm__ __volatile__ ("sync" : : : "memory")
 154 #define ISK0SEG(va)     ((va) >= K0BASE && (va) <= (K0BASE + K0SIZE - 1))
 155 #define ISK1SEG(va)     ((va) >= K1BASE && (va) <= (K1BASE + K1SIZE - 1))
 156 #endif
 157
 158 /*  *********************************************************************
 159     *  Register aliases
 160     ********************************************************************* */
 161
 162 #if defined(__ASSEMBLER__)
 163 #define zero            $0
 164 #define AT              $1              /* assembler temporaries */
 165 #define v0              $2              /* value holders */
 166 #define v1              $3
 167 #define a0              $4              /* arguments */
 168 #define a1              $5
 169 #define a2              $6
 170 #define a3              $7
 171 #define t0              $8              /* temporaries */
 172 #define t1              $9
 173 #define t2              $10
 174 #define t3              $11
 175 #define t4              $12
 176 #define t5              $13
 177 #define t6              $14
 178 #define t7              $15
 179 #define ta0             $12
 180 #define ta1             $13
 181 #define ta2             $14
 182 #define ta3             $15
 183 #define s0              $16             /* saved registers */
 184 #define s1              $17
 185 #define s2              $18
 186 #define s3              $19
 187 #define s4              $20
 188 #define s5              $21
 189 #define s6              $22
 190 #define s7              $23
 191 #define t8              $24             /* temporaries */
 192 #define t9              $25
 193 #define k0              $26             /* kernel registers */
 194 #define k1              $27
 195 #define gp              $28             /* global pointer */
 196 #define sp              $29             /* stack pointer */
 197 #define s8              $30             /* saved register */
 198 #define fp              $30             /* frame pointer */
 199 #define ra              $31             /* return address */
 200 #endif
 201
 202 /*  *********************************************************************
 203     *  CP0 Registers
 204     ********************************************************************* */
 205
 206 #if defined(__ASSEMBLER__)
 207 #define C0_INX          $0              /* CP0: TLB Index */
 208 #define C0_RAND         $1              /* CP0: TLB Random */
 209 #define C0_TLBLO0       $2              /* CP0: TLB EntryLo0 */
 210 #define C0_TLBLO        C0_TLBLO0       /* CP0: TLB EntryLo0 */
 211 #define C0_TLBLO1       $3              /* CP0: TLB EntryLo1 */
 212 #define C0_CTEXT        $4              /* CP0: Context */
 213 #define C0_PGMASK       $5              /* CP0: TLB PageMask */
 214 #define C0_WIRED        $6              /* CP0: TLB Wired */
 215 #define C0_BADVADDR     $8              /* CP0: Bad Virtual Address */
 216 #define C0_COUNT        $9              /* CP0: Count */
 217 #define C0_TLBHI        $10             /* CP0: TLB EntryHi */
 218 #define C0_COMPARE      $11             /* CP0: Compare */
 219 #define C0_SR           $12             /* CP0: Processor Status */
 220 #define C0_STATUS       C0_SR           /* CP0: Processor Status */
 221 #define C0_CAUSE        $13             /* CP0: Exception Cause */
 222 #define C0_EPC          $14             /* CP0: Exception PC */
 223 #define C0_PRID         $15             /* CP0: Processor Revision Indentifier */
 224 #define C0_CONFIG       $16             /* CP0: Config */
 225 #define C0_LLADDR       $17             /* CP0: LLAddr */
 226 #define C0_WATCHLO      $18             /* CP0: WatchpointLo */
 227 #define C0_WATCHHI      $19             /* CP0: WatchpointHi */
 228 #define C0_XCTEXT       $20             /* CP0: XContext */
 229 #define C0_ECC          $26             /* CP0: ECC */
 230 #define C0_CACHEERR     $27             /* CP0: CacheErr */
 231 #define C0_TAGLO        $28             /* CP0: TagLo */
 232 #define C0_TAGHI        $29             /* CP0: TagHi */
 233 #define C0_ERREPC       $30             /* CP0: ErrorEPC */
 234 #else
 235 #define C0_INX          0               /* CP0: TLB Index */
 236 #define C0_RAND         1               /* CP0: TLB Random */
 237 #define C0_TLBLO0       2               /* CP0: TLB EntryLo0 */
 238 #define C0_TLBLO        C0_TLBLO0       /* CP0: TLB EntryLo0 */
 239 #define C0_TLBLO1       3               /* CP0: TLB EntryLo1 */
 240 #define C0_CTEXT        4               /* CP0: Context */
 241 #define C0_PGMASK       5               /* CP0: TLB PageMask */
 242 #define C0_WIRED        6               /* CP0: TLB Wired */
 243 #define C0_BADVADDR     8               /* CP0: Bad Virtual Address */
 244 #define C0_COUNT        9               /* CP0: Count */
 245 #define C0_TLBHI        10              /* CP0: TLB EntryHi */
 246 #define C0_COMPARE      11              /* CP0: Compare */
 247 #define C0_SR           12              /* CP0: Processor Status */
 248 #define C0_STATUS       C0_SR           /* CP0: Processor Status */
 249 #define C0_CAUSE        13              /* CP0: Exception Cause */
 250 #define C0_EPC          14              /* CP0: Exception PC */
 251 #define C0_PRID         15              /* CP0: Processor Revision Indentifier */
 252 #define C0_CONFIG       16              /* CP0: Config */
 253 #define C0_LLADDR       17              /* CP0: LLAddr */
 254 #define C0_WATCHLO      18              /* CP0: WatchpointLo */
 255 #define C0_WATCHHI      19              /* CP0: WatchpointHi */
 256 #define C0_XCTEXT       20              /* CP0: XContext */
 257 #define C0_ECC          26              /* CP0: ECC */
 258 #define C0_CACHEERR     27              /* CP0: CacheErr */
 259 #define C0_TAGLO        28              /* CP0: TagLo */
 260 #define C0_TAGHI        29              /* CP0: TagHi */
 261 #define C0_ERREPC       30              /* CP0: ErrorEPC */
 262 #endif
 263
 264 /*  *********************************************************************
 265     *  CP1 (floating point) control registers
 266     ********************************************************************* */
 267
 268 #define FPA_IRR         0               /* CP1: Implementation/Revision */
 269 #define FPA_CSR         31              /* CP1: Control/Status */
 270
 271 /*  *********************************************************************
 272     *  Macros for generating assembly language routines
 273     ********************************************************************* */
 274
 275 #if defined(__ASSEMBLER__)
 276
 277 /* global leaf function (does not call other functions) */
 278 #define LEAF(name)              \
 279         .globl  name;           \
 280         .ent    name;           \
 281 name:
 282
 283 /* global alternate entry to (local or global) leaf function */
 284 #define XLEAF(name)             \
 285         .globl  name;           \
 286         .aent   name;           \
 287 name:
 288
 289 /* end of a global function */
 290 #define END(name)               \
 291         .size   name,.-name;    \
 292         .end    name
 293
 294 /* local leaf function (does not call other functions) */
 295 #define SLEAF(name)             \
 296         .ent    name;           \
 297 name:
 298
 299 /* local alternate entry to (local or global) leaf function */
 300 #define SXLEAF(name)            \
 301         .aent   name;           \
 302 name:
 303
 304 /* end of a local function */
 305 #define SEND(name)              \
 306         END(name)
 307
 308 /* define & export a symbol */
 309 #define EXPORT(name)            \
 310         .globl name;            \
 311 name:
 312
 313 /* import a symbol */
 314 #define IMPORT(name, size)      \
 315         .extern name,size
 316
 317 /* define a zero-fill common block (BSS if not overridden) with a global name */
 318 #define COMM(name,size)         \
 319         .comm   name,size
 320
 321 /* define a zero-fill common block (BSS if not overridden) with a local name */
 322 #define LCOMM(name,size)                \
 323         .lcomm  name,size
 324
 325 #endif
 326
 327
 328 /* Floating-Point Control register bits */
 329 #define CSR_C           0x00800000
 330 #define CSR_EXC         0x0003f000
 331 #define CSR_EE          0x00020000
 332 #define CSR_EV          0x00010000
 333 #define CSR_EZ          0x00008000
 334 #define CSR_EO          0x00004000
 335 #define CSR_EU          0x00002000
 336 #define CSR_EI          0x00001000
 337 #define CSR_TV          0x00000800
 338 #define CSR_TZ          0x00000400
 339 #define CSR_TO          0x00000200
 340 #define CSR_TU          0x00000100
 341 #define CSR_TI          0x00000080
 342 #define CSR_SV          0x00000040
 343 #define CSR_SZ          0x00000020
 344 #define CSR_SO          0x00000010
 345 #define CSR_SU          0x00000008
 346 #define CSR_SI          0x00000004
 347 #define CSR_RM          0x00000003
 348
 349 /* Status Register */
 350 #define M_SR_CUMASK     _MM_MAKEMASK(4,28)      /* coprocessor usable bits */
 351 #define M_SR_CU3        _MM_MAKEMASK1(31)       /* coprocessor 3 usable */
 352 #define M_SR_CU2        _MM_MAKEMASK1(30)       /* coprocessor 2 usable */
 353 #define M_SR_CU1        _MM_MAKEMASK1(29)       /* coprocessor 1 usable */
 354 #define M_SR_CU0        _MM_MAKEMASK1(28)       /* coprocessor 0 usable */
 355
 356 #define M_SR_RP         _MM_MAKEMASK1(27)       /* reduced power mode */
 357 #define M_SR_FR         _MM_MAKEMASK1(26)       /* fpu regs any data */
 358 #define M_SR_RE         _MM_MAKEMASK1(25)       /* reverse endian */
 359 #define M_SR_MX         _MM_MAKEMASK1(24)       /* MDMX */
 360 #define M_SR_PX         _MM_MAKEMASK1(23)       /* 64-bit ops in user mode */
 361 #define M_SR_BEV        _MM_MAKEMASK1(22)       /* boot exception vectors */
 362 #define M_SR_TS         _MM_MAKEMASK1(21)       /* TLB is shut down */
 363 #define M_SR_SR         _MM_MAKEMASK1(20)       /* soft reset */
 364 #define M_SR_NMI        _MM_MAKEMASK1(19)       /* nonmaskable interrupt */
 365
 366 #define M_SR_IMASK      _MM_MAKEMASK(8,8)       /* all interrupt mask bits */
 367
 368 #define M_SR_IBIT8      _MM_MAKEMASK1(15)       /* individual bits */
 369 #define M_SR_IBIT7      _MM_MAKEMASK1(14)
 370 #define M_SR_IBIT6      _MM_MAKEMASK1(13)
 371 #define M_SR_IBIT5      _MM_MAKEMASK1(12)
 372 #define M_SR_IBIT4      _MM_MAKEMASK1(11)
 373 #define M_SR_IBIT3      _MM_MAKEMASK1(10)
 374 #define M_SR_IBIT2      _MM_MAKEMASK1(9)
 375 #define M_SR_IBIT1      _MM_MAKEMASK1(8)
 376
 377 #define M_SR_IMASK8     0                       /* masks for nested int levels */
 378 #define M_SR_IMASK7     _MM_MAKEMASK(1,15)
 379 #define M_SR_IMASK6     _MM_MAKEMASK(2,14)
 380 #define M_SR_IMASK5     _MM_MAKEMASK(3,13)
 381 #define M_SR_IMASK4     _MM_MAKEMASK(4,12)
 382 #define M_SR_IMASK3     _MM_MAKEMASK(5,11)
 383 #define M_SR_IMASK2     _MM_MAKEMASK(6,10)
 384 #define M_SR_IMASK1     _MM_MAKEMASK(7,9)
 385 #define M_SR_IMASK0     _MM_MAKEMASK(8,8)
 386
 387 #define M_SR_KX         _MM_MAKEMASK1(7)        /* 64-bit access for kernel */
 388 #define M_SR_SX         _MM_MAKEMASK1(6)        /* .. for supervisor */
 389 #define M_SR_UX         _MM_MAKEMASK1(5)        /* .. for user */
 390
 391 #define S_SR_KSU        3                       /* base operating mode mode */
 392 #define M_SR_KSU        _MM_MAKEMASK(2,S_SR_KSU)
 393 #define V_SR_KSU(x)     _MM_MAKEVALUE(x,S_SR_KSU)
 394 #define G_SR_KSU(x)     _MM_GETVALUE(x,S_SR_KSU,M_SR_KSU)
 395 #define K_SR_KSU_KERNEL 0
 396 #define K_SR_KSU_SUPR   1
 397 #define K_SR_KSU_USER   2
 398
 399 #define M_SR_UM         _MM_MAKEMASK1(4)
 400 #define M_SR_ERL        _MM_MAKEMASK1(2)
 401 #define M_SR_EXL        _MM_MAKEMASK1(1)
 402 #define M_SR_IE         _MM_MAKEMASK1(0)
 403
 404 /*
 405  * Cause Register
 406  */
 407 #define M_CAUSE_BD      _MM_MAKEMASK1(31) /* exception in BD slot */
 408
 409 #define S_CAUSE_CE      28              /* coprocessor error */
 410 #define M_CAUSE_CE      _MM_MAKEMASK(2,S_CAUSE_CE)
 411 #define V_CAUSE_CE(x)   _MM_MAKEVALUE(x,S_CAUSE_CE)
 412 #define G_CAUSE_CE(x)   _MM_GETVALUE(x,S_CAUSE_CE,M_CAUSE_CE)
 413
 414 #define M_CAUSE_IV      _MM_MAKEMASK1(23) /* special interrupt */
 415 #define M_CAUSE_WP      _MM_MAKEMASK1(22) /* watch interrupt deferred */
 416
 417 #define S_CAUSE_IPMASK  8
 418 #define M_CAUSE_IPMASK  _MM_MAKEMASK(8,S_CAUSE_IPMASK)
 419 #define M_CAUSE_IP8     _MM_MAKEMASK1(15)       /* hardware interrupts */
 420 #define M_CAUSE_IP7     _MM_MAKEMASK1(14)
 421 #define M_CAUSE_IP6     _MM_MAKEMASK1(13)
 422 #define M_CAUSE_IP5     _MM_MAKEMASK1(12)
 423 #define M_CAUSE_IP4     _MM_MAKEMASK1(11)
 424 #define M_CAUSE_IP3     _MM_MAKEMASK1(10)
 425 #define M_CAUSE_SW2     _MM_MAKEMASK1(9)        /* software interrupts */
 426 #define M_CAUSE_SW1     _MM_MAKEMASK1(8)
 427
 428 #define S_CAUSE_EXC     2
 429 #define M_CAUSE_EXC     _MM_MAKEMASK(5,S_CAUSE_EXC)
 430 #define V_CAUSE_EXC(x)  _MM_MAKEVALUE(x,S_CAUSE_EXC)
 431 #define G_CAUSE_EXC(x)  _MM_GETVALUE(x,S_CAUSE_EXC,M_CAUSE_EXC)
 432
 433 /* Exception Code */
 434 #define K_CAUSE_EXC_INT         0       /* External interrupt */
 435 #define K_CAUSE_EXC_MOD         1       /* TLB modification */
 436 #define K_CAUSE_EXC_TLBL        2       /* TLB miss (Load or Ifetch) */
 437 #define K_CAUSE_EXC_TLBS        3       /* TLB miss (Save) */
 438 #define K_CAUSE_EXC_ADEL        4       /* Address error (Load or Ifetch) */
 439 #define K_CAUSE_EXC_ADES        5       /* Address error (Save) */
 440 #define K_CAUSE_EXC_IBE         6       /* Bus error (Ifetch) */
 441 #define K_CAUSE_EXC_DBE         7       /* Bus error (data load or store) */
 442 #define K_CAUSE_EXC_SYS         8       /* System call */
 443 #define K_CAUSE_EXC_BP          9       /* Break point */
 444 #define K_CAUSE_EXC_RI          10      /* Reserved instruction */
 445 #define K_CAUSE_EXC_CPU         11      /* Coprocessor unusable */
 446 #define K_CAUSE_EXC_OVF         12      /* Arithmetic overflow */
 447 #define K_CAUSE_EXC_TRAP        13      /* Trap exception */
 448 #define K_CAUSE_EXC_VCEI        14      /* Virtual Coherency Exception (I) */
 449 #define K_CAUSE_EXC_FPE         15      /* Floating Point Exception */
 450 #define K_CAUSE_EXC_CP2         16      /* Cp2 Exception */
 451 #define K_CAUSE_EXC_WATCH       23      /* Watchpoint exception */
 452 #define K_CAUSE_EXC_VCED        31      /* Virtual Coherency Exception (D) */
 453
 454 #define K_NTLBENTRIES   64
 455
 456 #define HI_HALF(x)      ((x) >> 16)
 457 #define LO_HALF(x)      ((x) & 0xffff)
 458
 459 /* FPU stuff */
 460
 461 #if defined(__ASSEMBLER__)
 462 #define C1_CSR          $31
 463 #define C1_FRID         $0
 464 #else
 465 #define C1_CSR          31
 466 #define C1_FRID         0
 467 #endif
 468
 469 #define S_FCSR_CAUSE    12
 470 #define M_FCSR_CAUSE    _MM_MAKEMASK(5,S_FCSR_CAUSE)
 471 #define V_FCSR_CAUSE(x) _MM_MAKEVALUE(x,S_FCSR_CAUSE)
 472 #define G_FCSR_CAUSE(x) _MM_GETVALUE(x,S_FCSR_CAUSE,M_FCSR_CAUSE)
 473
 474 #define S_FCSR_ENABLES  7
 475 #define M_FCSR_ENABLES  _MM_MAKEMASK(5,S_FCSR_ENABLES)
 476 #define V_FCSR_ENABLES(x) _MM_MAKEVALUE(x,S_FCSR_ENABLES)
 477 #define G_FCSR_ENABLES(x) _MM_GETVALUE(x,S_FCSR_ENABLES,M_FCSR_ENABLES)
 478
 479 #define S_FCSR_FLAGS    2
 480 #define M_FCSR_FLAGS    _MM_MAKEMASK(5,S_FCSR_FLAGS)
 481 #define V_FCSR_FLAGS(x) _MM_MAKEVALUE(x,S_FCSR_FLAGS)
 482 #define G_FCSR_FLAGS(x) _MM_GETVALUE(x,S_FCSR_FLAGS,M_FCSR_FLAGS)
 483
 484
 485 /*
 486  * MIPS64 Config Register (select 0)
 487  */
 488 #define M_CFG_CFG1      _MM_MAKEMASK1(31)       /* config1 select1 is impl */
 489 #define M_CFG_BE        _MM_MAKEMASK1(15)       /* big-endian mode */
 490
 491 #define S_CFG_AT        13                      /* Architecture Type */
 492 #define M_CFG_AT        _MM_MAKEMASK(2,S_CFG_AT)
 493 #define V_CFG_AT(x)     _MM_MAKEVALUE(x,S_CFG_AT)
 494 #define G_CFG_AT(x)     _MM_GETVALUE(x,S_CFG_AT,M_CFG_AT)
 495 #define K_CFG_AT_MIPS32 0
 496 #define K_CFG_AT_MIPS64_32 1
 497 #define K_CFG_AT_MIPS64 2
 498
 499 #define S_CFG_AR        10                      /* Architecture Revision */
 500 #define M_CFG_AR        _MM_MAKEMASK(3,S_CFG_AR)
 501 #define V_CFG_AR(x)     _MM_MAKEVALUE(x,S_CFG_AR)
 502 #define G_CFG_AR(x)     _MM_GETVALUE(x,S_CFG_AR,M_CFG_AR)
 503 #define K_CFG_AR_REV1   0
 504
 505 #define S_CFG_MMU       7                       /* MMU Type */
 506 #define M_CFG_MMU       _MM_MAKEMASK(3,S_CFG_MMU)
 507 #define V_CFG_MMU(x)    _MM_MAKEVALUE(x,S_CFG_MMU)
 508 #define G_CFG_MMU(x)    _MM_GETVALUE(x,S_CFG_MMU,M_CFG_MMU)
 509 #define K_CFG_MMU_NONE  0
 510 #define K_CFG_MMU_TLB   1
 511 #define K_CFG_MMU_BAT   2
 512 #define K_CFG_MMU_FIXED 3
 513
 514 #define S_CFG_K0COH     0                       /* K0seg coherency */
 515 #define M_CFG_K0COH     _MM_MAKEMASK(3,S_CFG_K0COH)
 516 #define V_CFG_K0COH(x)  _MM_MAKEVALUE(x,S_CFG_K0COH)
 517 #define G_CFG_K0COH(x)  _MM_GETVALUE(x,S_CFG_K0COH,M_CFG_K0COH)
 518 #define K_CFG_K0COH_UNCACHED    2
 519 #define K_CFG_K0COH_CACHEABLE   3
 520 #define K_CFG_K0COH_COHERENT    5
 521
 522 /*
 523  * MIPS64 Config Register (select 1)
 524  */
 525
 526 #define M_CFG_CFG2      _MM_MAKEMASK1(31)       /* config2 select2 is impl */
 527
 528 #define S_CFG_MMUSIZE   25
 529 #define M_CFG_MMUSIZE   _MM_MAKEMASK(6,S_CFG_MMUSIZE)
 530
 531 #define S_CFG_IS        22
 532 #define M_CFG_IS        _MM_MAKEMASK(3,S_CFG_IS)
 533 #define V_CFG_IS(x)     _MM_MAKEVALUE(x,S_CFG_IS)
 534 #define G_CFG_IS(x)     _MM_GETVALUE(x,S_CFG_IS,M_CFG_IS)
 535
 536 #define S_CFG_IL        19
 537 #define M_CFG_IL        _MM_MAKEMASK(S_CFG_IL,3)
 538 #define V_CFG_IL(x)     _MM_MAKEVALUE(x,S_CFG_IL)
 539 #define G_CFG_IL(x)     _MM_GETVALUE(x,S_CFG_IL,M_CFG_IL)
 540
 541 #define S_CFG_IA        16
 542 #define M_CFG_IA        _MM_MAKEMASK(3,S_CFG_IA)
 543 #define V_CFG_IA(x)     _MM_MAKEVALUE(x,S_CFG_IA)
 544 #define G_CFG_IA(x)     _MM_GETVALUE(x,S_CFG_IA,M_CFG_IA)
 545
 546 #define S_CFG_DS        13
 547 #define M_CFG_DS        _MM_MAKEMASK(3,S_CFG_DS)
 548 #define V_CFG_DS(x)     _MM_MAKEVALUE(x,S_CFG_DS)
 549 #define G_CFG_DS(x)     _MM_GETVALUE(x,S_CFG_DS,M_CFG_DS)
 550
 551 #define S_CFG_DL        10
 552 #define M_CFG_DL        _MM_MAKEMASK(3,S_CFG_DL)
 553 #define V_CFG_DL(x)     _MM_MAKEVALUE(x,S_CFG_DL)
 554 #define G_CFG_DL(x)     _MM_GETVALUE(x,S_CFG_DL,M_CFG_DL)
 555
 556 #define S_CFG_DA        7
 557 #define M_CFG_DA        _MM_MAKEMASK(3,S_CFG_DA)
 558 #define V_CFG_DA(x)     _MM_MAKEVALUE(x,S_CFG_DA)
 559 #define G_CFG_DA(x)     _MM_GETVALUE(x,S_CFG_DA,M_CFG_DA)
 560
 561 #define M_CFG_PC        _MM_MAKEMASK1(4)        /* perf ctrs present */
 562 #define M_CFG_WR        _MM_MAKEMASK1(3)        /* watch regs present */
 563 #define M_CFG_CA        _MM_MAKEMASK1(2)        /* MIPS16 present */
 564 #define M_CFG_EP        _MM_MAKEMASK1(1)        /* EJTAG present */
 565 #define M_CFG_FP        _MM_MAKEMASK1(0)        /* FPU present */
 566
 567
 568
 569 /*
 570  * Primary Cache TagLo
 571  */
 572
 573 #define S_TAGLO_PTAG    8
 574 #define M_TAGLO_PTAG    _MM_MAKEMASK(56,S_TAGLO_PTAG)
 575
 576 #define S_TAGLO_PSTATE  6
 577 #define M_TAGLO_PSTATE  _MM_MAKEMASK(2,S_TAGLO_PSTATE)
 578 #define V_TAGLO_PSTATE(x) _MM_MAKEVALUE(x,S_TAGLO_PSTATE)
 579 #define G_TAGLO_PSTATE(x) _MM_GETVALUE(x,S_TAGLO_PSTATE,M_TAGLO_PSTATE)
 580 #define K_TAGLO_PSTATE_INVAL            0
 581 #define K_TAGLO_PSTATE_SHARED           1
 582 #define K_TAGLO_PSTATE_CLEAN_EXCL       2
 583 #define K_TAGLO_PSTATE_DIRTY_EXCL       3
 584
 585 #define M_TAGLO_LOCK    _MM_MAKEMASK1(5)
 586 #define M_TAGLO_PARITY  _MM_MAKEMASK1(0)
 587
 588
 589 /*
 590  * CP0 CacheErr register
 591  */
 592 #define M_CERR_DATA     _MM_MAKEMASK1(31)       /* err in D space */
 593 #define M_CERR_SCACHE   _MM_MAKEMASK1(30)       /* err in l2, not l1 */
 594 #define M_CERR_DERR     _MM_MAKEMASK1(29)       /* data error */
 595 #define M_CERR_TERR     _MM_MAKEMASK1(28)       /* tag error */
 596 #define M_CERR_EXTRQ    _MM_MAKEMASK1(27)       /* external req caused err */
 597 #define M_CERR_BPAR     _MM_MAKEMASK1(26)       /* bus parity err */
 598 #define M_CERR_ADATA    _MM_MAKEMASK1(25)       /* additional data */
 599 #define M_CERR_IDX      _MM_MAKEMASK(22,0)
 600
 601
 602
 603 /*
 604  * Primary Cache operations
 605  */
 606 #define Index_Invalidate_I               0x0         /* 0       0 */
 607 #define Index_Writeback_Inv_D            0x1         /* 0       1 */
 608 #define Index_Invalidate_SI              0x2         /* 0       2 */
 609 #define Index_Writeback_Inv_SD           0x3         /* 0       3 */
 610 #define Index_Load_Tag_I                 0x4         /* 1       0 */
 611 #define Index_Load_Tag_D                 0x5         /* 1       1 */
 612 #define Index_Load_Tag_SI                0x6         /* 1       2 */
 613 #define Index_Load_Tag_SD                0x7         /* 1       3 */
 614 #define Index_Store_Tag_I                0x8         /* 2       0 */
 615 #define Index_Store_Tag_D                0x9         /* 2       1 */
 616 #define Index_Store_Tag_SI               0xA         /* 2       2 */
 617 #define Index_Store_Tag_SD               0xB         /* 2       3 */
 618 #define Create_Dirty_Exc_D               0xD         /* 3       1 */
 619 #define Create_Dirty_Exc_SD              0xF         /* 3       3 */
 620 #define Hit_Invalidate_I                 0x10        /* 4       0 */
 621 #define Hit_Invalidate_D                 0x11        /* 4       1 */
 622 #define Hit_Invalidate_SI                0x12        /* 4       2 */
 623 #define Hit_Invalidate_SD                0x13        /* 4       3 */
 624 #define Fill_I                           0x14        /* 5       0 */
 625 #define Hit_Writeback_Inv_D              0x15        /* 5       1 */
 626 #define Hit_Writeback_Inv_SD             0x17        /* 5       3 */
 627 #define Hit_Writeback_I                  0x18        /* 6       0 */
 628 #define Hit_Writeback_D                  0x19        /* 6       1 */
 629 #define Hit_Writeback_SD                 0x1B        /* 6       3 */
 630 #define Hit_Set_Virtual_SI               0x1E        /* 7       2 */
 631 #define Hit_Set_Virtual_SD               0x1F        /* 7       3 */
 632
 633 /* Watchpoint Register */
 634 #define M_WATCH_PA              0xfffffff8
 635 #define M_WATCH_R               0x00000002
 636 #define M_WATCH_W               0x00000001
 637
 638
 639 /* TLB entries */
 640 #define M_TLBHI_ASID            _MM_MAKEMASK(0,8)
 641 #define M_TLBHI_VPN2            _MM_MAKEMASK(27,13)
 642
 643 #define M_TLBLO_G               _MM_MAKEMASK1(0)
 644 #define M_TLBLO_V               _MM_MAKEMASK1(1)
 645 #define M_TLBLO_D               _MM_MAKEMASK1(2)
 646
 647 #define S_TLBLO_CALG            3
 648 #define M_TLBLO_CALG            _MM_MAKEMASK(3,S_TLBLO_CALG)
 649 #define V_TLBLO_CALG(x)         _MM_MAKEVALUE(x,S_TLBLO_CALG)
 650 #define G_TLBLO_CALG(x)         _MM_GETVALUE(x,S_TLBLO_CALG,M_TLBLO_CALG)
 651
 652 #define K_CALG_COH_EXCL1_NOL2   0
 653 #define K_CALG_COH_SHRL1_NOL2   1
 654 #define K_CALG_UNCACHED         2
 655 #define K_CALG_NONCOHERENT      3
 656 #define K_CALG_COH_EXCL         4
 657 #define K_CALG_COH_SHAREABLE    5
 658 #define K_CALG_NOTUSED          6
 659 #define K_CALG_UNCACHED_ACCEL   7
 660
 661 #define S_TLBLO_PFNMASK         6
 662 #define M_TLBLO_PFNMASK         _MM_MAKEMASK(24,S_TLBLO_PFNMASK)
 663 #define V_TLBLO_PFNMASK(x)      _MM_MAKEVALUE(x,S_TLBLO_PFNMASK)
 664 #define G_TLBLO_PFNMASK(x)      _MM_GETVALUE(x,S_TLBLO_PFNMASK,M_TLBLO_PFNMASK)
 665
 666
 667
 668 #endif /* _SB_MIPS_H */