GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / cfe / cfe / arch / mips / board / vcs / include / bsp_config.h
blob02ef11bbfca78b009f438a08a926e741bd543ad9
1 /* *********************************************************************
2 * Broadcom Common Firmware Environment (CFE)
3 *
4 * BSP Configuration file File: bsp_config.h
5 *
6 * This module contains global parameters and conditional
7 * compilation settings for building CFE.
8 *
9 * Author: Mitch Lichtenberg (mpl@broadcom.com)
11 *********************************************************************
13 * Copyright 2000,2001,2002,2003
14 * Broadcom Corporation. All rights reserved.
16 * This software is furnished under license and may be used and
17 * copied only in accordance with the following terms and
18 * conditions. Subject to these conditions, you may download,
19 * copy, install, use, modify and distribute modified or unmodified
20 * copies of this software in source and/or binary form. No title
21 * or ownership is transferred hereby.
23 * 1) Any source code used, modified or distributed must reproduce
24 * and retain this copyright notice and list of conditions
25 * as they appear in the source file.
27 * 2) No right is granted to use any trade name, trademark, or
28 * logo of Broadcom Corporation. The "Broadcom Corporation"
29 * name may not be used to endorse or promote products derived
30 * from this software without the prior written permission of
31 * Broadcom Corporation.
33 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
34 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
35 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
36 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
37 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
38 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
39 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
40 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
41 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
42 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
43 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
44 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
45 * THE POSSIBILITY OF SUCH DAMAGE.
46 ********************************************************************* */
50 #define CFG_BOARDNAME "VCS" /* Name of board */
51 //#define CFG_CPU_SPEED 800000000 /* 800MHz */
52 #define CFG_CPU_SPEED 500000 /* 500KHz for the func simulator */
54 #define CFG_INIT_L1 1 /* initialize the L1 cache */
55 #define CFG_INIT_L2 1 /* initialize the L2 cache */
56 #define CFG_INIT_DRAM 1 /* initialize DRAM controller */
58 #define CFG_NETWORK 0 /* define to include network support */
60 #define CFG_UI 1 /* Define to enable user interface */
62 #define CFG_MULTI_CPUS 0 /* Define to include multiple CPU support */
64 #define CFG_HEAP_SIZE 32 /* heap size in kilobytes */
65 #define CFG_STACK_SIZE 1024 /* stack size in bytes */
69 * These parameters control the flash driver's sector buffer.
70 * If you write environment variables or make small changes to
71 * flash sectors from user applications, you
72 * need to have the heap big enough to store a temporary sector
73 * for merging in small changes to flash sectors, so you
74 * should set CFG_FLASH_ALLOC_SECTOR_BUFFER in that case.
75 * Otherwise, you can provide an address in unallocated memory
76 * of where to place the sector buffer.
79 #define CFG_FLASH_ALLOC_SECTOR_BUFFER 0 /* '1' to allocate sector buffer from the heap */
80 #define CFG_FLASH_SECTOR_BUFFER_ADDR (100*1024*1024-128*1024) /* 100MB - 128K */
81 #define CFG_FLASH_SECTOR_BUFFER_SIZE (128*1024)
84 * The flash staging buffer is where we store a flash image before we write
85 * it to the flash. It's too big for the heap.
88 #define CFG_FLASH_STAGING_BUFFER_ADDR (100*1024*1024)
89 #define CFG_FLASH_STAGING_BUFFER_SIZE (4*1024*1024)
92 * These parameters control the default DRAM init table
93 * inside of sb1250_draminit.c.
97 #define CFG_DRAM_ECC 0 /* Turn on to enable ECC */
98 #define CFG_DRAM_SMBUS_CHANNEL 0 /* SMBus channel for memory SPDs */
99 #define CFG_DRAM_SMBUS_BASE 0x54 /* starting SMBus device base */
100 #define CFG_DRAM_SMBUS_NDIMMS 4 /* total number of DIMM slots */
101 #define CFG_DRAM_BLOCK_SIZE 32 /* don't interleave columns */
102 #define CFG_DRAM_CSINTERLEAVE 0 /* Use 0,1, or 2. Max number of address
103 bits allowed for chip select
104 interleaving. Only matching dimms
105 will be interleaved. 3 outcomes:
106 no interleaving, interleave CS 0 &
107 1, and interleave CS 0,1,2 & 3. */
109 #define CFG_SERIAL_BAUD_RATE 921600 /* really, really fast for verilog */
111 #ifndef _VERILOG_
112 #define _VERILOG_
113 #endif
114 #ifndef _FASTEMUL_
115 #define _FASTEMUL_
116 #endif