1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * Board-specific initialization File: PTSWARM_INIT.S
6 * This module contains the assembly-language part of the init
7 * code for this board support package. The routine
8 * "board_earlyinit" lives here.
10 * Author: Mitch Lichtenberg (mpl@broadcom.com)
12 * modification history
13 * --------------------
14 * 01f,09apr03,gtb Added hardwired memory init table to set memclk to 133 MHz
15 * 01e,02feb02,jmb Incorporate Mitch's 1.0.27 DRAM patches from CSWARM
16 * 01d,07jan02,jmb Resizing of CS1 space
17 * 01c,20dec01,jmb Just resize ROM space after CFE starts
18 * 01b,19dec01,jmb Add function to remap ROM space after CFE starts
19 * 01a,14dec01,jmb Ported from cswarm_init.S.
20 * Added configuration of I/O bus for the
21 * external UART. Deleted unused chip selects.
23 *********************************************************************
25 * Copyright 2000,2001,2002,2003
26 * Broadcom Corporation. All rights reserved.
28 * This software is furnished under license and may be used and
29 * copied only in accordance with the following terms and
30 * conditions. Subject to these conditions, you may download,
31 * copy, install, use, modify and distribute modified or unmodified
32 * copies of this software in source and/or binary form. No title
33 * or ownership is transferred hereby.
35 * 1) Any source code used, modified or distributed must reproduce
36 * and retain this copyright notice and list of conditions
37 * as they appear in the source file.
39 * 2) No right is granted to use any trade name, trademark, or
40 * logo of Broadcom Corporation. The "Broadcom Corporation"
41 * name may not be used to endorse or promote products derived
42 * from this software without the prior written permission of
43 * Broadcom Corporation.
45 * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
46 * IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
47 * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
48 * PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
49 * SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
50 * PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
51 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
52 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
53 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
54 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
55 * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
56 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
57 * THE POSSIBILITY OF SUCH DAMAGE.
58 ********************************************************************* */
62 #include "sb1250_genbus.h"
63 #include "sb1250_regs.h"
64 #include "sb1250_scd.h"
65 #include "bsp_config.h"
67 #include "sb1250_draminit.h"
68 #include "../dev/ns16550.h"
70 #if defined(_PTSWARM_DIAG_CFG_)
71 #undef SERIAL_PORT_LEDS
72 #define SERIAL_PORT_LEDS
76 /* *********************************************************************
78 ********************************************************************* */
82 #define CALLKSEG1(x) la k0,x ; or k0,K1BASE ; jal k0
84 #define CALLKSEG1(x) jal x
88 /* *********************************************************************
91 * Initialize board registers. This is the earliest
92 * time the BSP gets control. This routine cannot assume that
93 * memory is operational, and therefore all code in this routine
94 * must run from registers only. The $ra register must not
95 * be modified, as it contains the return address.
97 * This routine will be called from uncached space, before
98 * the caches are initialized. If you want to make
99 * subroutine calls from here, you must use the CALLKSEG1 macro.
101 * Among other things, this is where the GPIO registers get
102 * programmed to make on-board LEDs function, or other startup
103 * that has to be done before anything will work.
110 ********************************************************************* */
112 LEAF(board_earlyinit)
115 # Configure the GPIOs
118 # 1, 2, and 5 are interrupts
119 # remainder are input (unused)
122 li t0,PHYS_TO_K1(A_GPIO_DIRECTION)
123 li t1,GPIO_OUTPUT_MASK
126 li t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
127 li t1,GPIO_INTERRUPT_MASK
131 # Turn on the diagnostic LED
133 li t0,PHYS_TO_K1(A_GPIO_PIN_SET)
134 li t1,M_GPIO_DEBUG_LED
141 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS))
142 li t1,LEDS_PHYS >> S_IO_ADDRBASE
143 sd t1,R_IO_EXT_START_ADDR(t0)
145 li t1,LEDS_SIZE-1 /* Needs to be 1 smaller, se UM for details */
146 sd t1,R_IO_EXT_MULT_SIZE(t0)
149 sd t1,R_IO_EXT_TIME_CFG0(t0)
152 sd t1,R_IO_EXT_TIME_CFG1(t0)
155 sd t1,R_IO_EXT_CFG(t0)
160 # Configure the alternate boot ROM
163 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
165 li t1,ALT_BOOTROM_PHYS >> S_IO_ADDRBASE
166 sd t1,R_IO_EXT_START_ADDR(t0)
168 li t1,ALT_BOOTROM_SIZE-1
169 sd t1,R_IO_EXT_MULT_SIZE(t0)
171 li t1,ALT_BOOTROM_TIMING0
172 sd t1,R_IO_EXT_TIME_CFG0(t0)
174 li t1,ALT_BOOTROM_TIMING1
175 sd t1,R_IO_EXT_TIME_CFG1(t0)
177 li t1,ALT_BOOTROM_CONFIG
178 sd t1,R_IO_EXT_CFG(t0)
181 # Configure I/O bus for an external UART
184 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(UART_CS))
186 li t1, UART_PHYS >> S_IO_ADDRBASE
187 sd t1,R_IO_EXT_START_ADDR(t0)
190 sd t1,R_IO_EXT_MULT_SIZE(t0)
192 li t1, (UART_TIMING0)
193 sd t1,R_IO_EXT_TIME_CFG0(t0)
195 li t1, (UART_TIMING1)
196 sd t1,R_IO_EXT_TIME_CFG1(t0)
199 sd t1,R_IO_EXT_CFG(t0)
201 #ifdef SERIAL_PORT_LEDS
204 * Initialize the UART well enough to output characters.
206 li t0, PHYS_TO_K1(UART_PHYS)
209 sb t1, R_UART_CFCR(t0)
211 li t1, BRTC(CFG_SERIAL_BAUD_RATE)
212 sb t1, R_UART_DATA(t0)
214 sb t1, R_UART_IER(t0)
217 sb t1, R_UART_CFCR(t0)
219 li t1, (MCR_DTR | MCR_RTS | MCR_IENABLE)
220 sb t1, R_UART_MCR(t0)
223 sb t1, R_UART_IER(t0)
226 sb t1, R_UART_FIFO(t0)
233 li t1, (FIFO_ENABLE | FIFO_RCV_RST | FIFO_XMT_RST \
235 sb t1, R_UART_FIFO(t0)
242 /* if (value & MASK) != MASK, write 0 to fifo reg. */
243 lb t1, R_UART_IIR(t0)
244 andi t1, t1, IIR_FIFO_MASK
245 xori t1, t1, IIR_FIFO_MASK
249 sb t1, R_UART_FIFO(t0)
258 /* *********************************************************************
261 * Return the address of the DRAM information table
267 * v0 - DRAM info table, return 0 to use default table
268 ********************************************************************* */
269 /* Use hard wired table */
270 #define _HARDWIRED_MEMORY_TABLE 1
271 #define CFG_DRAM_tROUNDTRIP DRT10(2,0)
272 /* CFG_DRAM_MIN_tMEMCLK must be set to 7. Some DIMMS cause diag failures
273 when the memclk is at 125 MHz but pass at 100 MHz or 133 MHz. Setting to 7 causes
274 memclk to be 133 MHz*/
275 #define CFG_DRAM_MIN_tMEMCLK DRT10(7,0)
276 #define DEVADDR (CFG_DRAM_SMBUS_BASE)
277 #define DEFCHAN (CFG_DRAM_SMBUS_CHANNEL)
281 #define LOADREL(reg,label) \
290 #define LOADREL(reg,label) \
298 #ifdef _HARDWIRED_MEMORY_TABLE
301 move v0,zero # auto configure
311 DRAM_GLOBALS(CFG_DRAM_INTERLEAVE) /* do port interleaving if possible */
314 * Memory channel 0: Configure via SMBUS, Automatic Timing
315 * Assumes SMBus device numbers are arranged such
316 * that the first two addresses are CS0,1 and CS2,3 on MC0
317 * and the second two addresses are CS0,1 and CS2,3 on MC1
319 DRAM_CHAN_CFG2(MC_CHAN0, CFG_DRAM_MIN_tMEMCLK, CFG_DRAM_tROUNDTRIP, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
320 DRAM_CHAN_CLKCFG(0x08, 0x08, 0x08, 0x0f, 0x0f, 0x0f)
322 DRAM_CS_SPD(MC_CS0, 0, DEFCHAN, DEVADDR+0)
323 DRAM_CS_SPD(MC_CS2, 0, DEFCHAN, DEVADDR+1)
326 * Memory channel 1: Configure via SMBUS
330 DRAM_CHAN_CFG2(MC_CHAN1, CFG_DRAM_MIN_tMEMCLK, CFG_DRAM_tROUNDTRIP, DRAM_TYPE_SPD, CASCHECK, CFG_DRAM_BLOCK_SIZE, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
331 DRAM_CHAN_CLKCFG(0x08, 0x08, 0x08, 0x0f, 0x0f, 0x0f)
333 DRAM_CS_SPD(MC_CS0, 0, DEFCHAN, DEVADDR+2)
334 DRAM_CS_SPD(MC_CS2, 0, DEFCHAN, DEVADDR+3)
342 #ifdef SERIAL_PORT_LEDS
343 /* *********************************************************************
344 * BOARD_UART_TXCHAR(x)
346 * Transmit one character out the UART on the GENERIC bus.
349 * a0 - 8 bit character value.
356 ********************************************************************* */
358 LEAF(board_uart_txchar)
360 # Wait until there is space in the transmit buffer.
362 li t0, PHYS_TO_K1(UART_PHYS)
364 1: lb t1, R_UART_LSR(t0)
365 andi t1, t1, LSR_TXRDY
368 # OK, now send a character.
370 sb a0, R_UART_DATA(t0)
376 END(board_uart_txchar)
380 /* *********************************************************************
383 * Set LEDs for boot-time progress indication. Not used if
384 * the board does not have progress LEDs. This routine
385 * must not call any other routines, since it may be invoked
386 * either from KSEG0 or KSEG1 and it may be invoked
387 * whether or not the icache is operational.
390 * a0 - LED value (8 bits per character, 4 characters)
397 ********************************************************************* */
400 #define LED_CHAR0 (32+8*3)
401 #define LED_CHAR1 (32+8*2)
402 #define LED_CHAR2 (32+8*1)
403 #define LED_CHAR3 (32+8*0)
405 #ifdef SERIAL_PORT_LEDS
406 #define OUTPUT_CHAR(offset) \
407 li t0, PHYS_TO_K1(LEDS_PHYS) ; \
408 sb a0, offset(t0) ; \
409 bal board_uart_txchar
411 #define OUTPUT_CHAR(offset) \
412 li t0, PHYS_TO_K1(LEDS_PHYS) ; \
421 #ifdef SERIAL_PORT_LEDS
423 bal board_uart_txchar
428 OUTPUT_CHAR(LED_CHAR0)
431 OUTPUT_CHAR(LED_CHAR1)
434 OUTPUT_CHAR(LED_CHAR2)
437 OUTPUT_CHAR(LED_CHAR3)
439 #ifdef SERIAL_PORT_LEDS
441 bal board_uart_txchar
443 bal board_uart_txchar
445 bal board_uart_txchar
453 /* *********************************************************************
456 * Change the size of the bootrom area.
457 * This routine is called only after CFE has been relocated to DRAM
458 * and is executing from DRAM. After that point, the boot rom
459 * is serving as a flash file storage area. Note: this could be
460 * done in board_earlyinit since we're not changing the base address.
470 ********************************************************************* */
473 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(BOOTROM_CS))
476 sd t1,R_IO_EXT_MULT_SIZE(t0)
481 /* *********************************************************************
484 * Change the size of the flash area.
485 * Usually CS1 is the promice, but if it's not, the flash is here.
495 ********************************************************************* */
498 li t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
501 sd t1,R_IO_EXT_MULT_SIZE(t0)