release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/pt1120/src/pt1120_pci.c

   1 /*  *********************************************************************
   2     *  Broadcom Common Firmware Environment (CFE)
   3     *
   4     *  Board device initialization              File: pt1120_pci.c
   5     *
   6     *  This is the part of the board support package for boards
   7     *  that support PCI. It describes the board-specific slots/devices
   8     *  and wiring thereof.
   9     *
  10     *********************************************************************
  11     *
  12     *  Copyright 2000,2001,2002
  13     *  Broadcom Corporation. All rights reserved.
  14     *
  15     *  This software is furnished under license and may be used and
  16     *  copied only in accordance with the following terms and
  17     *  conditions.  Subject to these conditions, you may download,
  18     *  copy, install, use, modify and distribute modified or unmodified
  19     *  copies of this software in source and/or binary form.  No title
  20     *  or ownership is transferred hereby.
  21     *
  22     *  1) Any source code used, modified or distributed must reproduce
  23     *     and retain this copyright notice and list of conditions as
  24     *     they appear in the source file.
  25     *
  26     *  2) No right is granted to use any trade name, trademark, or
  27     *     logo of Broadcom Corporation. Neither the "Broadcom
  28     *     Corporation" name nor any trademark or logo of Broadcom
  29     *     Corporation may be used to endorse or promote products
  30     *     derived from this software without the prior written
  31     *     permission of Broadcom Corporation.
  32     *
  33     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  34     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  35     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  37     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  38     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  39     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  41     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  42     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  43     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  44     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  45     *     THE POSSIBILITY OF SUCH DAMAGE.
  46     ********************************************************************* */
  47
  48 #include "lib_types.h"
  49
  50 #include "pcireg.h"
  51 #include "pcivar.h"
  52
  53
  54 /* PCI interrupt mapping on the BCM912500 (SWARM) board:
  55    Only device ids 5 and 6 are implemented as PCI connectors, and
  56    the only on-board device has id 7 (USB bridge).
  57
  58    Slot    IDSEL   DevID  INT{A,B,C,D}   shift
  59   (PHB)      -       0       {A,-,-,-}     0
  60   (LHB)      -       1       {-,-,-,-}     0
  61     0       16       5       {A,B,C,D}     0 (identity)
  62     1       17       6       {B,C,D,A}     1 (A->B, B->C, C->D, D->A)
  63   (USB)     18       7       {C,D,-,-}     2 (A->C, B->D, C->A, D->B)
  64     -                                      3 (A->D, B->A, C->B, D->C)
  65
  66    Device 1 is the LDT host bridge.  By giving it a shift of 0,
  67    the normal rotation algorithm gives the correct result for devices
  68    on the secondary bus of the LDT host bridge (bus 1).  Firmware
  69    must program the API 10ll LDT-PCI bridge so that the normal
  70    rotation algorithm gives correct results for its secondary (bus 2):
  71
  72     0       16       0       {A,B,C,D}     0 (identity)
  73     1       17       1       {B,C,D,A}     1 (A->B, B->C, C->D, D->A)
  74 */
  75
  76 extern int _pciverbose;
  77
  78 /* Return the base shift of a slot or device on the motherboard.
  79    This is board specific, for the SWARM (BCM912500E) only. */
  80 uint8_t
  81 pci_int_shift_0(pcitag_t tag)
  82 {
  83     int bus, device;
  84
  85     pci_break_tag(tag, &bus, &device, NULL);
  86
  87     if (bus != 0)
  88         return 0;
  89     switch (device) {
  90     case 0:
  91         return 0;
  92     case 5: case 6: case 7:
  93         return ((device - 5) % 4);
  94     default:
  95         return 0;
  96     }
  97 }
  98
  99 /* Return the mapping of a SWARM device/function interrupt to an
 100    interrupt line.  For the SB-1250, return 1-4 to indicate the
 101    pci_inta - pci_intd inputs to the interrupt mapper, respectively,
 102    or 0 if there is no mapping.  This is board specific, and the
 103    version below is for SWARM (BCM912500E), 32-bit slots only. */
 104 uint8_t
 105 pci_int_map_0(pcitag_t tag)
 106 {
 107     pcireg_t data;
 108     int pin, bus, device;
 109
 110     data = pci_conf_read(tag, PCI_BPARAM_INTERRUPT_REG);
 111     pin = PCI_INTERRUPT_PIN(data);
 112     if (pin == 0) {
 113         /* No IRQ used. */
 114         return 0;
 115     }
 116     if (pin > 4) {
 117         if (_pciverbose >= 1)
 118             pci_tagprintf(tag, "pci_map_int: bad interrupt pin %d\n", pin);
 119         return 0;
 120     }
 121
 122     pci_break_tag(tag, &bus, &device, NULL);
 123
 124     if (bus != 0)
 125         return 0;
 126
 127     switch (device) {
 128     case 0:
 129     case 5: case 6: case 7:
 130         return (((pin - 1) + pci_int_shift_0(tag)) % 4) + 1;
 131     default:
 132         return 0;
 133     }
 134 }