release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/pt1120/include/pt1120.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  PT1120 Definitions       File: pt1120.h
   5     *  PT1120 is a slightly modified version of PTSWARM, set up to be
   6     *  a Production Tester, hence PT.
   7     *
   8     *  This file contains I/O, chip select, and GPIO assignments
   9     *  for the BCM12500 production test board.
  10     *
  11     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  12     *
  13     * modification history
  14     * --------------------
  15     * 01a,26jun02,gtb  created for  pt1120 board.
  16     *                           Copy of ptswarm.h
  17     *
  18     *
  19     *********************************************************************
  20     *
  21     *  Copyright 2000,2001
  22     *  Broadcom Corporation. All rights reserved.
  23     *
  24     *  This software is furnished under license and may be used and
  25     *  copied only in accordance with the following terms and
  26     *  conditions.  Subject to these conditions, you may download,
  27     *  copy, install, use, modify and distribute modified or unmodified
  28     *  copies of this software in source and/or binary form.  No title
  29     *  or ownership is transferred hereby.
  30     *
  31     *  1) Any source code used, modified or distributed must reproduce
  32     *     and retain this copyright notice and list of conditions as
  33     *     they appear in the source file.
  34     *
  35     *  2) No right is granted to use any trade name, trademark, or
  36     *     logo of Broadcom Corporation. Neither the "Broadcom
  37     *     Corporation" name nor any trademark or logo of Broadcom
  38     *     Corporation may be used to endorse or promote products
  39     *     derived from this software without the prior written
  40     *     permission of Broadcom Corporation.
  41     *
  42     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  43     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  44     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  45     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  46     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  47     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  48     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  49     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  50     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  51     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  52     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  53     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  54     *     THE POSSIBILITY OF SUCH DAMAGE.
  55     ********************************************************************* */
  56
  57 /*
  58  * I/O Address assignments for the PT1120 board
  59  *
  60  * Summary of address map:
  61  *
  62  * Address         Size   CSel    Description
  63  * --------------- ----   ------  --------------------------------
  64  * 0x1FC00000      16MB    CS0    Boot ROM
  65  * 0x1CC00000       2MB    CS1    Alternate boot ROM
  66  * 0x1B000000      64KB    CS2    External UART
  67  * 0x1B0A0000      64KB    CS3    LED display
  68  *                         CS4    Unused
  69  *                         CS5    Unused
  70  *                         CS6    Unused
  71  *                         CS7    Unused
  72  *
  73  * GPIO assignments
  74  *
  75  * GPIO#    Direction   Description
  76  * -------  ---------   ------------------------------------------
  77  * GPIO0    Output      Debug LED
  78  * GPIO1    Input       UART interrupt              (interrupt)
  79  * GPIO2    Input       PHY interrupt               (interrupt)
  80  * GPIO3    N/A         fpga interface
  81  * GPIO4    N/A         fpga interface
  82  * GPIO5    Input       Temperature Sensor Alert    (interrupt)
  83  * GPIO6    N/A         fpga interface
  84  * GPIO7    N/A         fpga interface
  85  * GPIO8    N/A         fpga interface
  86  * GPIO9    N/A         fpga interface
  87  * GPIO10   N/A         fpga interface
  88  * GPIO11   N/A         fpga interface
  89  * GPIO12   N/A         fpga interface
  90  * GPIO13   N/A         fpga interface
  91  * GPIO14   N/A         fpga interface
  92  * GPIO15   N/A         fpga interface
  93  */
  94
  95 /*  *********************************************************************
  96     *  Macros
  97     ********************************************************************* */
  98
  99 #define MB (1024*1024)
 100 #define K64 65536
 101 #define NUM64K(x) (((x)+(K64-1))/K64)
 102
 103
 104 /*  *********************************************************************
 105     *  GPIO pins
 106     ********************************************************************* */
 107
 108 #define GPIO_DEBUG_LED          0
 109 #define GPIO_UART_INT           1
 110 #define GPIO_PHY_INT            2
 111 #define GPIO_RTC_OUT_INT         3
 112 #define GPIO_TEMP_SENSOR_INT    5
 113
 114 #define M_GPIO_DEBUG_LED        _SB_MAKEMASK1(GPIO_DEBUG_LED)
 115 #define M_GPIO_RTC_OUT_INT      _SB_MAKEMASK1(GPIO_RTC_OUT_INT)
 116
 117 #define GPIO_OUTPUT_MASK (_SB_MAKEMASK1(GPIO_DEBUG_LED))
 118
 119 #define GPIO_INTERRUPT_MASK ((V_GPIO_INTR_TYPEX(GPIO_PHY_INT,K_GPIO_INTR_LEVEL)) | \
 120                              (V_GPIO_INTR_TYPEX(GPIO_UART_INT,K_GPIO_INTR_LEVEL))| \
 121                              (V_GPIO_INTR_TYPEX(GPIO_TEMP_SENSOR_INT,K_GPIO_INTR_LEVEL))| \
 122                              (V_GPIO_INTR_TYPEX(GPIO_RTC_OUT_INT,K_GPIO_INTR_LEVEL)))
 123
 124
 125 /*  *********************************************************************
 126     *  Generic Bus
 127     ********************************************************************* */
 128
 129 /*
 130  * Boot ROM:  Using default parameters until CFE has been copied from
 131  * ROM to RAM and is executing in RAM
 132  */
 133 #define BOOTROM_CS              0
 134 #define BOOTROM_SIZE            NUM64K(16*MB)   /* size of boot ROM */
 135 #define BOOTROM_PHYS            0x1FC00000      /* address of boot ROM (CS0) */
 136 #define BOOTROM_NCHIPS          8
 137 #define BOOTROM_CHIPSIZE        2*MB
 138
 139
 140 #define ALT_BOOTROM_CS          1
 141 #define ALT_BOOTROM_PHYS        0x1CC00000      /* address of alternate boot ROM (CS1) */
 142 #define ALT_BOOTROM_SIZE        NUM64K(2*MB)    /* size of alternate boot ROM */
 143 #define ALT_BOOTROM_TIMING0     V_IO_ALE_WIDTH(4) | \
 144                                 V_IO_ALE_TO_CS(2) | \
 145                                 V_IO_CS_WIDTH(24) | \
 146                                 V_IO_RDY_SMPLE(1)
 147 #define ALT_BOOTROM_TIMING1     V_IO_ALE_TO_WRITE(7) | \
 148                                 V_IO_WRITE_WIDTH(7) | \
 149                                 V_IO_IDLE_CYCLE(6) | \
 150                                 V_IO_CS_TO_OE(0) | \
 151                                 V_IO_OE_TO_CS(0)
 152 #define ALT_BOOTROM_CONFIG      V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 153 #define ALT_BOOTROM_NCHIPS      1
 154 #define ALT_BOOTROM_CHIPSIZE    2*MB
 155
 156 /*
 157  * External UART:  non-multiplexed, byte width, no parity, no ack
 158  */
 159 #define UART_CS         2
 160 #define UART_PHYS       0x1B000000      /* address of UART (CS2) */
 161 #define UART_SIZE       NUM64K(8)       /* size allocated for UART access. minimum is 64KB */
 162 #define UART_TIMING0    V_IO_ALE_WIDTH(4) | \
 163                         V_IO_ALE_TO_CS(2) | \
 164                         V_IO_CS_WIDTH(24) | \
 165                         V_IO_RDY_SMPLE(1)
 166 #define UART_TIMING1    V_IO_ALE_TO_WRITE(7) | \
 167                         V_IO_WRITE_WIDTH(7) | \
 168                         V_IO_IDLE_CYCLE(6) | \
 169                         V_IO_CS_TO_OE(0) | \
 170                         V_IO_OE_TO_CS(0)
 171 #define UART_CONFIG     V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 172
 173 /*
 174  * LEDs:  non-multiplexed, byte width, no parity, no ack
 175  */
 176 #define LEDS_CS                 3
 177 #define LEDS_PHYS               0x1B0A0000
 178 #define LEDS_SIZE               NUM64K(4)
 179 #define LEDS_TIMING0            V_IO_ALE_WIDTH(4) | \
 180                                 V_IO_ALE_TO_CS(2) | \
 181                                 V_IO_CS_WIDTH(13) | \
 182                                 V_IO_RDY_SMPLE(1)
 183 #define LEDS_TIMING1            V_IO_ALE_TO_WRITE(2) | \
 184                                 V_IO_WRITE_WIDTH(8) | \
 185                                 V_IO_IDLE_CYCLE(6) | \
 186                                 V_IO_CS_TO_OE(0) | \
 187                                 V_IO_OE_TO_CS(0)
 188 #define LEDS_CONFIG             V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 189
 190
 191 /*  *********************************************************************
 192     *  SMBus Devices
 193     ********************************************************************* */
 194
 195 #define TEMPSENSOR_SMBUS_CHAN   0
 196 #define TEMPSENSOR_SMBUS_DEV    0x2A
 197 #define DRAM_SMBUS_CHAN         0
 198 #define DRAM_SMBUS_DEV          0x54
 199 #define BIGEEPROM_SMBUS_CHAN    0
 200 #define BIGEEPROM_SMBUS_DEV     0x50
 201
 202 /*
 203 #define X1240_SMBUS_CHAN        1
 204 #define X1240_SMBUS_DEV         0x50
 205 */
 206 #define M41T81_SMBUS_CHAN       1
 207 #define M41T81_SMBUS_DEV        0x68