release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/p6064/src/pci_machdep.c

   1 /*
   2  * p6032/pci_machdep.c: Machine-specific functions for PCI autoconfiguration.
   3  *
   4  * Copyright (c) 2000-2001, Algorithmics Ltd.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the "Free MIPS" License Agreement, a copy of
   8  * which is available at:
   9  *
  10  *  http://www.algor.co.uk/ftp/pub/doc/freemips-license.txt
  11  *
  12  * You may not, however, modify or remove any part of this copyright
  13  * message if this program is redistributed or reused in whole or in
  14  * part.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * "Free MIPS" License for more details.
  20  */
  21
  22 #include "cfe_pci.h"
  23 #include "sbmips.h"
  24 #include "pcivar.h"
  25 #include "pcireg.h"
  26 #include "sbd.h"
  27
  28 #define PCI_MISC_LTIM_SHIFT                     8
  29 #define PCI_MISC_LTIM_MASK                      0xff
  30 #define PCI_MISC_LTIM(mr) \
  31             (((mr) >> PCI_MISC_LTIM_SHIFT) & PCI_MISC_LTIM_MASK)
  32 #define PCI_MISC_LTIM_SET(mr,v) \
  33             (mr) = ((mr) & ~(PCI_MISC_LTIM_MASK << PCI_MISC_LTIM_SHIFT)) | \
  34                 ((v) << PCI_MISC_LTIM_SHIFT)
  35
  36
  37 /* default PCI mem regions in PCI space */
  38 #define PCI_MEM_SPACE_PCI_BASE          0x00000000
  39 #define PCI_LOCAL_MEM_PCI_BASE          0x80000000
  40 #define PCI_LOCAL_MEM_ISA_BASE          0x00800000
  41
  42 /* soft versions of above */
  43 static pcireg_t const pci_mem_space = PCI_MEM_SPACE;    /* CPU base for access to mapped PCI memory */
  44 static pcireg_t pci_mem_space_pci_base;                 /* PCI mapped memory base */
  45 static pcireg_t pci_local_mem_pci_base;                 /* PCI address of local memory */
  46 static pcireg_t pci_local_mem_isa_base;                 /* PCI address of ISA accessible local memory */
  47
  48 static pcireg_t const pci_io_space = PCI_IO_SPACE;      /* CPU base for access to mapped PCI IO */
  49 static pcireg_t const pci_io_space_pci_base = 0;        /* PCI mapped IO base */
  50
  51 /* PCI mem space allocation */
  52 pcireg_t minpcimemaddr;
  53 pcireg_t nextpcimemaddr;
  54 pcireg_t minpcimemaddr;
  55 pcireg_t maxpcimemaddr;
  56
  57
  58 /* PCI i/o space allocation */
  59 pcireg_t minpciioaddr;
  60 pcireg_t maxpciioaddr;
  61 pcireg_t nextpciioaddr;
  62
  63 typedef long hsaddr_t;
  64
  65 #define hs_write8(a,b) *((volatile uint8_t *) (a)) = (b)
  66 #define hs_write16(a,b) *((volatile uint16_t *) (a)) = (b)
  67 #define hs_write32(a,b) *((volatile uint32_t *) (a)) = (b)
  68 #define hs_write64(a,b) *((volatile uint32_t *) (a)) = (b)
  69 #define hs_read8(a) *((volatile uint8_t *) (a))
  70 #define hs_read16(a) *((volatile uint16_t *) (a))
  71 #define hs_read32(a) *((volatile uint32_t *) (a))
  72 #define hs_read64(a) *((volatile uint64_t *) (a))
  73
  74
  75 static const struct pci_bus bonito_pci_bus = {
  76         0,              /* minimum grant */
  77         255,            /* maximum latency */
  78         0,              /* devsel time = fast */
  79         0,              /* we don't support fast back-to-back */
  80         0,              /* we don't support prefetch */
  81         0,              /* we don't support 66 MHz */
  82         0,              /* we don't support 64 bits */
  83         4000000,        /* bandwidth: in 0.25us cycles / sec */
  84         1               /* initially one device on bus (i.e. us) */
  85 };
  86
  87 #ifdef _CFE_
  88 const cons_t pci_optnames[] = {
  89     {"verbose",PCI_FLG_VERBOSE},
  90     {NULL,0}};
  91 #endif
  92
  93 extern int _pciverbose;
  94
  95 #define MAXBUS  3
  96 const int _pci_maxbus = MAXBUS;         /* maximum # buses we support */
  97 static int _pci_nbus = 0;
  98 static struct pci_bus _pci_bus[MAXBUS];
  99
 100 /* Access functions */
 101
 102 /* The following must either fail or return the next sequential bus
 103    number to make secondary/subordinate numbering work correctly. */
 104 int
 105 pci_nextbus (int port)
 106 {
 107     int bus = _pci_nbus;
 108
 109     if (bus >= MAXBUS)
 110         return -1;
 111     _pci_nbus++;
 112     return bus;
 113 }
 114
 115 int
 116 pci_maxbus (int port)
 117 {
 118     return _pci_nbus - 1;
 119 }
 120
 121 struct pci_bus *
 122 pci_businfo (int port, int bus)
 123 {
 124     return (bus < _pci_nbus ? &_pci_bus[bus] : NULL);
 125 }
 126
 127 /*
 128  * PCI address resources.
 129  * NB: initial limits for address allocation are assumed to be aligned
 130  * appropriately for PCI bridges (4K boundaries for I/O, 1M for memory).
 131  */
 132
 133 pcireg_t
 134 pci_minmemaddr (int port)
 135 {
 136     return minpcimemaddr;
 137 }
 138
 139 pcireg_t
 140 pci_maxmemaddr (int port)
 141 {
 142     return maxpcimemaddr;
 143 }
 144
 145 pcireg_t
 146 pci_minioaddr (int port)
 147 {
 148     return minpciioaddr;
 149 }
 150
 151 pcireg_t
 152 pci_maxioaddr (int port)
 153 {
 154     return maxpciioaddr;
 155 }
 156
 157 static char * const _bonito = (char * const) PHYS_TO_K1(BONITO_BASE);
 158
 159 static int pcimaster;
 160 static int pcireserved;
 161
 162 /*
 163  * Called to initialise the bridge at the beginning of time
 164  */
 165 int
 166 pci_hwinit (int port, pci_flags_t flags)
 167 {
 168     int initialise = 1;
 169
 170     pcimaster = 1;
 171     pcireserved = 0;
 172
 173
 174     _pci_bus[0] = bonito_pci_bus;
 175     _pci_nbus = 1;
 176
 177     if (initialise && pcimaster) {
 178         /*
 179          * We are initialising and we are the bus master
 180          * so we get to define the mappings
 181          */
 182         pci_mem_space_pci_base = PCI_MEM_SPACE_PCI_BASE;
 183
 184         pci_local_mem_pci_base = PCI_LOCAL_MEM_PCI_BASE;
 185         pci_local_mem_isa_base = PCI_LOCAL_MEM_ISA_BASE;
 186
 187         /* point to start and end of region (leaving bottom 16M for ISA) */
 188         minpcimemaddr  = pci_mem_space_pci_base;
 189         if (minpcimemaddr < 0x1000000)
 190             minpcimemaddr = 0x1000000;
 191         nextpcimemaddr = pci_mem_space_pci_base + PCI_MEM_SPACE_SIZE;
 192         maxpcimemaddr = nextpcimemaddr;
 193
 194         printf("minpcimem=%08X next=%08X\n",minpcimemaddr,nextpcimemaddr);
 195
 196         /* leave 64KB at beginning of PCI i/o space for ISA bridge */
 197         minpciioaddr  = pci_io_space_pci_base;
 198         if (minpciioaddr < 0x10000)
 199             minpciioaddr = 0x10000;
 200         nextpciioaddr = pci_io_space_pci_base + PCI_IO_SPACE_SIZE;
 201         maxpciioaddr = nextpciioaddr;
 202     }
 203     else {
 204         /* If we are not the master then wait for somebody to configure us */
 205         if (!pcimaster) {
 206             /* wait for up to 3s until we get configured */
 207             int i;
 208             for (i = 0; i < 300; i++) {
 209                 msdelay (10);
 210                 if (BONITO_PCICMD & PCI_COMMAND_MEM_ENABLE)
 211                     break;
 212             }
 213             /* wait a little bit longer for the master scan to complete */
 214             msdelay (100);
 215         }
 216
 217         /* This assumes the address space is contiguous starting at PCIMAP_LO0 */
 218         pci_mem_space_pci_base = (BONITO_PCIMAP & BONITO_PCIMAP_PCIMAP_LO0) << (26 - BONITO_PCIMAP_PCIMAP_LO0_SHIFT);
 219
 220         pci_local_mem_pci_base = BONITO_PCIBASE0 & PCI_MAPREG_MEM_ADDR_MASK;
 221
 222         /* assume BAR1 is suitable for 24 bit accesses */
 223         pci_local_mem_isa_base = BONITO_PCIBASE1 & PCI_MAPREG_MEM_ADDR_MASK;
 224     }
 225
 226
 227     if (initialise) {
 228         /* set up Local->PCI mappings */
 229         /* LOCAL:PCI_MEM_SPACE+00000000 -> PCI:pci_mem_space_pci_base#0x0c000000 */
 230         /* LOCAL:80000000               -> PCI:80000000#0x80000000 */
 231         BONITO_PCIMAP =
 232             BONITO_PCIMAP_WIN(0, pci_mem_space_pci_base+0x00000000) |
 233             BONITO_PCIMAP_WIN(1, pci_mem_space_pci_base+0x04000000) |
 234             BONITO_PCIMAP_WIN(2, pci_mem_space_pci_base+0x08000000) |
 235             BONITO_PCIMAP_PCIMAP_2;
 236
 237         /* LOCAL:PCI_IO_SPACE -> PCI:00000000-00100000 */
 238         /* hardwired */
 239     }
 240
 241     if (pcimaster) {
 242         /* set up PCI->Local mappings */
 243
 244         /* pcimembasecfg has been set up by low-level code */
 245
 246         /* Initialise BARs for access to our memory */
 247         /* PCI:pci_local_mem_pci_base -> LOCAL:0 */
 248         BONITO_PCIBASE0 = pci_local_mem_pci_base;
 249
 250         /* PCI:pci_local_mem_isa_base -> LOCAL:0 */
 251         BONITO_PCIBASE1 = pci_local_mem_isa_base;
 252
 253         /* PCI:PCI_LOCAL_MEM_PCI_BASE+10000000 -> LOCAL bonito registers (512b) */
 254         BONITO_PCIBASE2 = pci_local_mem_pci_base + 0x10000000;
 255
 256         if (!initialise)
 257             return 0;
 258
 259 #ifdef BONITO_PCICFG_PCIRESET
 260         /* reset the PCI bus */
 261         BONITO_PCICFG &= ~BONITO_PCICFG_PCIRESET;
 262         usdelay (1);
 263
 264         /* unreset the PCI bus */
 265         BONITO_PCICFG |= BONITO_PCICFG_PCIRESET;
 266 #endif
 267     }
 268
 269     return initialise && pcimaster;
 270 }
 271
 272
 273 /*
 274  * Called to reinitialise the bridge after we've scanned each PCI device
 275  * and know what is possible.
 276  */
 277 void
 278 pci_hwreinit (int port, pci_flags_t flags)
 279 {
 280     if (pcimaster) {
 281         /* set variable latency timer */
 282         PCI_MISC_LTIM_SET(BONITO_PCILTIMER, _pci_bus[0].def_ltim);
 283
 284         if (_pci_bus[0].prefetch) {
 285             /* we can safely prefetch from all pci mem devices */
 286         }
 287     }
 288 }
 289
 290
 291 void
 292 pci_flush (void)
 293 {
 294     /* flush read-ahead fifos (!) */
 295 }
 296
 297
 298
 299
 300 pcitag_t
 301 pci_make_tag(int port, int bus, int device, int function)
 302 {
 303     pcitag_t tag;
 304     tag = (bus << 16) | (device << 11) | (function << 8);
 305     return tag;
 306 }
 307
 308 void __inline__
 309 pci_break_tag(pcitag_t tag,
 310               int *portp, int *busp, int *devicep, int *functionp)
 311 {
 312     if (portp) *portp = 0;
 313     if (busp) *busp = (tag >> 16) & 255;
 314     if (devicep) *devicep = (tag >> 11) & 31;
 315     if (functionp) *functionp = (tag >> 8) & 7;
 316 }
 317
 318 int
 319 pci_canscan (pcitag_t tag)
 320 {
 321     int bus, dev;
 322     pci_break_tag (tag, NULL, &bus, &dev, NULL);
 323     return !(bus == 0 && (pcireserved & (1 << dev)));
 324 }
 325
 326 /*
 327  * flush Bonito register writes
 328  */
 329 static void __inline__
 330 bflush (void)
 331 {
 332     (void)BONITO_PCIMAP_CFG;    /* register address is arbitrary */
 333 }
 334
 335 pcireg_t
 336 pci_conf_read(pcitag_t tag, int reg)
 337 {
 338     uint32_t addr, type;
 339     pcireg_t data, stat;
 340     int bus, device, function;
 341
 342     if ((reg & 3) || reg < 0 || reg >= 0x100) {
 343         if (_pciverbose >= 1)
 344             pci_tagprintf (tag, "pci_conf_read: bad reg 0x%x\n", reg);
 345         return ~0;
 346     }
 347
 348     pci_break_tag (tag, NULL, &bus, &device, &function);
 349     if (bus == 0) {
 350         /* Type 0 configuration on onboard PCI bus */
 351         if (device > 20 || function > 7)
 352             return ~0;          /* device out of range */
 353         addr = (1 << (device+11)) | (function << 8) | reg;
 354         type = 0x00000;
 355     }
 356     else {
 357         /* Type 1 configuration on offboard PCI bus */
 358         if (bus > 255 || device > 31 || function > 7)
 359             return ~0;  /* device out of range */
 360         addr = (bus << 16) | (device << 11) | (function << 8) | reg;
 361         type = 0x10000;
 362     }
 363
 364     /* clear aborts */
 365     BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT;
 366
 367     BONITO_PCIMAP_CFG = (addr >> 16) | type;
 368     bflush ();
 369
 370     data = *(volatile pcireg_t *)PHYS_TO_K1(BONITO_PCICFG_BASE | (addr & 0xfffc));
 371
 372     stat = BONITO_PCICMD;
 373
 374     if (stat & PCI_STATUS_MASTER_ABORT) {
 375         return ~0;
 376     }
 377
 378     if (stat & PCI_STATUS_MASTER_TARGET_ABORT) {
 379         if (_pciverbose >= 1)
 380             pci_tagprintf (tag, "pci_conf_read: target abort\n");
 381         return ~0;
 382     }
 383
 384     return data;
 385 }
 386
 387
 388 void
 389 pci_conf_write(pcitag_t tag, int reg, pcireg_t data)
 390 {
 391     uint32_t addr, type;
 392     pcireg_t stat;
 393     int bus, device, function;
 394
 395     if ((reg & 3) || reg < 0 || reg >= 0x100) {
 396         if (_pciverbose >= 1)
 397             pci_tagprintf (tag, "pci_conf_write: bad reg %x\n", reg);
 398         return;
 399     }
 400
 401     pci_break_tag (tag, NULL, &bus, &device, &function);
 402
 403     if (bus == 0) {
 404         /* Type 0 configuration on onboard PCI bus */
 405         if (device > 20 || function > 7)
 406             return;             /* device out of range */
 407         addr = (1 << (device+11)) | (function << 8) | reg;
 408         type = 0x00000;
 409     }
 410     else {
 411         /* Type 1 configuration on offboard PCI bus */
 412         if (bus > 255 || device > 31 || function > 7)
 413             return;     /* device out of range */
 414         addr = (bus << 16) | (device << 11) | (function << 8) | reg;
 415         type = 0x10000;
 416     }
 417
 418     /* clear aborts */
 419     BONITO_PCICMD |= PCI_STATUS_MASTER_ABORT | PCI_STATUS_MASTER_TARGET_ABORT;
 420
 421     BONITO_PCIMAP_CFG = (addr >> 16) | type;
 422     bflush ();
 423
 424     *(volatile pcireg_t *)PHYS_TO_K1(BONITO_PCICFG_BASE | (addr & 0xfffc)) = data;
 425     stat = BONITO_PCICMD;
 426
 427     if (stat & PCI_STATUS_MASTER_ABORT) {
 428         if (_pciverbose >= 1)
 429             pci_tagprintf (tag, "pci_conf_write: master abort\n");
 430     }
 431
 432     if (stat & PCI_STATUS_MASTER_TARGET_ABORT) {
 433         if (_pciverbose >= 1)
 434             pci_tagprintf (tag, "pci_conf_write: target abort\n");
 435     }
 436 }
 437
 438 int
 439 pci_conf_write_acked(pcitag_t tag, int reg, pcireg_t data)
 440 {
 441     pci_conf_write(tag,reg,data);
 442     return 1;
 443 }
 444
 445 pcireg_t
 446 pci_conf_read16(pcitag_t tag, int reg)
 447 {
 448     return pci_conf_read (tag, reg);
 449 }
 450
 451 void
 452 pci_conf_write16(pcitag_t tag, int reg, pcireg_t data)
 453 {
 454     pci_conf_write (tag, reg, data);
 455 }
 456
 457
 458
 459
 460 int
 461 pci_map_io(pcitag_t tag, int reg, pci_endian_t endian, phys_addr_t *pap)
 462 {
 463     pcireg_t address;
 464     phys_addr_t pa;
 465
 466     if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) {
 467         if (_pciverbose >= 1)
 468             pci_tagprintf(tag, "_pci_map_io: bad request\n");
 469         return -1;
 470     }
 471
 472     address = pci_conf_read(tag, reg);
 473
 474     if ((address & PCI_MAPREG_TYPE_IO) == 0) {
 475         if (_pciverbose >= 1)
 476             pci_tagprintf (tag, "_pci_map_io: attempt to i/o map a memory region\n");
 477         return -1;
 478     }
 479
 480     pa = (address & PCI_MAPREG_IO_ADDR_MASK) - pci_io_space_pci_base;
 481     pa += pci_io_space;
 482     *pap = pa;
 483
 484     if (_pciverbose >= 3)
 485         pci_tagprintf(tag, "_pci_map_io: mapping i/o at physical %016llx\n",
 486                        (uint64_t)*pap);
 487
 488     return 0;
 489 }
 490
 491 int
 492 pci_map_mem(pcitag_t tag, int reg, pci_endian_t endian, phys_addr_t *pap)
 493 {
 494     pcireg_t address;
 495     phys_addr_t pa;
 496
 497     if (reg == PCI_MAPREG_ROM) {
 498         /* expansion ROM */
 499         address = pci_conf_read(tag, reg);
 500         if (!(address & PCI_MAPREG_ROM)) {
 501             pci_tagprintf (tag, "_pci_map_mem: attempt to map missing rom\n");
 502             return -1;
 503         }
 504         pa = address & PCI_MAPREG_ROM_ADDR_MASK;
 505     }
 506     else {
 507         if (reg < PCI_MAPREG_START || reg >= PCI_MAPREG_END || (reg & 3)) {
 508             if (_pciverbose >= 1)
 509                 pci_tagprintf(tag, "_pci_map_mem: bad request\n");
 510             return -1;
 511         }
 512
 513         address = pci_conf_read(tag, reg);
 514
 515         if ((address & PCI_MAPREG_TYPE_IO) != 0) {
 516             if (_pciverbose >= 1)
 517                 pci_tagprintf(tag, "pci_map_mem: attempt to memory map an I/O region\n");
 518             return -1;
 519         }
 520
 521         switch (address & PCI_MAPREG_MEM_TYPE_MASK) {
 522         case PCI_MAPREG_MEM_TYPE_32BIT:
 523         case PCI_MAPREG_MEM_TYPE_32BIT_1M:
 524             break;
 525         case PCI_MAPREG_MEM_TYPE_64BIT:
 526             if (_pciverbose >= 1)
 527                 pci_tagprintf (tag, "_pci_map_mem: attempt to map 64-bit region\n");
 528             return -1;
 529         default:
 530             if (_pciverbose >= 1)
 531                 pci_tagprintf (tag, "_pci_map_mem: reserved mapping type\n");
 532             return -1;
 533         }
 534         pa = address & PCI_MAPREG_MEM_ADDR_MASK;
 535     }
 536
 537
 538     pa -= pci_mem_space_pci_base;
 539     pa += pci_mem_space;
 540     *pap = pa;
 541
 542     if (_pciverbose >= 3)
 543         pci_tagprintf (tag, "_pci_map_mem: mapping memory at physical 0x%016llX\n",
 544                         (uint64_t)*pap);
 545     return 0;
 546 }
 547
 548 /*
 549  * allocate PCI address spaces
 550  * only applicable if we are the PCI master
 551  */
 552
 553
 554 \f
 555
 556 /*
 557  * Handle mapping of fixed ISA addresses
 558  */
 559
 560
 561 #define ISAPORT_ADDR(port) (PHYS_TO_K1(pci_io_space_pci_base + (port)))
 562
 563
 564 uint8_t
 565 inb (unsigned int port)
 566 {
 567     return hs_read8(ISAPORT_ADDR(port));
 568 }
 569
 570 uint16_t
 571 inw (unsigned int port)
 572 {
 573     return hs_read16(ISAPORT_ADDR(port));
 574 }
 575
 576 uint32_t
 577 inl (unsigned int port)
 578 {
 579     return hs_read32(ISAPORT_ADDR(port));
 580 }
 581
 582 void
 583 outb (unsigned int port, uint8_t val)
 584 {
 585     hs_write8(ISAPORT_ADDR(port),val);
 586     mips_wbflush ();
 587 }
 588
 589 void
 590 outw (unsigned int port, uint16_t val)
 591 {
 592     hs_write16(ISAPORT_ADDR(port),val);
 593     mips_wbflush ();
 594 }
 595
 596 void
 597 outl (unsigned int port, uint32_t val)
 598 {
 599     hs_write32(ISAPORT_ADDR(port),val);
 600     mips_wbflush ();
 601 }
 602
 603
 604 int
 605 pci_probe_tag(pcitag_t tag)
 606 {
 607     pcireg_t data;
 608
 609     if (!pci_canscan(tag))
 610         return 0;
 611
 612     data = pci_conf_read(tag,PCI_ID_REG);
 613
 614     mips_wbflush ();
 615
 616     if ((data == 0) || (data == 0xffffffff)) return 0;
 617
 618     return 1;
 619 }
 620
 621 int
 622 pci_map_window(phys_addr_t va,
 623                unsigned int offset, unsigned int len,
 624                int l2ca, int endian)
 625 {
 626     return -1;
 627 }
 628
 629 int
 630 pci_unmap_window(unsigned int offset, unsigned int len)
 631 {
 632     return -1;
 633 }
 634
 635 int
 636 pci_device_preset (pcitag_t tag)
 637 {
 638     /* Nothing to do for now. */
 639     return 0;
 640 }
 641 void
 642 pci_device_setup (pcitag_t tag)
 643 {
 644     /* Nothing to do for now. */
 645 }
 646
 647
 648 /* Called for each bridge after configuring the secondary bus, to allow
 649    device-specific initialization. */
 650 void
 651 pci_bridge_setup (pcitag_t tag, pci_flags_t flags)
 652 {
 653     /* nothing to do */
 654 }
 655
 656 /* The base shift of a slot or device on the motherboard.  Only device
 657    ids 3, 4 and 5 are implemented as PCI connectors. */
 658 uint8_t
 659 pci_int_shift_0(pcitag_t tag)
 660 {
 661     int bus, device;
 662
 663     pci_break_tag (tag, NULL, &bus, &device, NULL);
 664
 665     if (bus != 0)
 666         return 0;
 667
 668     switch (device) {
 669     case 0: case 1: case 2:            /* dedicated on-board devices */
 670         return 0;
 671     case 3: case 4: case 5:            /* PCI slots */
 672         return ((device - 3) % 4);
 673     default:
 674         return 0;
 675     }
 676 }
 677
 678 #define PCI_INTERRUPT_ENET  5
 679 #define PCI_INTERRUPT_SCSI  6
 680 #define PCI_INTERRUPT_USB   8
 681
 682 /* Return the mapping of a P5064 device/function interrupt to an
 683    interrupt line.  Values 1-4 indicate the PCIIRQ0-3 inputs to the
 684    interrupt mapper, respectively, dedicated values as above, or 0 if
 685    there is no mapping.  This is board specific. */
 686 uint8_t
 687 pci_int_map_0(pcitag_t tag)
 688 {
 689     pcireg_t data;
 690     int pin, bus, device;
 691
 692     data = pci_conf_read(tag, PCI_BPARAM_INTERRUPT_REG);
 693     pin = PCI_INTERRUPT_PIN(data);
 694     if (pin == 0) {
 695         /* No IRQ used. */
 696         return 0;
 697     }
 698     if (pin > 4) {
 699         if (_pciverbose >= 1)
 700             pci_tagprintf (tag, "pci_map_int: bad interrupt pin %d\n", pin);
 701         return 0;
 702     }
 703
 704     pci_break_tag (tag, NULL, &bus, &device, NULL);
 705
 706     if (bus != 0)
 707         return 0;
 708
 709     switch (device) {
 710     case 0:
 711         return PCI_INTERRUPT_ENET;
 712     case 1:
 713         return PCI_INTERRUPT_SCSI;
 714     case 2:
 715         return PCI_INTERRUPT_USB;
 716     case 3: case 4: case 5:
 717         return (((pin - 1) + pci_int_shift_0(tag)) % 4) + 1;
 718     default:
 719         return 0;
 720     }
 721 }
 722
 723 /* Map PCI interrupts A, B, C, D into a value for the IntLine
 724    register.  For SB1250, return the source number used by the
 725    interrupt mapper, or 0xff if none. */
 726 uint8_t
 727 pci_int_line(uint8_t pci_int)
 728 {
 729   switch (pci_int) {
 730   case PCI_INTERRUPT_ENET:
 731       return 0x02;
 732   case PCI_INTERRUPT_SCSI:
 733       return 0x04;
 734   case PCI_INTERRUPT_USB:
 735       return 0x08;
 736   case 1: case 2: case 3: case 4:   /* PCI_INT_A .. PCI_INT_D */
 737       return 0x10 << (pci_int - 1);
 738   default:
 739       return 0;
 740   }
 741 }