release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/p6064/include/reginit.h

   1 /*
   2  * share/reginit.h: generic hardware initialisation engine
   3  *
   4  * Copyright (c) 2001, Algorithmics Ltd.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the "Free MIPS" License Agreement, a copy of
   8  * which is available at:
   9  *
  10  *  http://www.algor.co.uk/ftp/pub/doc/freemips-license.txt
  11  *
  12  * You may not, however, modify or remove any part of this copyright
  13  * message if this program is redistributed or reused in whole or in
  14  * part.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * "Free MIPS" License for more details.
  20  */
  21
  22 #define MOD_MASK        0x00000003
  23 #define MOD_B           0x00000000 /* byte "modifier" */
  24 #define MOD_H           0x00000001 /* halfword "modifier" */
  25 #define MOD_W           0x00000002 /* word "modifier" */
  26 #if __mips64
  27 #define MOD_D           0x00000003 /* doubleword "modifier" */
  28 #endif
  29
  30 #define OP_MASK         0x000000fc
  31 #define OP_EXIT         0x00000000 /* exit (status) */
  32 #define OP_DELAY        0x00000008 /* delay (cycles) */
  33 #define OP_RD           0x00000010 /* read (addr) */
  34 #define OP_WR           0x00000014 /* write (addr, val) */
  35 #define OP_RMW          0x00000018 /* read-modify-write (addr, and, or) */
  36 #define OP_WAIT         0x00000020 /* wait (addr, mask, value) */
  37 #define OP_JUMP         0x00000024 /* jump (addr) */
  38
  39 #ifdef __ASSEMBLER__
  40
  41 #if __mips64
  42 #define rword   .dword
  43 #define lr      ld
  44 #else
  45 #define rword   .word
  46 #define lr      lw
  47 #endif
  48
  49         .struct 0
  50 Init_Op:        .word   0
  51 Init_A0:        .word   0
  52 Init_A1:        rword   0
  53 Init_A2:        rword   0
  54 Init_Size:
  55         .previous
  56
  57 #define WR_INIT(mod,addr,val) \
  58         .word   OP_WR|MOD_##mod,PHYS_TO_K1(addr);\
  59         rword   (val),0
  60
  61 #define RD_INIT(mod,addr) \
  62         .word   OP_RD|MOD_##mod,PHYS_TO_K1(addr);\
  63         rword   0,0
  64
  65 #define RMW_INIT(mod,addr,and,or) \
  66         .word   OP_RMW|MOD_##mod,PHYS_TO_K1(addr);\
  67         rword   (and),(or)
  68
  69 #define WAIT_INIT(mod,addr,and,or) \
  70         .word   OP_WAIT|MOD_##mod,PHYS_TO_K1(addr);\
  71         rword   (mask),(val)
  72
  73 #define JUMP_INIT(addr) \
  74 88:     .word   OP_JUMP,addr;\
  75         rword   0,0
  76
  77 #define DELAY_INIT(cycles) \
  78         .word   OP_DELAY,(cycles);\
  79         rword   0,0
  80
  81 #define EXIT_INIT(status) \
  82         .word   OP_EXIT,(status);\
  83         rword   0,0
  84
  85 #else
  86
  87 struct reginit {
  88     unsigned long       op;
  89     unsigned long       a0;
  90 #if __mips64
  91     unsigned long long  a1;
  92     unsigned long long  a2;
  93 #else
  94     unsigned long       a1;
  95     unsigned long       a2;
  96 #endif
  97 };
  98
  99 #define WR_INIT(mod,addr,val) \
 100         {OP_WR | MOD_ ## mod, PHYS_TO_K1(addr), (val)}
 101
 102 #define RD_INIT(mod,addr) \
 103         {OP_RD | MOD_ ## mod, PHYS_TO_K1(addr)}
 104
 105 #define RMW_INIT(mod,addr,and,or) \
 106         {OP_RMW | MOD_ ## mod, PHYS_TO_K1(addr), (and), (or)}
 107
 108 #define WAIT_INIT(mod,addr,and,or) \
 109         {OP_WAIT | MOD_ ## mod, PHYS_TO_K1(addr), (mask), (val)}
 110
 111 #define JUMP_INIT(addr) \
 112         {OP_JUMP, (unsigned long)(addr)}
 113
 114 #define DELAY_INIT(cycles) \
 115         {OP_DELAY, (cycles)}
 116
 117 #define EXIT_INIT(status) \
 118         {OP_EXIT, (status)}
 119 #endif