release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/p6064/include/ns16550.h

   1 /*
   2  * ns16550.h: NS16550/450 & XR16850 UART registers
   3  *
   4  * Copyright (c) 1998-1999, Algorithmics Ltd.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the "Free MIPS" License Agreement, a copy of
   8  * which is available at:
   9  *
  10  *  http://www.algor.co.uk/ftp/pub/doc/freemips-license.txt
  11  *
  12  * You may not, however, modify or remove any part of this copyright
  13  * message if this program is redistributed or reused in whole or in
  14  * part.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * "Free MIPS" License for more details.
  20  */
  21
  22 #ifndef NS16550_HZ
  23 #define NS16550_HZ      1843200
  24 #endif
  25
  26 #define NS16550_TICK    (NS16550_HZ / 16)
  27
  28 /* 16 bit baud rate divisor (lower byte in dll, upper in dlm) */
  29 #define BRTC(x)         (NS16550_TICK / (x))
  30
  31 /* permissible speed variance in thousandths; real == desired +- 3.0% */
  32 #define SPEED_TOLERANCE 30
  33
  34
  35 #ifndef __ASSEMBLER__
  36
  37 #ifndef nsreg
  38 #if #endian(big)
  39 #define nsreg(x)        unsigned int x:24; unsigned char x
  40 #else
  41 #define nsreg(x)        unsigned char x; unsigned :24
  42 #endif
  43 #endif
  44
  45 #ifndef nslayout
  46 #define nslayout(r0,r1,r2,r3) nsreg(r0); nsreg(r1); nsreg(r2); nsreg(r3)
  47 #endif
  48
  49 typedef struct {
  50     nslayout (data, ier, iir, cfcr);
  51         /* data */      /* data register (R/W) */
  52 #define dll     data    /* 16550 fifo control (W) */
  53         /* ier */       /* interrupt enable (W) */
  54 #define dlm     ier     /* 16550 fifo control (W) */
  55         /* iir */       /* interrupt identification (R) */
  56 #define fifo    iir     /* 16550 fifo control (W) */
  57         /* cfcr) */     /* line control register (R/W) */
  58     nslayout(mcr,lsr,msr,scr);
  59         /* mcr */       /* modem control register (R/W) */
  60         /* lsr */       /* line status register (R/W) */
  61         /* msr */       /* modem status register (R/W) */
  62         /* scr */       /* scratch register (R/W) */
  63 } ns16550dev;
  64
  65 typedef struct {
  66     nslayout(fifo2,fctr,efr,cfcr);
  67         /* fifo2 */     /* fifo trigger register (R/W) */
  68         /* fctr */      /* feature control (W) */
  69         /* efr */       /* enhanced feature register (R/W) */
  70         /* cfcr */      /* same as above */
  71     nslayout(xon1, xon2, xoff1, xoff2);
  72         /* xon1 */      /* xon-1 word (R/W) */
  73         /* xon2 */      /* xon-2 word (R/W) */
  74         /* xoff1 */     /* xoff-2 word (R/W) */
  75         /* xoff2 */     /* xoff-2 word (R) */
  76 } xr16850efr;
  77
  78 #else
  79
  80 #ifndef NSREG
  81 #if #endian(big)
  82 #define NSREG(x)        ((x)*4+3)
  83 #else
  84 #define NSREG(x)        ((x)*4+0)
  85 #endif
  86 #endif
  87
  88 #define DATA    NSREG(0)
  89 #define DLL     DATA
  90 #define IER     NSREG(1)
  91 #define DLM     IER
  92 #define IIR     NSREG(2)
  93 #define FIFO    IIR
  94 #define CFCR    NSREG(3)
  95 #define MCR     NSREG(4)
  96 #define LSR     NSREG(5)
  97 #define MSR     NSREG(6)
  98 #define SCR     NSREG(7)
  99
 100 #endif /* __ASSEMBLER__ */
 101
 102 /* interrupt enable register */
 103 #define IER_ERXRDY      0x01    /* int on rx ready */
 104 #define IER_ETXRDY      0x02    /* int on tx ready */
 105 #define IER_ERLS        0x04    /* int on line status change */
 106 #define IER_EMSC        0x08    /* int on modem status change */
 107 #define IER_SLEEP       0x10    /* (16850) sleep mode */
 108 #define IER_XOFF        0x20    /* (16850) int on receiving xoff */
 109 #define IER_RTS         0x40    /* (16850) int on rts */
 110 #define IER_CTS         0x80    /* (16850) int on cts */
 111
 112 /* interrupt identification register */
 113 #define IIR_IMASK       0xf     /* mask */
 114 #define IIR_RXTOUT      0xc     /* receive timeout */
 115 #define IIR_RLS         0x6     /* receive line status */
 116 #define IIR_RXRDY       0x4     /* receive ready */
 117 #define IIR_TXRDY       0x2     /* transmit ready */
 118 #define IIR_NOPEND      0x1     /* nothing */
 119 #define IIR_MLSC        0x0     /* modem status */
 120 #define IIR_XOFF        0x10    /* (16850) xoff interrupt */
 121 #define IIR_RTSCTS      0x20    /* (16850) rts/cts interrupt */
 122 #define IIR_FIFO_MASK   0xc0    /* set if FIFOs are enabled */
 123
 124 /* fifo control register */
 125 #define FIFO_ENABLE     0x01    /* enable fifo */
 126 #define FIFO_RCV_RST    0x02    /* reset receive fifo */
 127 #define FIFO_XMT_RST    0x04    /* reset transmit fifo */
 128 #define FIFO_DMA_MODE   0x08    /* enable dma mode */
 129 #define FIFO_TRIGGER_1  0x00    /* trigger at 1 char */
 130 #define FIFO_TRIGGER_4  0x40    /* trigger at 4 chars */
 131 #define FIFO_TRIGGER_8  0x80    /* trigger at 8 chars */
 132 #define FIFO_TRIGGER_14 0xc0    /* trigger at 14 chars */
 133 #define FIFO_RXTRIG_a   0x00    /* (16850) Rx fifo trigger */
 134 #define FIFO_RXTRIG_b   0x40    /* (16850) Rx fifo trigger */
 135 #define FIFO_RXTRIG_c   0x80    /* (16850) Rx fifo trigger */
 136 #define FIFO_RXTRIG_d   0xc0    /* (16850) Rx fifo trigger */
 137 #define FIFO_TXTRIG_a   0x00    /* (16850) Tx fifo trigger */
 138 #define FIFO_TXTRIG_b   0x10    /* (16850) Tx fifo trigger */
 139 #define FIFO_TXTRIG_c   0x20    /* (16850) Tx fifo trigger */
 140 #define FIFO_TXTRIG_d   0x30    /* (16850) Tx fifo trigger */
 141
 142 /* character format control register */
 143 #define CFCR_DLAB       0x80    /* divisor latch */
 144 #define CFCR_SBREAK     0x40    /* send break */
 145 #define CFCR_PZERO      0x30    /* zero parity */
 146 #define CFCR_PONE       0x20    /* one parity */
 147 #define CFCR_PEVEN      0x10    /* even parity */
 148 #define CFCR_PODD       0x00    /* odd parity */
 149 #define CFCR_PENAB      0x08    /* parity enable */
 150 #define CFCR_STOPB      0x04    /* 2 stop bits */
 151 #define CFCR_CSIZE      0x03
 152 #define CFCR_8BITS      0x03    /* 8 data bits */
 153 #define CFCR_7BITS      0x02    /* 7 data bits */
 154 #define CFCR_6BITS      0x01    /* 6 data bits */
 155 #define CFCR_5BITS      0x00    /* 5 data bits */
 156 #define CFCR_EFR        0xbf    /* access 16850 extended registers */
 157
 158 /* modem control register */
 159 #define MCR_CLKDIV4     0x80    /* (16850) divide baud rate by 4 */
 160 #define MCR_IRRT        0x40    /* (16850) IrDA connection */
 161 #define MCR_XON_ANY     0x20    /* (16850) XON any?? */
 162 #define MCR_LOOPBACK    0x10    /* loopback */
 163 #define MCR_IENABLE     0x08    /* output 2 = int enable */
 164 #define MCR_DRS         0x04
 165 #define MCR_RTS         0x02    /* enable RTS */
 166 #define MCR_DTR         0x01    /* enable DTR */
 167
 168 /* line status register */
 169 #define LSR_RCV_FIFO    0x80    /* error in receive fifo */
 170 #define LSR_TSRE        0x40    /* transmitter empty */
 171 #define LSR_TXRDY       0x20    /* transmitter ready */
 172 #define LSR_BI          0x10    /* break detected */
 173 #define LSR_FE          0x08    /* framing error */
 174 #define LSR_PE          0x04    /* parity error */
 175 #define LSR_OE          0x02    /* overrun error */
 176 #define LSR_RXRDY       0x01    /* receiver ready */
 177 #define LSR_RCV_MASK    0x1f
 178
 179 /* modem status register */
 180 #define MSR_DCD         0x80    /* DCD active */
 181 #define MSR_RI          0x40    /* RI  active */
 182 #define MSR_DSR         0x20    /* DSR active */
 183 #define MSR_CTS         0x10    /* CTS active */
 184 #define MSR_DDCD        0x08    /* DCD changed */
 185 #define MSR_TERI        0x04    /* RI  changed */
 186 #define MSR_DDSR        0x02    /* DSR changed */
 187 #define MSR_DCTS        0x01    /* CTS changed */
 188
 189 /* 16850 EFR */
 190 #define EFR_AUTO_CTS    0x80    /* auto CTS output flow control */
 191 #define EFR_AUTO_RTS    0x40    /* auto RTS input flow control */
 192 #define EFR_SPECIAL     0x20    /* special character detect */
 193 #define EFR_ENABLE      0x10    /* enable 16850 extensions */
 194 #define EFR_IFLOW_NONE  0x00    /* no input "software" flow control */
 195 #define EFR_IFLOW_1     0x08    /* transmit Xon/Xoff-1 */
 196 #define EFR_IFLOW_2     0x04    /* transmit Xon/Xoff-2 */
 197 #define EFR_OFLOW_NONE  0x00    /* no output "software" flow control */
 198 #define EFR_OFLOW_1     0x02    /* check for Xon/Xoff-1 */
 199 #define EFR_OFLOW_2     0x01    /* check for Xon/Xoff-2 */
 200
 201 /* 16850 FCTR */
 202 #define FCTR_TX_LEVEL   0x80    /* Tx programmable trigger level selected */
 203 #define FCTR_RX_LEVEL   0x00    /* Rx programmable trigger level selected */
 204 #define FCTR_SCPAD_SWAP 0x40    /* scratchpad becomes fifo count / emsr */
 205 #define FCTR_TTABLE_A   0x00    /* select trigger table A */
 206 #define FCTR_TTABLE_B   0x10    /* select trigger table B */
 207 #define FCTR_TTABLE_C   0x20    /* select trigger table C */
 208 #define FCTR_TTABLE_D   0x30    /* select trigger table D */
 209 #define FCTR_RS485      0x08    /* auto RS485 direction control */
 210 #define FCTR_IRRX_INV   0x04    /* invert IrDA Rx data */
 211 #define FCTR_RTSDELAY_0 0x00    /* RTS delay timer */
 212 #define FCTR_RTSDELAY_4 0x01
 213 #define FCTR_RTSDELAY_6 0x02
 214 #define FCTR_RTSDELAY_8 0x03
 215
 216 /* These next two appear in place of the scratchpad register if
 217    FCTR_SCPAD_SWAP is set */
 218
 219 /* 16850 EMSR (write only) */
 220 #define EMSR_ALT_FCNT   0x02    /* alternate Tx/Rx fifo count */
 221 #define EMSR_FCNT_TX    0x01    /* select Tx fifo count */
 222 #define EMSR_FCNT_RX    0x00    /* select Rx fifo count */
 223
 224 /* 16850 FIFO count (read only) */
 225 #define FCNT_TX         0x80    /* fifo count is Tx fifo */
 226 #define FCNT_RX         0x00    /* fifo count is Rx fifo */
 227 #define FCNT_MASK       0x7f    /* fifo count */