release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/p6064/include/i82371eb.h

   1 /*
   2  * i82371eb.h: Intel PCI to ISA bridge (PIIX4)
   3  *
   4  * Copyright (c) 2000, Algorithmics Ltd.  All rights reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the "Free MIPS" License Agreement, a copy of
   8  * which is available at:
   9  *
  10  *  http://www.algor.co.uk/ftp/pub/doc/freemips-license.txt
  11  *
  12  * You may not, however, modify or remove any part of this copyright
  13  * message if this program is redistributed or reused in whole or in
  14  * part.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * "Free MIPS" License for more details.
  20  */
  21
  22 #define I82371_IORT             0x4c
  23 #define  I82371_IORT_16BIT(x)    0x04+(((x)&3)<<0)
  24 #define  I82371_IORT_8BIT(x)     0x40+(((x)&7)<<3)
  25 #define  I82371_IORT_DMAAC       0x80
  26
  27 #define I82371_XBCS             0x4e
  28 #define  I82371_XBCS_RTCEN       0x0001
  29 #define  I82371_XBCS_KBDEN       0x0002
  30 #define  I82371_XBCS_BIOSWP      0x0004
  31 #define  I82371_XBCS_ALIAS61     0x0008
  32 #define  I82371_XBCS_MOUSE       0x0010
  33 #define  I82371_XBCS_CPERR       0x0020
  34 #define  I82371_XBCS_LBIOS       0x0040
  35 #define  I82371_XBCS_XBIOS       0x0080
  36 #define  I82371_XBCS_APIC        0x0100
  37 #define  I82371_XBCS_1MXBIOS     0x0200
  38 #define  I82371_XBCS_MCALE       0x0400
  39
  40 #define I82371_PIRQRCA          0x60
  41 #define I82371_PIRQRCB          0x61
  42 #define I82371_PIRQRCC          0x62
  43 #define I82371_PIRQRCD          0x63
  44 #define  I82371_PIRQRC(d)       (0x80 | (d & 0xf))
  45
  46 #define I82371_SICR             0x64
  47 #define  I82371_SICR_PW4         0x00
  48 #define  I82371_SICR_PW6         0x01
  49 #define  I82371_SICR_PW8         0x02
  50 #define  I82371_SICR_FS21        0x10
  51 #define  I82371_SICR_CONT        0x40
  52 #define  I82371_SICR_IRQEN       0x80
  53
  54 #define I82371_TOM              0x69
  55 #define  I82371_TOM_FWD_89       0x02
  56 #define  I82371_TOM_FWD_AB       0x04
  57 #define  I82371_TOM_FWD_LBIOS    0x08
  58 #define  I82371_TOM_TOM(mb)      (((mb)-1) << 4)
  59
  60 #define I82371_MSTAT            0x6a
  61 #define  I82371_MSTAT_NBRE       0x0080
  62 #define  I82371_MSTAT_SEDT       0x8000
  63
  64 #define I82371_MBDMA0           0x76
  65 #define I82371_MBDMA1           0x77
  66 #define  I82371_MBDMA_CHNL(x)   ((x) & 7)
  67 #define  I82371_MBDMA_FAST       0x80
  68
  69 #define I82371_APICBASE         0x80
  70
  71 #define I82371_DLC              0x82
  72 #define  I82371_DLC_DT           0x01 /* delayed transaction enb */
  73 #define  I82371_DLC_PR           0x02 /* passive release enb */
  74 #define  I82371_DLC_USBPR        0x04 /* USB passive release enb */
  75 #define  I82371_DLC_DTTE         0x08 /* SERR on delayed timeout */
  76
  77 #define I82371_PDMACFG          0x90
  78 #define I82371_DDMABP0          0x92
  79 #define I82371_DDMABP1          0x94
  80
  81 #define I82371_GENCFG           0xb0
  82 #define  I82371_GENCFG_CFG       0xfbfec001
  83
  84 #define I82371_RTCCFG           0xcb
  85 #define  I82371_RTCPDE          0x20
  86 #define  I82371_RTCLUB          0x10
  87 #define  I82371_RTCLLB          0x08
  88 #define  I82371_RTCURE          0x04
  89 #define  I82371_RTCRTCE         0x01
  90
  91 /* PCI function 1 configuration registers */
  92
  93 #define I82371_PCI1BMIBA                0x20
  94 #define I82371_PCI1IDETIM               0x40
  95 #define  I82371_PCI1IDETIM_IDE  0x8000 /* IDE decode enable */
  96 #define  I82371_PCI1IDETIM_SITRE        0x4000 /* IDE decode enable */
  97 #define  I82371_PCI1IDETIM_ISP2 0x3000 /* IDE slave timing */
  98 #define  I82371_PCI1IDETIM_ISP3 0x2000 /* IDE slave timing */
  99 #define  I82371_PCI1IDETIM_ISP4 0x1000 /* IDE slave timing */
 100 #define  I82371_PCI1IDETIM_ISP5 0x0000 /* IDE slave timing */
 101 #define  I82371_PCI1IDETIM_RTC1 0x0300 /* IDE recovery time */
 102 #define  I82371_PCI1IDETIM_RTC2 0x0200 /* IDE recovery time */
 103 #define  I82371_PCI1IDETIM_RTC3 0x0100 /* IDE recovery time */
 104 #define  I82371_PCI1IDETIM_RTC4 0x0000 /* IDE recovery time */
 105 #define  I82371_PCI1IDETIM_DTE1 0x0080 /* IDE DMA Timing enable */
 106 #define  I82371_PCI1IDETIM_PPE1 0x0040 /* IDE prefetch & post enable */
 107 #define  I82371_PCI1IDETIM_IE1  0x0020 /* IDE sample point enable */
 108 #define  I82371_PCI1IDETIM_TIME1        0x0010 /* IDE fast timing enable */
 109 #define  I82371_PCI1IDETIM_DTE0 0x0008 /* IDE DMA Timing enable */
 110 #define  I82371_PCI1IDETIM_PPE0 0x0004 /* IDE prefetch & post enable */
 111 #define  I82371_PCI1IDETIM_IE0  0x0002 /* IDE sample point enable */
 112 #define  I82371_PCI1IDETIM_TIME0        0x0001 /* IDE fast timing enable */
 113
 114
 115 #define I82371_PCI3_PMBA        0x40            /* Power Management Base Address */
 116 #define I82371_PCI3_CNTA        0x44            /* Count A */
 117 #define I82371_PCI3_CNTB        0x48            /* Count B */
 118 #define I82371_PCI3_GPICTL      0x4C            /* General Purpose Input Control */
 119 #define I82371_PCI3_DEVRESD     0x50            /* Device Resource D */
 120 #define I82371_PCI3_DEVACTA     0x54            /* Device Activity A */
 121 #define I82371_PCI3_DEVACTB     0x58            /* Device Activity B */
 122 #define I82371_PCI3_DEVRESA     0x5C            /* Device Resource A */
 123 #define I82371_PCI3_DEVRESB     0x60            /* Device Resource B */
 124 #define I82371_PCI3_DEVRESC     0x64            /* Device Resource C */
 125 #define I82371_PCI3_DEVRESE     0x68            /* Device Resource E */
 126 #define I82371_PCI3_DEVRESF     0x6C            /* Device Resource F */
 127 #define I82371_PCI3_DEVRESG     0x70            /* Device Resource G */
 128 #define I82371_PCI3_DEVRESH     0x74            /* Device Resource H */
 129 #define I82371_PCI3_DEVRESI     0x78            /* Device Resource I */
 130 #define I82371_PCI3_DEVRESJ     0x7C            /* Device Resource J */
 131 #define I82371_PCI3_PMREGMISC   0x80            /* Miscellaneous Power Management */
 132 #define I82371_PCI3_SMBBA       0x90            /* SMBus Base Address */
 133 #define I82371_PCI3_SMBHSTCFG   0xD2            /* SMBus Host Configuration */
 134 #define I82371_PCI3_SMBREV      0xD3            /* SMBus Revision ID */
 135 #define I82371_PCI3_SMBSLVC     0xD4            /* SMBus Slave Command */
 136 #define I82371_PCI3_SMBSHDW1    0xD5            /* SMBus Slave Shadow Port 1 */
 137 #define I82371_PCI3_SMBSHDW2    0xD6            /* SMBus Slave Shadow Port 2 */
 138
 139 /* I82371_PCI3_SMBHSTCFG */
 140 #define I82371_PCI3_SMB_HST_EN  0x01            /* enable SMB host interface */
 141
 142 /* Offsets from I82371_PCI3_SMBBA */
 143 #define I82371_SMB_SMBHSTSTS    0x00            /* SMBus Host Status */
 144 #define I82371_SMB_SMBSLVSTS    0x01            /* SMBus Slave Status */
 145 #define I82371_SMB_SMBHSTCNT    0x02            /* SMBus Host Count */
 146 #define I82371_SMB_SMBHSTCMD    0x03            /* SMBus Host Command */
 147 #define I82371_SMB_SMBHSTADD    0x04            /* SMBus Host Address */
 148 #define I82371_SMB_SMBHSTDAT0   0x05            /* SMBus Host Data 0 */
 149 #define I82371_SMB_SMBHSTDAT1   0x06            /* SMBus Host Data 1 */
 150 #define I82371_SMB_SMBBLKDAT    0x07            /* SMBus Block Data */
 151 #define I82371_SMB_SMBSLVCNT    0x08            /* SMBus Slave Count */
 152 #define I82371_SMB_SMBSHDWCMD   0x09            /* SMBus Shadow Command */
 153 #define I82371_SMB_SMBSLVEVT    0x0A            /* SMBus Slave Event */
 154 #define I82371_SMB_SMBSLVDAT    0x0C            /* SMBus Slave Data */
 155
 156 #define I82371_SMB_START        0x40
 157 #define I82371_SMB_QRW          (0<<2)
 158 #define I82371_SMB_BRW          (1<<2)
 159 #define I82371_SMB_BDRW         (2<<2)
 160 #define I82371_SMB_WDRW         (3<<2)
 161 #define I82371_SMB_BKRW         (5<<2)
 162 #define I82371_SMB_KILL         0x02
 163 #define I82371_SMB_INTEREN      0x01
 164
 165 #define I82371_SMB_FAILED       0x10
 166 #define I82371_SMB_BUS_ERR      0x08
 167 #define I82371_SMB_DEV_ERR      0x04
 168 #define I82371_SMB_INTER        0x02
 169 #define I82371_SMB_HOST_BUSY    0x01
 170
 171 #define I82371_SMB_ALERT_STS    0x10
 172 #define I82371_SMB_SHDW2_STS    0x08
 173 #define I82371_SMB_SHDW1_STS    0x04
 174 #define I82371_SMB_SLV_STS      0x02
 175 #define I82371_SMB_SLV_BSY      0x01
 176
 177 /* I82371_PCI3_PMREGMISC */
 178 #define I82371_PCI3_PMIOSE      0x01            /* enable SMB host interface */
 179
 180 /* Offsets from I82371_PCI3_PMBA */
 181 #define I82371_PM_PMSTS         0x00
 182 #define I82371_PM_PMEN          0x02
 183 #define I82371_PM_PMCNTRL       0x04
 184 #define I82371_PM_PMTMR         0x08
 185 #define I82371_PM_GPSTS         0x0c
 186 #define I82371_PM_GPEN          0x0e
 187 #define I82371_PM_PCNTRL        0x10
 188 #define I82371_PM_PLVL2         0x14
 189 #define I82371_PM_PLVL3         0x15
 190 #define I82371_PM_GLBSTS        0x18
 191 #define I82371_PM_DEVSTS        0x1c
 192 #define I82371_PM_GLBEN         0x20
 193 #define I82371_PM_GLBCTL        0x28
 194 #define I82371_PM_DEVCTL        0x2c
 195 #define I82371_PM_GPIREG0       0x30
 196 #define I82371_PM_GPIREG1       0x31
 197 #define I82371_PM_GPIREG2       0x32
 198 #define I82371_PM_GPOREG0       0x34
 199 #define I82371_PM_GPOREG1       0x35
 200 #define I82371_PM_GPOREG2       0x36
 201 #define I82371_PM_GPOREG3       0x37