release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/littlesur/include/littlesur.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  LITTLESUR  Definitions                           File: littlesur.h
   5     *
   6     *  This file contains I/O, chip select, and GPIO assignments
   7     *  for the LITTLESUR checkout board.
   8     *
   9     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This software is furnished under license and may be used and
  17     *  copied only in accordance with the following terms and
  18     *  conditions.  Subject to these conditions, you may download,
  19     *  copy, install, use, modify and distribute modified or unmodified
  20     *  copies of this software in source and/or binary form.  No title
  21     *  or ownership is transferred hereby.
  22     *
  23     *  1) Any source code used, modified or distributed must reproduce
  24     *     and retain this copyright notice and list of conditions
  25     *     as they appear in the source file.
  26     *
  27     *  2) No right is granted to use any trade name, trademark, or
  28     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  29     *     name may not be used to endorse or promote products derived
  30     *     from this software without the prior written permission of
  31     *     Broadcom Corporation.
  32     *
  33     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  34     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  35     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  37     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  38     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  39     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  41     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  42     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  43     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  44     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  45     *     THE POSSIBILITY OF SUCH DAMAGE.
  46     ********************************************************************* */
  47
  48
  49 /*
  50  * I/O Address assignments for the littlesur board
  51  *
  52  * Summary of address map:
  53  *
  54  * Address         Size   CSel    Description
  55  * --------------- ----   ------  --------------------------------
  56  * 0x1FC00000      16MB    CS0    Boot ROM
  57  *                         CS1    Unused
  58  *                         CS2    Unused
  59  * 0x100A0000      64KB    CS3    LED display
  60  * 0x100B0000      64KB    CS4    IDE Disk
  61  *                         CS5    Unused
  62  * 0x100C0000      64KB    CS6    Real Time Clock (RTC)
  63  *                         CS7    Unused
  64  *
  65  * GPIO assignments
  66  *
  67  * GPIO#    Direction   Description
  68  * -------  ---------   ------------------------------------------
  69  * GPIO0    Inout       Carmel GPIO 0
  70  * GPIO1    Input       RTC OUT                 (interrupt)
  71  * GPIO2    Input       PHY Interrupt           (interrupt)
  72  * GPIO3    Input       Nonmaskable Interrupt   (interrupt)
  73  * GPIO4    Input       IDE Disk Interrupt      (interrupt)
  74  * GPIO5    Input       Temperature Sensor Alert (interrupt)
  75  * GPIO6    Input       HT Loopback Reset
  76  * GPIO7    Input       HT Loopback Power OK
  77  * GPIO8    Input       Carmel GPIO 9
  78  * GPIO9    N/A         Unused
  79  * GPIO10   N/A         Unused
  80  * GPIO11   N/A         Unused
  81  * GPIO12   Input       Carmel GPIO 12
  82  * GPIO13   Input       Carmel GPIO 13
  83  * GPIO14   Input       Slot1 GPIO 0
  84  * GPIO15   Input       Slot1 GPIO 1
  85  */
  86
  87 /*  *********************************************************************
  88     *  Macros
  89     ********************************************************************* */
  90
  91 #define MB (1024*1024)
  92 #define K64 65536
  93 #define NUM64K(x) (((x)+(K64-1))/K64)
  94
  95
  96 /*  *********************************************************************
  97     *  GPIO pins
  98     ********************************************************************* */
  99
 100 #define GPIO_RTC_OUT_INT        1
 101 #define GPIO_PHY_INTERRUPT      2
 102 #define GPIO_NONMASKABLE_INT    3
 103 #define GPIO_IDE_INTERRUPT      4
 104 #define GPIO_TEMP_SENSOR_INT    5
 105
 106 #define M_GPIO_RTC_OUT_INT      _SB_MAKEMASK1(GPIO_RTC_OUT_INT)
 107 #define M_GPIO_PHY_INTERRUPT    _SB_MAKEMASK1(GPIO_PHY_INTERRUPT)
 108 #define M_GPIO_NONMASKABLE_INT  _SB_MAKEMASK1(GPIO_NONMASKABLE_INT)
 109 #define M_GPIO_IDE_INTERRUPT    _SB_MAKEMASK1(GPIO_IDE_INTERRUPT)
 110 #define M_GPIO_TEMP_SENSOR_INT  _SB_MAKEMASK1(GPIO_TEMP_SENSOR_INT)
 111
 112 #define GPIO_INTERRUPT_MASK ((V_GPIO_INTR_TYPEX(GPIO_PHY_INTERRUPT,K_GPIO_INTR_LEVEL)) | \
 113                              (V_GPIO_INTR_TYPEX(GPIO_IDE_INTERRUPT,K_GPIO_INTR_LEVEL)) | \
 114                              (V_GPIO_INTR_TYPEX(GPIO_TEMP_SENSOR_INT,K_GPIO_INTR_LEVEL)) | \
 115                              (V_GPIO_INTR_TYPEX(GPIO_RTC_OUT_INT,K_GPIO_INTR_LEVEL)))
 116
 117 #define GPIO_OUTPUT_MASK        0
 118
 119 /*  *********************************************************************
 120     *  Generic Bus
 121     ********************************************************************* */
 122
 123 #define BOOTROM_CS              0
 124 #define BOOTROM_PHYS            0x1FC00000      /* address of boot ROM (CS0) */
 125 #define BOOTROM_SIZE            NUM64K(4*MB)    /* size of boot ROM */
 126 #define BOOTROM_TIMING0         V_IO_ALE_WIDTH(4) | \
 127                                 V_IO_ALE_TO_CS(2) | \
 128                                 V_IO_CS_WIDTH(24) | \
 129                                 V_IO_RDY_SMPLE(1)
 130 #define BOOTROM_TIMING1         V_IO_ALE_TO_WRITE(7) | \
 131                                 V_IO_WRITE_WIDTH(7) | \
 132                                 V_IO_IDLE_CYCLE(6) | \
 133                                 V_IO_CS_TO_OE(0) | \
 134                                 V_IO_OE_TO_CS(0)
 135 #define BOOTROM_CONFIG          V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 136
 137 /*
 138  * LEDs:  non-multiplexed, byte width, no parity, no ack
 139  *
 140  */
 141 #define LEDS_CS                 3
 142 #define LEDS_PHYS               0x100A0000      /* same address as SWARM */
 143 #define LEDS_SIZE               NUM64K(4)
 144 #define LEDS_TIMING0            V_IO_ALE_WIDTH(4) | \
 145                                 V_IO_ALE_TO_CS(2) | \
 146                                 V_IO_CS_WIDTH(13) | \
 147                                 V_IO_RDY_SMPLE(1)
 148 #define LEDS_TIMING1            V_IO_ALE_TO_WRITE(2) | \
 149                                 V_IO_WRITE_WIDTH(8) | \
 150                                 V_IO_IDLE_CYCLE(6) | \
 151                                 V_IO_CS_TO_OE(0) | \
 152                                 V_IO_OE_TO_CS(0)
 153 #define LEDS_CONFIG             V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 154
 155 /*
 156  * RTC:  non-multiplexed, byte width, no parity, ack mode
 157  *
 158  */
 159 #define RTC_CS                  6
 160 #define RTC_PHYS                0x100C0000
 161 #define RTC_SIZE                NUM64K(4)
 162 #define RTC_TIMING0             V_IO_ALE_WIDTH(4) | \
 163                                 V_IO_ALE_TO_CS(1) | \
 164                                 V_IO_CS_WIDTH(23) | \
 165                                 V_IO_RDY_SMPLE(1)
 166 #define RTC_TIMING1             V_IO_ALE_TO_WRITE(2) | \
 167                                 V_IO_WRITE_WIDTH(8) | \
 168                                 V_IO_IDLE_CYCLE(6) | \
 169                                 V_IO_CS_TO_OE(3) | \
 170                                 V_IO_OE_TO_CS(2)
 171 #define RTC_CONFIG              V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1L)
 172
 173 /*
 174  * IDE: non-multiplexed, word(16) width, no parity, ack mode
 175  * See BCM12500 Application Note: "BCM12500 Generic Bus Interface
 176  * to ATA/ATAPI PIO Mode 3 (IDE) Hard Disk"
 177  */
 178 #define IDE_CS                  4
 179 #define IDE_PHYS                0x100B0000
 180 #define IDE_SIZE                NUM64K(256)
 181 #define IDE_TIMING0             V_IO_ALE_WIDTH(3) | \
 182                                 V_IO_ALE_TO_CS(1) | \
 183                                 V_IO_CS_WIDTH(8) | \
 184                                 V_IO_RDY_SMPLE(2)
 185 #define IDE_TIMING1             V_IO_ALE_TO_WRITE(4) | \
 186                                 V_IO_WRITE_WIDTH(0xA) | \
 187                                 V_IO_IDLE_CYCLE(1) | \
 188                                 V_IO_CS_TO_OE(3) | \
 189                                 V_IO_OE_TO_CS(2)
 190 #define IDE_CONFIG              V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2) | \
 191                                 M_IO_RDY_ACTIVE | \
 192                                 M_IO_ENA_RDY
 193
 194
 195 /*  *********************************************************************
 196     *  SMBus
 197     ********************************************************************* */
 198
 199 #define TEMPSENSOR_SMBUS_CHAN   0
 200 #define TEMPSENSOR_SMBUS_DEV    0x2A
 201
 202 #define BIGEEPROM_SMBUS_CHAN_1  1
 203 #define BIGEEPROM_SMBUS_DEV_1   0x51
 204
 205 #define BIGEEPROM_SMBUS_CHAN_0  0
 206 #define BIGEEPROM_SMBUS_DEV_0   0x50
 207
 208
 209 /*  *********************************************************************
 210     *  Board revision numbers
 211     ********************************************************************* */
 212
 213 /* Maps from SYSTEM_CFG register to actual board rev #'s */
 214
 215 #define LITTLESUR_REV_1 0