release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/c3/include/c3.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  C3 Checkout Board Definitions            File: c3.h
   5     *
   6     *  This file contains I/O, chip select, and GPIO assignments
   7     *  for the BCM12500 "C3" checkout board.
   8     *
   9     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This software is furnished under license and may be used and
  17     *  copied only in accordance with the following terms and
  18     *  conditions.  Subject to these conditions, you may download,
  19     *  copy, install, use, modify and distribute modified or unmodified
  20     *  copies of this software in source and/or binary form.  No title
  21     *  or ownership is transferred hereby.
  22     *
  23     *  1) Any source code used, modified or distributed must reproduce
  24     *     and retain this copyright notice and list of conditions
  25     *     as they appear in the source file.
  26     *
  27     *  2) No right is granted to use any trade name, trademark, or
  28     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  29     *     name may not be used to endorse or promote products derived
  30     *     from this software without the prior written permission of
  31     *     Broadcom Corporation.
  32     *
  33     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  34     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  35     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  37     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  38     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  39     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  41     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  42     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  43     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  44     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  45     *     THE POSSIBILITY OF SUCH DAMAGE.
  46     ********************************************************************* */
  47
  48
  49 #include "sb1250_jtag.h"
  50
  51 /*
  52  * I/O Address assignments for the C3 board
  53  *
  54  * Summary of address map:
  55  *
  56  * Address         Size   CSel    Description
  57  * --------------- ----   ------  --------------------------------
  58  * 0x1FC00000      4MB     CS0    Boot ROM
  59  * 0x1F800000      4MB     CS1    Alternate boot ROM
  60  *                         CS2    Unused
  61  *                         CS3    Unused
  62  *                         CS4    Unused
  63  *                         CS5    Unused
  64  *                         CS6    PCMCIA
  65  *                         CS7    Unused
  66  *
  67  * GPIO assignments
  68  *
  69  * GPIO#    Direction   Description
  70  * -------  ---------   ------------------------------------------
  71  * GPIO0    Output      Debug LED
  72  * GPIO1    Output      To Xilinx RTS_TSTROBE
  73  * GPIO2    Bidir       To Xilinx IO_ADP0
  74  * GPIO3    Bidir       To Xilinx IO_ADP1
  75  * GPIO4    Bidir       To Xilinx IO_ADP2
  76  * GPIO5    Bidir       To Xilinx IO_ADP3
  77  * GPIO6    Bidir       To Xilinx GPIOa pin
  78  * GPIO7    Bidir       To Xilinx GPIOb pin
  79  * GPIO8    Input       Nonmaskable Interrupt       (interrupt)
  80  * GPIO9    Input       Temperature Sensor Alert    (interrupt)
  81  * GPIO10   Output      Xilinx Programming Interface X_CCLK
  82  * GPIO11   Input       Xilinx Programming Interface X_DOUT
  83  * GPIO12   Output      Xilinx Programming Interface X_DIN
  84  * GPIO13   Output      Xilinx Programming Interface X_PGM_L
  85  * GPIO14   Bidir       Xilinx Programming Interface X_DONE
  86  * GPIO15   Bidir       Xilinx Programming Interface X_INIT_L
  87  */
  88
  89 /*  *********************************************************************
  90     *  Macros
  91     ********************************************************************* */
  92
  93 #define MB (1024*1024)
  94 #define K64 65536
  95 #define NUM64K(x) (((x)+(K64-1))/K64)
  96
  97
  98 /*  *********************************************************************
  99     *  GPIO pins
 100     ********************************************************************* */
 101
 102 #define GPIO_DEBUG_LED          0
 103 #define GPIO_XILINX_RTS_TSTROBE 1
 104 #define GPIO_XILINX_IO_ADP0     2
 105 #define GPIO_XILINX_IO_ADP1     3
 106 #define GPIO_XILINX_IO_ADP2     4
 107 #define GPIO_XILINX_IO_ADP3     5
 108 #define GPIO_XILINX_GPIO_A      6
 109 #define GPIO_XILINX_GPIO_B      7
 110 #define GPIO_NONMASKABLE_INT    8
 111 #define GPIO_TEMP_SENSOR_INT    9
 112 #define GPIO_XPROG_X_CCLK       10
 113 #define GPIO_XPROG_X_DOUT       11
 114 #define GPIO_XPROG_X_DIN        12
 115 #define GPIO_XPROG_X_PGM_L      13
 116 #define GPIO_XPROG_X_DONE       14
 117 #define GPIO_XPROG_X_INIT_L     14
 118
 119
 120 #define M_GPIO_DEBUG_LED        _SB_MAKEMASK1(GPIO_DEBUG_LED)
 121 #define M_GPIO_XILINX_RTS_TSTROBE _SB_MAKEMASK1(GPIO_XILINX_RTS_TSTROBE)
 122 #define M_GPIO_XILINX_IO_ADP0   _SB_MAKEMASK1(GPIO_XILINX_IO_ADP0)
 123 #define M_GPIO_XILINX_IO_ADP1   _SB_MAKEMASK1(GPIO_XILINX_IO_ADP1)
 124 #define M_GPIO_XILINX_IO_ADP2   _SB_MAKEMASK1(GPIO_XILINX_IO_ADP2)
 125 #define M_GPIO_XILINX_IO_ADP3   _SB_MAKEMASK1(GPIO_XILINX_IO_ADP3)
 126 #define M_GPIO_XILINX_GPIO_A    _SB_MAKEMASK1(GPIO_XILINX_GPIO_A)
 127 #define M_GPIO_XILINX_GPIO_B    _SB_MAKEMASK1(GPIO_XILINX_GPIO_B)
 128 #define M_GPIO_NONMASKABLE_INT  _SB_MAKEMASK1(GPIO_NONMASKABLE_INT)
 129 #define M_GPIO_TEMP_SENSOR_INT  _SB_MAKEMASK1(GPIO_TEMP_SENSOR_INT)
 130 #define M_GPIO_XPROG_X_CCLK     _SB_MAKEMASK1(GPIO_XPROG_X_CCLK)
 131 #define M_GPIO_XPROG_X_DOUT     _SB_MAKEMASK1(GPIO_XPROG_X_DOUT)
 132 #define M_GPIO_XPROG_X_DIN      _SB_MAKEMASK1(GPIO_XPROG_X_DIN)
 133 #define M_GPIO_XPROG_X_PGM_L    _SB_MAKEMASK1(GPIO_XPROG_X_PGM_L)
 134 #define M_GPIO_XPROG_X_DONE     _SB_MAKEMASK1(GPIO_XPROG_X_DONE)
 135 #define M_GPIO_XPROG_X_INIT_L   _SB_MAKEMASK1(GPIO_XPROG_X_INIT_L)
 136
 137 /* Leave bidirectional pins in "input" state at boot. */
 138
 139 #define GPIO_OUTPUT_MASK (M_GPIO_DEBUG_LED | \
 140                           M_GPIO_XILINX_RTS_TSTROBE | \
 141                           M_GPIO_XPROG_X_CCLK | \
 142                           M_GPIO_XPROG_X_DIN | \
 143                           M_GPIO_XPROG_X_PGM_L)
 144
 145
 146 #define GPIO_INTERRUPT_MASK (0)
 147
 148 /*  *********************************************************************
 149     *  Generic Bus
 150     ********************************************************************* */
 151
 152 #define BOOTROM_CS              0
 153 #define BOOTROM_PHYS            0x1FC00000      /* address of boot ROM (CS0) */
 154 #define BOOTROM_SIZE            NUM64K(4*MB)    /* size of boot ROM */
 155 #define BOOTROM_TIMING0         V_IO_ALE_WIDTH(4) | \
 156                                 V_IO_ALE_TO_CS(2) | \
 157                                 V_IO_CS_WIDTH(24) | \
 158                                 V_IO_RDY_SMPLE(1)
 159 #define BOOTROM_TIMING1         V_IO_ALE_TO_WRITE(7) | \
 160                                 V_IO_WRITE_WIDTH(7) | \
 161                                 V_IO_IDLE_CYCLE(6) | \
 162                                 V_IO_CS_TO_OE(0) | \
 163                                 V_IO_OE_TO_CS(0)
 164 #define BOOTROM_CONFIG          V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 165
 166 #define ALT_BOOTROM_CS          1
 167 #define ALT_BOOTROM_PHYS        0x1F800000      /* address of alternate boot ROM (CS1) */
 168 #define ALT_BOOTROM_SIZE        NUM64K(4*MB)    /* size of alternate boot ROM */
 169 #define ALT_BOOTROM_TIMING0     V_IO_ALE_WIDTH(4) | \
 170                                 V_IO_ALE_TO_CS(2) | \
 171                                 V_IO_CS_WIDTH(24) | \
 172                                 V_IO_RDY_SMPLE(1)
 173 #define ALT_BOOTROM_TIMING1     V_IO_ALE_TO_WRITE(7) | \
 174                                 V_IO_WRITE_WIDTH(7) | \
 175                                 V_IO_IDLE_CYCLE(6) | \
 176                                 V_IO_CS_TO_OE(0) | \
 177                                 V_IO_OE_TO_CS(0)
 178 #define ALT_BOOTROM_CONFIG      V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 179
 180
 181 /*
 182  * Xilinx:  non-multiplexed, byte width, no parity, no ack
 183  */
 184 #define XILINX_CS               2
 185 #define XILINX_PHYS             0x1F400000      /* address of Xilinx (CS2) */
 186 #define XILINX_SIZE             NUM64K(4*MB)    /* size of Xilinx */
 187 #define XILINX_TIMING0          V_IO_ALE_WIDTH(4) | \
 188                                 V_IO_ALE_TO_CS(2) | \
 189                                 V_IO_CS_WIDTH(24) | \
 190                                 V_IO_RDY_SMPLE(1)
 191 #define XILINX_TIMING1          V_IO_ALE_TO_WRITE(7) | \
 192                                 V_IO_WRITE_WIDTH(7) | \
 193                                 V_IO_IDLE_CYCLE(6) | \
 194                                 V_IO_CS_TO_OE(0) | \
 195                                 V_IO_OE_TO_CS(0)
 196 #define XILINX_CONFIG           V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 197
 198
 199
 200 /* Memory base for JTAG console registers (near end of the JTAG
 201    region) */
 202 #define C3_JTAG_CONS_BASE      (K_SCD_JTAG_MEMBASE+K_SCD_JTAG_MEMSIZE-0x80)
 203
 204 #define TEMPSENSOR_SMBUS_CHAN   0
 205 #define TEMPSENSOR_SMBUS_DEV    0x2A
 206 #define BIGEEPROM_SMBUS_CHAN    0
 207 #define BIGEEPROM_SMBUS_DEV     0x50
 208 #define X1240_SMBUS_CHAN        1
 209 #define X1240_SMBUS_DEV         0x50