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GUI: Fix Tomato RAF theme for all builds. Compilation typo.
[tomato.git] / release / src-rt-6.x.4708 / cfe / cfe / arch / mips / board / bcm9635x / include / 6352_map.h
blobf734d1dc87119fb5caab672491281356cece988f
1 /*
2 <:copyright-broadcom
3
4 Copyright (c) 2002 Broadcom Corporation
5 All Rights Reserved
6 No portions of this material may be reproduced in any form without the
7 written permission of:
8 Broadcom Corporation
9 16215 Alton Parkway
10 Irvine, California 92619
11 All information contained in this document is Broadcom Corporation
12 company private, proprietary, and trade secret.
13
14 :>
15 */
16 /***********************************************************************/
17 /* */
18 /* MODULE: 6352_map.h */
19 /* PURPOSE: Define addresses of major hardware components of */
20 /* BCM6352 */
21 /* */
22 /***********************************************************************/
23 #ifndef __BCM6352_MAP_H
24 #define __BCM6352_MAP_H
25
26 #if __cplusplus
27 extern "C" {
28 #endif
29
30 #include "bcmtypes.h"
31 #include "6352_common.h"
32
33 /* macro to convert logical data addresses to physical */
34 /* DMA hardware must see physical address */
35 #define LtoP( x ) ( (uint32)x & 0x1fffffff )
36 #define PtoL( x ) ( LtoP(x) | 0xa0000000 )
37
38 typedef enum {
39 LED_1A = 1,
40 LED_2B,
41 LED_3C,
42 LED_4D
43 }LEDDEFS;
44
45 #define LEDON 1
46 #define LEDOFF 0
47
48 /*
49 ** Sdram Controller
50 */
51 typedef struct SdramControllerRegs {
52 uint16 unused1;
53 uint16 initControl; /* 02 */
54 #define SD_POWER_DOWN 0x200 /* put sdram into power down */
55 #define SD_SELF_REFRESH 0x100 /* enable self refresh mode */
56 #define SD_SOFT_RESET 0x080 /* soft reset all sdram controller regs */
57 #define SD_EDO_SELECT 0x040 /* select EDO mode */
58 #define SD_EDO_WAIT_STATE 0x020 /* add an EDO wait state */
59 #define SD_8MEG 0x010 /* map sdram to 8 megs */
60 #define SD_MASTER_ENABLE 0x008 /* enable accesses to external sdram */
61 #define SD_MRS 0x004 /* generate a mode register select cycle */
62 #define SD_PRECHARGE 0x002 /* generate a precharge cycle */
63 #define SD_CBR 0x001 /* generate a refresh cycle */
64 uint8 unused2[3];
65 uint8 config; /* 07 */
66 #define SD_FAST_MEM 0x04 /* 1=CAS latency of 2, 0 = CAS latency of 3 */
67 #define SD_BURST_LEN 0x03 /* set burst length */
68 #define SD_BURST_FULL_PAGE 0x00 /* .. full page */
69 #define SD_BURST_8 0x01 /* .. 8 words */
70 #define SD_BURST_4 0x02 /* .. 4 words */
71 #define SD_BURST_2 0x03 /* .. 2 words */
72 uint16 unused3;
73 uint16 refreshControl; /* 0a */
74 #define SD_REFRESH_ENABLE 0x8000 /* refresh enable */
75 #define SD_REFRESH_PERIOD 0x00ff /* refresh period (16 x n x clock_period) */
76
77 uint32 memoryBase; /* 0c */
78 #define SD_MEMBASE_MASK 0xffffe000 /* base address mask */
79 #define SD_MEMSIZE_8MEG 0x00000001 /* memory is 8 meg */
80 #define SD_MEMSIZE_2MEG 0x00000001 /* memory is 2 meg */
81
82 } SdramControllerRegs;
83
84 /*
85 ** External Bus Interface
86 */
87 typedef struct EbiChipSelect {
88 uint32 base; /* base address in upper 24 bits */
89 #define EBI_SIZE_8K 0
90 #define EBI_SIZE_16K 1
91 #define EBI_SIZE_32K 2
92 #define EBI_SIZE_64K 3
93 #define EBI_SIZE_128K 4
94 #define EBI_SIZE_256K 5
95 #define EBI_SIZE_512K 6
96 #define EBI_SIZE_1M 7
97 #define EBI_SIZE_2M 8
98 #define EBI_SIZE_4M 9
99 #define EBI_SIZE_8M 10
100 #define EBI_SIZE_16M 11
101 #define EBI_SIZE_32M 12
102 #define EBI_SIZE_64M 13
103 #define EBI_SIZE_128M 14
104 #define EBI_SIZE_256M 15
105 uint32 config;
106 #define EBI_ENABLE 0x00000001 /* .. enable this range */
107 #define EBI_WAIT_STATES 0x0000000e /* .. mask for wait states */
108 #define EBI_WTST_SHIFT 1 /* .. for shifting wait states */
109 #define EBI_WORD_WIDE 0x00000010 /* .. 16-bit peripheral, else 8 */
110 #define EBI_WREN 0x00000020 /* enable posted writes */
111 #define EBI_POLARITY 0x00000040 /* .. set to invert something,
112 ** don't know what yet */
113 #define EBI_TS_TA_MODE 0x00000080 /* .. use TS/TA mode */
114 #define EBI_TS_SEL 0x00000100 /* .. drive tsize, not bs_b */
115 #define EBI_FIFO 0x00000200 /* .. use fifo */
116 #define EBI_RE 0x00000400 /* .. Reverse Endian */
117 } EbiChipSelect;
118
119 typedef struct EbiRegisters {
120 EbiChipSelect cs[6]; /* size chip select configuration */
121 uint32 reserved[4];
122 uint32 ebi_config; /* configuration */
123 #define EBI_MASTER_ENABLE 0x80000000 /* allow external masters */
124 #define EBI_EXT_MAST_PRIO 0x40000000 /* maximize ext master priority */
125 #define EBI_CTRL_ENABLE 0x20000000
126 #define EBI_TA_ENABLE 0x10000000
127 uint32 dma_control;
128 #define EBI_TX_INV_IRQ_EN 0x00080000
129 #define EBI_RX_INV_IRQ_EN 0x00040000
130 #define EBI_TX_PKT_DN_IRQ_EN 0x00020000
131 #define EBI_RX_PKT_DN_IRQ_EN 0x00010000
132 #define EBI_TX_INV_CLR 0x00001000
133 #define EBI_RX_INV_CLR 0x00000800
134 #define EBI_CHAINING 0x00000400
135 #define EBI_EXT_MODE 0x00000200
136 #define EBI_HALF_WORD 0x00000100
137 #define EBI_TX_PKT_DN_CLR 0x00000080
138 #define EBI_RX_PKT_DN_CLR 0x00000040
139 #define EBI_TX_BUF_DN_CLR 0x00000020
140 #define EBI_RX_BUF_DN_CLR 0x00000010
141 #define EBI_TX_BUF_DN_IRQ_EN 0x00000008
142 #define EBI_RX_BUF_DN_IRQ_EN 0x00000004
143 #define EBI_TX_EN 0x00000002
144 #define EBI_RX_EN 0x00000001
145 uint32 dma_rx_start_addr;
146 uint32 dma_rx_buf_size;
147 uint32 dma_tx_start_addr;
148 uint32 dma_tx_buf_size;
149 uint32 dma_status;
150 #define EBI_TX_INV_DESC 0x00000020
151 #define EBI_RX_INV_DESC 0x00000010
152 #define EBI_TX_PKT_DN 0x00000008
153 #define EBI_RX_PKT_DN 0x00000004
154 #define EBI_TX_BUF_DN 0x00000002
155 #define EBI_RX_BUF_DN 0x00000001
156 } EbiRegisters;
157
158 #define EBIC ((volatile EbiRegisters * const) EBIC_BASE)
159
160 /*
161 ** Bus Bridge Registers
162 */
163 typedef struct BusBridge {
164 uint16 status;
165 #define BB_BUSY 0x8000 /* posted operation in progress */
166 #define BB_RD_PND 0x4000 /* read pending */
167 #define BB_RD_CMPLT 0x2000 /* read complete */
168 #define BB_ERROR 0x1000 /* posted write error */
169 #define BB_TEA 0x0800 /* transfer aborted */
170 uint16 abortTimeoutCnt; /* abort timeout value */
171
172 byte writePostEnable;
173 #define BB_POST_DS_EN 0x40 /* post writes to downstream regs */
174 #define BB_POST_US_EN 0x20 /* post writes to upstream regs */
175 #define BB_POST_TRC_EN 0x10 /* post writes to trc regs */
176 #define BB_POST_TIMR_EN 0x08 /* post writes to timer regs */
177 #define BB_POST_GPIO_EN 0x04 /* post writes to gpio regs */
178 #define BB_POST_INTC_EN 0x02 /* post writes to interrupt controller regs */
179 #define BB_POST_UART_EN 0x01 /* post writes to uart regs */
180 byte unused1[5];
181 uint16 postAddr; /* posted read address (lower half) */
182 byte unused2[3];
183 byte postData; /* posted read data */
184 } BusBridge;
185
186 /* register offsets (needed for EBI master access) */
187 #define BB_STATUS 0
188 #define BB_ABORT_TO_CNT 2
189 #define BB_WR_POST_EN 4
190 #define BB_RD_POST_ADDR 10
191 #define BB_RD_POST_DATA 12
192
193 /*
194 ** Periph Bridge Registers
195 */
196 typedef struct PeriphBridge {
197 uint32 ormcfg;
198 uint32 apmcfg;
199 uint32 vpmcfg;
200 } PeriphBridge;
201
202 #define MTACTL ((volatile PeriphBridge * const) MTACTL_BASE)
203
204 /*
205 ** APM Registers
206 */
207 typedef struct {
208 uint16 RingFreqA1;
209 uint16 RingFreqB0;
210 uint16 RingScale;
211 uint16 RingOffset;
212 uint16 RingClip;
213 uint16 ResetPeriod;
214 uint32 HostIfCtrl;
215
216
217 // More to come...
218
219 } AudioProcessor;
220
221 #define APM ((volatile AudioProcessor * const) APM_BASE)
222
223 typedef struct CiMon {
224 uint16 debCntlCfg;
225 uint8 sendByte;
226 uint8 rcvByte;
227 } CiMon;
228
229 /* VPM configuration register bit defines */
230 #define VPMCFG_MM_VP_RST 0x00000001
231 #define VPMCFG_MM_VP_DSP_RST 0x00000002
232 #define VPMCFG_MM_FIFO_FLUSH 0x00000004
233 #define VPMCFG_PLL_EXTRSB 0x00000008
234 #define VPMCFG_PLL_IDDQ 0x00000010
235 #define VPMCFG_PLL_HG 0x00001000
236 #define VPMCFG_CLK_DIV_RST 0x00002000
237 #define VPMCFG_ENABLE_NMI 0x00004000
238 #define VPMCFG_FORCE_IBOOT 0x00008000
239 #define VPMCFG_TESTER_BENCH 0x00010000
240 #define VPMCFG_SM_TIC_BYP 0x00020000
241 #define VPMCFG_CLK_EN_DMA 0x00040000
242 #define VPMCFG_TDM_SEL_MSK 0xF0000000
243 #define VPMCFG_TDM_SEL_SHIFT 28
244 #define TDM_SEL_NORMAL 0
245 #define TDM_SEL_EXT_MASTER 1
246 #define TDM_SEL_EXT_SLAVE 2
247 #define TDM_SEL_PCM4 3
248 #define TDM_SEL_MON 4
249 #define TDM_SEL_APM_EXT 0xC
250 #define VPMCFG_PLL_FDIV_MSK 0x000000e0
251 #define VPMCFG_PLL_FDIV_SHIFT 5
252 #define VPMCFG_PLL_FSEL_MSK 0x00000f00
253 #define VPMCFG_PLL_FSEL_SHIFT 8
254 #define VPMCFG_PLL_HIGH_SHIFT 12
255
256 /* VPM configuration register default value */
257 #if EXTERNAL_QSLAC
258 #define VPMCFG_INIT VPMCFG_MM_FIFO_FLUSH | \
259 VPMCFG_PLL_IDDQ | \
260 1 << VPMCFG_PLL_FDIV_SHIFT | \
261 7 << VPMCFG_PLL_FSEL_SHIFT | \
262 TDM_SEL_EXT_SLAVE << VPMCFG_TDM_SEL_SHIFT
263 /* TDM_SEL_APM_EXT << VPMCFG_TDM_SEL_SHIFT*/
264 #else
265 /*
266 #define VPMCFG_INIT VPMCFG_MM_FIFO_FLUSH | \
267 VPMCFG_PLL_IDDQ | \
268 1 << VPMCFG_PLL_FDIV_SHIFT | \
269 7 << VPMCFG_PLL_FSEL_SHIFT | \
270 TDM_SEL_MON << VPMCFG_TDM_SEL_SHIFT
271 */
272
273 /* ZSP now is running 150Mhz */
274 #define VPMCFG_INIT VPMCFG_MM_FIFO_FLUSH | \
275 VPMCFG_PLL_IDDQ | \
276 1 << VPMCFG_PLL_FDIV_SHIFT | \
277 5 << VPMCFG_PLL_FSEL_SHIFT | \
278 1 << VPMCFG_PLL_HIGH_SHIFT | \
279 TDM_SEL_MON << VPMCFG_TDM_SEL_SHIFT
280
281 #endif
282
283
284 /*
285 ** VPM Register
286 */
287 typedef struct VpmReg {
288 uint8 timeSlot[64]; /* (0x00): PCM highway timeslots */
289 #define MAX_PCM_TIMESLOTS 128
290
291 uint16 pcmChanConfig; /* (0x40): PCM Channel Controller Configuration Register */
292 #define PCMCONFIG_RX_THRSH_MSK 0x000f
293 #define PCMCONFIG_RX_THRSH_SHIFT 0
294 #define PCMCONFIG_TX_THRSH_MSK 0x0f00
295 #define PCMCONFIG_TX_THRSH_SHIFT 8
296
297 uint8 fill[30];
298 CiMon ciMonRegs[4]; /* (0x60): CI/Monitor Configuration Register */
299
300 uint16 pcmClkConfig; /* (0x70): Clock configuration register */
301 #define CLKCONFIG_PCM_ENABLE 0x8000
302 #define CLKCONFIG_2MHZ 0x0002
303 #define CLKCONFIG_SYNCRATE_584KHZ 1
304 #define CLKCONFIG_SYNCRATE_256KHZ 0x0100
305 #define CLKCONFIG_SYNCRATE_SHIFT 8
306
307
308 uint16 pcmHwyIMR; /* (0x72): PCM Hwy Interrupt Mask Register */
309
310 uint16 pcmHwyISR; /* (0x74): PCM Hwy Interrupt Status Register */
311 uint8 padd[0x80-0x76]; /* not used */
312
313 uint16 mpiCommand; /* (0x80): MPI Command register */
314 #define COMMAND_SHIFT 0
315 #define SOFT_RESET_CMD 1
316 #define HARD_RESET_CMD 2
317 #define PANIC_RESET_CMD 3
318 #define START_IMMEDIATE_CMD 4
319 #define DEVICE_ID_SHIFT 4
320 #define PREPEND_BYTE_CNT_SHIFT 8
321 #define ONE_BYTE_SHIFT 11
322 #define ONE_WIRE_SHIFT 12
323
324 uint16 mpiIntStatus; /* (0x82): MPI Interrupt Status Register */
325 #define CMD_DONE_MASK 0x0001
326 #define CMD_DONE_CLEAR 1
327 #define CMD_CLEAR_ALL 0x1f
328
329 uint16 mpiIntMask; /* (0x84): MPI Interrupt Mask Register */
330 uint8 mpiStatus; /* (0x86): MPI Status Register */
331 #define MPI_FIFO_FULL_MASK 0x01
332 #define MPI_FIFO_EMPTY_MASK 0x02
333 #define MPI_CMD_BUSY_MASK 0x04
334 #define MPI_SERIAL_BUSY_MASK 0x08
335 uint8 mpiClkCfg; /* (0x87): MPI Clock Configuration Register */
336 #define MPI_4096MHZ_CLK 0
337 #define MPI_2048MHZ_CLK 1 /* Default */
338 #define MPI_1024MHZ_CLK 2
339 #define MPI_512MHZ_CLK 3
340 uint8 mpiFillByte; /* (0x88): MPI Fill Byte Register */
341 uint8 padd1[0x8C-0x89]; /* Not Used */
342 uint8 mpiData; /* (0x8C): MPI Data Register */
343 #define MPI_MSG_TYPE_SHIFT 6
344 #define MPI_BYTE_CNT_SHIFT 0
345 #define FULL_DUPLEX_RW 0
346 #define HALF_DUPLEX_W 1
347 #define HALF_DUPLEX_R 2
348
349 uint8 padd2[0xC0-0x8D]; /* not used */
350
351 uint16 mboxIntSts; /* (0xC0): Mailbox Interrupt Status to Modem Module */
352 uint16 mboxIntMsk; /* (0xC2): Interrupt Mask Register */
353 uint16 mbox0Recv; /* (0xC4): Mailbox 0 Receive Register */
354 uint16 mbox1Recv; /* (0xC6): Mailbox 1 Receive Register */
355 uint16 mbox0Msk; /* (0xC8): Mailbox 0 Mask Register */
356 uint16 mbox1Msk; /* (0xCA): Mailbox 1 Mask Register */
357 uint16 mbox0Send; /* (0xCC): Mailbox 0 Send Register */
358 uint16 mbox1Send; /* (0xCE): Mailbox 1 Send Register */
359 uint16 mmCtrl; /* (0xD0): Modem Module Control Register */
360 #define MM_CTRL_WR_PWR 0x0001
361 #define MM_CTRL_BIST_EN 0x0004
362
363 uint16 hldPwrMgmt; /* (0xD2): Holding Power Management Register */
364 uint16 pwrMgmt; /* (0xD4): Power Management Register */
365 #define PWR_SPEED_MSK 0x0003
366 #define CTRL_CLK_SPEED_SHIF 0
367
368 #define VPM_NO_CLOCK 0
369 #define VPM_QUARTER_SPEED 1
370 #define VPM_HALF_SPEED 2
371 #define VPM_FULL_SPEED 3
372
373 uint16 diagCtrl; /* (0xD6): Diagnostic Control Register */
374 #define DIAG_CLK_SEL_MSK 0xE000
375 #define DIAG_CLK_SEL_SHIFT 13
376
377 #define DIAG_CLK_NULL 0
378 #define DIAG_CLK_DSP 1
379 #define DIAG_CLK_8192 2
380 #define DIAG_CLK_4096 3
381 #define DIAG_CLK_PCLKD2 4
382 #define DIAG_CLK_8 5
383
384
385 #define DIAG_MOD_SEL_MSK 0x00F0
386 #define DIAG_MOD_SEL_SHIFT 4
387
388 #define DIAG_BUS_SEL_MSK 0x000F
389 #define DIAG_BUS_SEL_SHIFT 0
390 } VpmReg;
391
392 #define VPM ((volatile VpmReg * const) VPM_BASE)
393
394
395 /*
396 ** Interrupt Controller
397 */
398 typedef struct IntControl {
399 uint32 RevID; /* (00) */
400 #define CHIPID 0x635207a0
401 #define SECMOD_EN 0x400
402 #define DES3_EN 0x200
403 #define DES56_EN 0x100
404 uint16 testControl; /* (04) */
405 uint16 blkEnables; /* (06) */
406
407 #define HDLC_CLK_EN 0x0800
408 #define SEC_CLK_EN 0x0400
409 #define USB_CLK_EN 0x0100
410 #define ESWITCH_CLK_EN 0x0080
411 #define EPHY_CLK_EN 0x0040
412 #define ATM_CLK_EN 0x0010
413 #define UART_CLK_EN 0x0008
414 #define EBI_CLK_EN 0x0004
415 #define BUS_CLK_EN 0x0002
416 #define CPU_CLK_EN 0x0001
417
418 uint16 pll_control; /* (08) */
419 /* Bits [15:12] micro_pll: default 6
420 * Bits [7:4] usb_pll : default 7
421 * Bits [2:0] usb_pll_div : default 0
422 */
423 byte diagControl; /* (0a) */
424 /* Bits [6:4] diag12
425 * Bits [2:0] diag16
426 */
427 byte control; /* (0b) */
428 #define SOFT_RESET 0x10
429 #define QUIET_XTAL 0x08
430 #define USPHY_BYP 0x04
431 #define DSPHY_BYP 0x02
432 #define USBPHY_BYP 0x01
433
434 uint32 IrqMask; /* (0c) */
435 #define DMACH18 0x80000000
436 #define DMACH17 0x40000000
437 #define DMACH16 0x20000000
438 #define DMACH15 0x10000000
439 #define DMACH14 0x08000000
440 #define DMACH13 0x04000000
441 #define DMACH12 0x02000000
442 #define DMACH11 0x01000000
443 #define DMACH10 0x00800000
444 #define DMACH09 0x00400000
445 #define DMACH08 0x00200000
446 #define DMACH07 0x00100000
447 #define DMACH06 0x00080000
448 #define DMACH05 0x00040000
449 #define DMACH04 0x00020000
450 #define DMACH03 0x00010000
451 #define DMACH02 0x00008000
452 #define DMACH01 0x00004000
453
454 #define VPMIRQ 0x00000800
455 #define PCMIRQ 0x00000400
456 #define EPHYIRQ 0x00000200
457 #define ESWITCHIRQ 0x00000100
458 #define HDLCIRQ 0x00000080
459 #define SECIRQ 0x00000040
460 #define USBIRQ 0x00000020
461 #define ATMIRQ 0x00000008
462 #define UART0IRQ 0x00000004
463 #define UART1IRQ 0x00000002
464 #define TIMRIRQ 0x00000001
465
466 uint32 IrqStatus; /* (10) */
467 byte unused3; /* (14) */
468
469 /* Upper 4 bits set to 1 to use level, set to 0 to use edge */
470 /* Lower 4 bits set disable edge sensitivity */
471 byte extLevelEdgeInsense;
472
473 /* Upper 4 bits enable corresponding ExtIrq, Lower 4 bits clr IRQ */
474 byte extIrqMskandDetClr;
475
476 /* Upper 4 bits are current status of input, lower bits define edge
477 * sensitivity. If high, IRQ on rising edge. If low, IRQ on falling edge
478 */
479 byte extIrqStatEdgeConfig;
480 } IntControl;
481
482 #define INTC ((volatile IntControl * const) INTC_BASE)
483
484 /*
485 ** Gpio Controller
486 */
487 typedef struct GpioControl {
488 uint16 unused0;
489 byte unused1;
490 byte TBusSel;
491
492 /* High in bit location enables output */
493 uint16 unused2;
494 uint16 GPIODir;
495 byte unused3;
496 byte Leds; //Only bits [3:0]
497 uint16 GPIOio;
498
499 /* Defines below show which bit enables which UART signals */
500 uint32 UartCtl;
501 #define RI1_EN 0x0001
502 #define CTS1_EN 0x0002
503 #define DCD1_EN 0x0004
504 #define DSR1_EN 0x0008
505 #define DTR1_EN 0x0010
506 #define RTS1_EN 0x0020
507 #define DO1_EN 0x0040
508 #define DI1_EN 0x0080
509 #define RI0_EN 0x0100
510 #define CTS0_EN 0x0200
511 #define DCD0_EN 0x0400
512 #define DSR0_EN 0x0800
513 #define DTR0_EN 0x1000
514 #define RTS0_EN 0x2000
515
516 /*********************************************************************
517 * Multiple Use Muxed GPIO
518 * -----------------------
519 *
520 * ------
521 * GPIO_A
522 * ------
523 *
524 * GPIO[0] -> RI1 I Controlled by UartCtl[0] ELSE 0
525 * GPIO[0] -> DMATC_i I Always
526 * GPIO[0] -> DMATC_o O Controlled by dma_enable_n|dma_drive_n
527 * GPIO[0] -> ebi_bsize[0] I Always
528 *
529 * GPIO[1] -> CTS1 I Controlled by UartCtl[1] ELSE 0
530 * GPIO[1] -> DMAACK1 (18) O Controlled by dma_enable_n
531 * GPIO[1] -> ebi_bg_b O Controlled by ebi_master_n
532 *
533 * GPIO[2] -> DCD1 I Controlled by UartCtl[2] ELSE 0
534 * GPIO[2] -> ebi_bsize[1] I Always
535 *
536 * GPIO[3] -> DSR1 I Controlled by UartCtl[3] ELSE 0
537 * GPIO[3] -> INT2 I Always
538 * GPIO[3] -> ebi_bsize[2] I Always
539 *
540 * GPIO[4] -> DTR1 O Controlled by UartCtl[4]&GpioDir[4]
541 * GPIO[4] -> INT3 I Always
542 * GPIO[4] -> ebi_burst I Always
543 *
544 * GPIO[5] -> RTS1 O Controlled by UartCtl[5]&GpioDir[5]
545 * GPIO[5] -> DMAACK0 (17) O Controlled by dma_enable_n
546 * GPIO[5] -> ebi_tsize I Always
547 *
548 * GPIO[6] -> sDout1 O Controlled by UartCtl[6]&GpioDir[6]
549 * GPIO[6] -> DMARQ1 (18) I Always
550 * GPIO[6] -> ebi_bb_i I Always
551 * GPIO[6] -> ebi_bb_o O Controlled by ebi_master_n|ebi_bb_oen
552 *
553 * GPIO[7] -> sDin1 I Controlled by UartCtl[7] ELSE 0
554 * GPIO[7] -> ebi_br_b I Always
555 * GPIO[7] -> DMARQ0 (17) I Always
556 *
557 * ------
558 * GPIO_B
559 * ------
560 *
561 * GPIO[8] -> RI0 I Controlled by UartCtl[8] ELSE 0
562 * GPIO[8] -> ebi_cs_b[6] O Controlled by ebi_cs_en[6]
563 *
564 * GPIO[9] -> CTS0 I Controlled by UartCtl[9] ELSE 0
565 *
566 * GPIO[a] -> DCD0 I Controlled by UartCtl[a] ELSE 0
567 * GPIO[a] -> ebi_cs_b[7] O Controlled by ebi_cs_en[7]
568 *
569 * GPIO[b] -> DSR0 I Controlled by UartCtl[b] ELSE 0
570 * GPIO[b] -> ebi_int_cs_b I Always
571 *
572 * GPIO[c] -> DTR0 O Controlled by UartCtl[c]&GpioDir[c]
573 *
574 * GPIO[d] -> RTS0 O Controlled by UartCtl[d]&&GpioDir[d]
575 *
576 * GPIO[e] -> INT0 I Always
577 *
578 * GPIO[f] -> INT1 I Always
579 *
580 * sDout0 -> (bist_en[15]) ? pll_clk48:sDout0_int
581 *
582 *********************************************************************/
583
584 } GpioControl;
585
586 #define GPIO ((volatile GpioControl * const) GPIO_BASE)
587
588 /*
589 ** Timer
590 */
591 typedef struct Timer {
592 uint16 unused0;
593 byte TimerMask;
594 #define TIMER0EN 0x01
595 #define TIMER1EN 0x02
596 #define TIMER2EN 0x04
597 byte TimerInts;
598 #define TIMER0 0x01
599 #define TIMER1 0x02
600 #define TIMER2 0x04
601 #define WATCHDOG 0x08
602 uint32 TimerCtl0;
603 uint32 TimerCtl1;
604 uint32 TimerCtl2;
605 #define TIMERENABLE 0x80000000
606 #define RSTCNTCLR 0x40000000
607 uint32 TimerCnt0;
608 uint32 TimerCnt1;
609 uint32 TimerCnt2;
610 uint32 WatchDogDefCount;
611
612 /* Write 0xff00 0x00ff to Start timer
613 * Write 0xee00 0x00ee to Stop and re-load default count
614 * Read from this register returns current watch dog count
615 */
616 uint32 WatchDogCtl;
617
618 /* Number of 40-MHz ticks for WD Reset pulse to last */
619 uint32 WDResetCount;
620 } Timer;
621
622 #define TIMER ((volatile Timer * const) TIMR_BASE)
623
624 /*
625 ** UART
626 */
627 typedef struct Uart {
628 byte unused0;
629 byte control;
630 #define BRGEN 0x80 /* Control register bit defs */
631 #define TXEN 0x40
632 #define RXEN 0x20
633 #define LOOPBK 0x10
634 #define TXPARITYEN 0x08
635 #define TXPARITYEVEN 0x04
636 #define RXPARITYEN 0x02
637 #define RXPARITYEVEN 0x01
638
639 byte config;
640 #define XMITBREAK 0x40
641 #define BITS5SYM 0x00
642 #define BITS6SYM 0x10
643 #define BITS7SYM 0x20
644 #define BITS8SYM 0x30
645 #define ONESTOP 0x07
646 #define TWOSTOP 0x0f
647 /* 4-LSBS represent STOP bits/char
648 * in 1/8 bit-time intervals. Zero
649 * represents 1/8 stop bit interval.
650 * Fifteen represents 2 stop bits.
651 */
652 byte fifoctl;
653 #define RSTTXFIFOS 0x80
654 #define RSTRXFIFOS 0x40
655 /* 5-bit TimeoutCnt is in low bits of this register.
656 * This count represents the number of characters
657 * idle times before setting receive Irq when below threshold
658 */
659 uint32 baudword;
660 /* When divide SysClk/2/(1+baudword) we should get 32*bit-rate
661 */
662
663 byte txf_levl; /* Read-only fifo depth */
664 byte rxf_levl; /* Read-only fifo depth */
665 byte fifocfg; /* Upper 4-bits are TxThresh, Lower are
666 * RxThreshold. Irq can be asserted
667 * when rx fifo> thresh, txfifo<thresh
668 */
669 byte prog_out; /* Set value of DTR (Bit0), RTS (Bit1)
670 * if these bits are also enabled to GPIO_o
671 */
672 #define DTREN 0x01
673 #define RTSEN 0x02
674
675 byte unused1;
676 byte DeltaIPEdgeNoSense; /* Low 4-bits, set corr bit to 1 to
677 * detect irq on rising AND falling
678 * edges for corresponding GPIO_i
679 * if enabled (edge insensitive)
680 */
681 byte DeltaIPConfig_Mask; /* Upper 4 bits: 1 for posedge sense
682 * 0 for negedge sense if
683 * not configured for edge
684 * insensitive (see above)
685 * Lower 4 bits: Mask to enable change
686 * detection IRQ for corresponding
687 * GPIO_i
688 */
689 byte DeltaIP_SyncIP; /* Upper 4 bits show which bits
690 * have changed (may set IRQ).
691 * read automatically clears bit
692 * Lower 4 bits are actual status
693 */
694
695 uint16 intMask; /* Same Bit defs for Mask and status */
696 uint16 intStatus;
697 #define DELTAIP 0x0001
698 #define TXUNDERR 0x0002
699 #define TXOVFERR 0x0004
700 #define TXFIFOTHOLD 0x0008
701 #define TXREADLATCH 0x0010
702 #define TXFIFOEMT 0x0020
703 #define RXUNDERR 0x0040
704 #define RXOVFERR 0x0080
705 #define RXTIMEOUT 0x0100
706 #define RXFIFOFULL 0x0200
707 #define RXFIFOTHOLD 0x0400
708 #define RXFIFONE 0x0800
709 #define RXFRAMERR 0x1000
710 #define RXPARERR 0x2000
711 #define RXBRK 0x4000
712
713 uint16 unused2;
714 uint16 Data; /* Write to TX, Read from RX */
715 /* bits 11:8 are BRK,PAR,FRM errors */
716
717 uint32 unused3;
718 uint32 unused4;
719 } Uart;
720
721
722 /* paste in your program ...
723 UartChannel *uartChannels = (UartChannel *)UART_BASE;
724 */
725
726 /*
727 ** DMA Channel (1 .. 20)
728 */
729 typedef struct DmaChannel {
730 uint32 cfg; /* (00) assorted configuration */
731 #define DMA_FLOWC_EN 0x00000010 /* flow control enable */
732 #define DMA_WRAP_EN 0x00000008 /* use DMA_WRAP bit */
733 #define DMA_CHAINING 0x00000004 /* chaining mode */
734 #define DMA_STALL 0x00000002
735 #define DMA_ENABLE 0x00000001 /* set to enable channel */
736 uint32 maxBurst; /* (04) max burst length permitted */
737 /* non-chaining / chaining */
738 uint32 startAddr; /* (08) source addr / ring start address */
739 uint32 length; /* (0c) xfer len / ring len */
740 #define DMA_KICKOFF 0x80000000 /* start non-chaining xfer */
741
742 uint32 bufStat; /* (10) buffer status for non-chaining */
743 uint32 intStat; /* (14) interrupts control and status */
744 uint32 intMask; /* (18) interrupts mask */
745 #define DMA_BUFF_DONE 0x00000001 /* buffer done */
746 #define DMA_DONE 0x00000002 /* packet xfer complete */
747 #define DMA_NO_DESC 0x00000004 /* no valid descriptors */
748
749 // DMA HW bits are clugy in this version of chip (mask/status shifted)
750 #define DMA_BUFF_DONE_MASK 0x00000004 /* buffer done */
751 #define DMA_DONE_MASK 0x00000001 /* packet xfer complete */
752 #define DMA_NO_DESC_MASK 0x00000002 /* no valid descriptors */
753
754 uint32 fcThreshold; /* (1c) flow control threshold */
755 uint32 numAlloc; /* */
756 uint32 unused[7]; /* (20-3c) pad to next descriptor */
757 } DmaChannel;
758 /* register offsets, useful for ebi master access */
759 #define DMA_CFG 0
760 #define DMA_MAX_BURST 4
761 #define DMA_START_ADDR 8
762 #define DMA_LENGTH 12
763 #define DMA_BUF_STAT 16
764 #define DMA_INT_STAT 20
765 #define DMA_FC_THRESHOLD 24
766 #define DMA_NUM_ALLOC 28
767
768
769 /* paste in your program ...
770 DmaChannel *dmaChannels = (DmaChannel *)DMA_BASE;
771 DmaChannel *dma1 = dmaChannels[1];
772 */
773
774
775 /*
776 ** DMA Buffer
777 */
778 typedef struct DmaDesc {
779 uint16 length; /* in bytes of data in buffer */
780 uint16 status; /* buffer status */
781 #define DMA_OWN 0x8000 /* cleared by DMA, set by SW */
782 #define DMA_EOP 0x0800 /* last buffer in packet */
783 #define DMA_SOP 0x0400 /* first buffer in packet */
784 #define DMA_WRAP 0x0200 /* */
785 #define DMA_APPEND_CRC 0x0100 /* .. for emac tx */
786 #define DATA_FLAG 0x0100 /* .. for secmod rx */
787 #define AUTH_FAIL_FLAG 0x0100 /* .. for secmod tx */
788
789 /* EMAC Descriptor Status definitions */
790 #define EMAC_UNDERRUN 0x4000 /* Tx underrun, dg-mod ???) */
791 #define EMAC_MISS 0x0080 /* framed address recognition failed (promiscuous) */
792 #define EMAC_BRDCAST 0x0040 /* DA is Broadcast */
793 #define EMAC_MULT 0x0020 /* DA is multicast */
794 #define EMAC_LG 0x0010 /* frame length > RX_LENGTH register value */
795 #define EMAC_NO 0x0008 /* Non-Octet aligned */
796 #define EMAC_RXER 0x0004 /* RX_ERR on MII while RX_DV assereted */
797 #define EMAC_CRC_ERROR 0x0002 /* CRC error */
798 #define EMAC_OV 0x0001 /* Overflow */
799
800 /* HDLC Descriptor Status definitions */
801 #define DMA_HDLC_TX_ABORT 0x0100
802 #define DMA_HDLC_RX_OVERRUN 0x4000
803 #define DMA_HDLC_RX_TOO_LONG 0x2000
804 #define DMA_HDLC_RX_CRC_OK 0x1000
805 #define DMA_HDLC_RX_ABORT 0x0100
806
807 uint32 address; /* address of data */
808 } DmaDesc;
809 #define DMA_DESC_LENGTH 0
810 #define DMA_DESC_STATUS 2
811 #define DMA_DESC_ADDR 4
812
813 /*
814 ** EMAC transmit MIB counters
815 */
816 typedef struct EmacTxMib {
817 uint32 tx_good_octets; /* (200) good byte count */
818 uint32 tx_good_pkts; /* (204) good pkt count */
819 uint32 tx_octets; /* (208) good and bad byte count */
820 uint32 tx_pkts; /* (20c) good and bad pkt count */
821 uint32 tx_broadcasts_pkts; /* (210) good broadcast packets */
822 uint32 tx_multicasts_pkts; /* (214) good mulitcast packets */
823 uint32 tx_len_64; /* (218) RMON tx pkt size buckets */
824 uint32 tx_len_65_to_127; /* (21c) */
825 uint32 tx_len_128_to_255; /* (220) */
826 uint32 tx_len_256_to_511; /* (224) */
827 uint32 tx_len_512_to_1023; /* (228) */
828 uint32 tx_len_1024_to_max; /* (22c) */
829 uint32 tx_jabber_pkts; /* (230) > 1518 with bad crc */
830 uint32 tx_oversize_pkts; /* (234) > 1518 with good crc */
831 uint32 tx_fragment_pkts; /* (238) < 63 with bad crc */
832 uint32 tx_underruns; /* (23c) fifo underrun */
833 uint32 tx_total_cols; /* (240) total collisions in all tx pkts */
834 uint32 tx_single_cols; /* (244) tx pkts with single collisions */
835 uint32 tx_multiple_cols; /* (248) tx pkts with multiple collisions */
836 uint32 tx_excessive_cols; /* (24c) tx pkts with excessive cols */
837 uint32 tx_late_cols; /* (250) tx pkts with late cols */
838 uint32 tx_defered; /* (254) tx pkts deferred */
839 uint32 tx_carrier_lost; /* (258) tx pkts with CRS lost */
840 uint32 tx_pause_pkts; /* (25c) tx pause pkts sent */
841 #define NumEmacTxMibVars 24
842 } EmacTxMib;
843
844 /*
845 ** EMAC receive MIB counters
846 */
847 typedef struct EmacRxMib {
848 uint32 rx_good_octets; /* (280) good byte count */
849 uint32 rx_good_pkts; /* (284) good pkt count */
850 uint32 rx_octets; /* (288) good and bad byte count */
851 uint32 rx_pkts; /* (28c) good and bad pkt count */
852 uint32 rx_broadcasts_pkts; /* (290) good broadcast packets */
853 uint32 rx_multicasts_pkts; /* (294) good mulitcast packets */
854 uint32 rx_len_64; /* (298) RMON rx pkt size buckets */
855 uint32 rx_len_65_to_127; /* (29c) */
856 uint32 rx_len_128_to_255; /* (2a0) */
857 uint32 rx_len_256_to_511; /* (2a4) */
858 uint32 rx_len_512_to_1023; /* (2a8) */
859 uint32 rx_len_1024_to_max; /* (2ac) */
860 uint32 rx_jabber_pkts; /* (2b0) > 1518 with bad crc */
861 uint32 rx_oversize_pkts; /* (2b4) > 1518 with good crc */
862 uint32 rx_fragment_pkts; /* (2b8) < 63 with bad crc */
863 uint32 rx_missed_pkts; /* (2bc) missed packets */
864 uint32 rx_crc_align_errs; /* (2c0) both or either */
865 uint32 rx_undersize; /* (2c4) < 63 with good crc */
866 uint32 rx_crc_errs; /* (2c8) crc errors (only) */
867 uint32 rx_align_errs; /* (2cc) alignment errors (only) */
868 uint32 rx_symbol_errs; /* (2d0) pkts with RXERR assertions (symbol errs) */
869 uint32 rx_pause_pkts; /* (2d4) MAC control, PAUSE */
870 uint32 rx_nonpause_pkts; /* (2d8) MAC control, not PAUSE */
871 #define NumEmacRxMibVars 23
872 } EmacRxMib;
873
874 /*
875 ** EMAC Registers
876 */
877 typedef struct EmacRegisters {
878 uint32 rxControl; /* (00) receive control */
879 #define EMAC_UNIFLOW 0x40 /* - accept cam match fc */
880 #define EMAC_FC_EN 0x20 /* - enable flow control */
881 #define EMAC_LOOPBACK 0x10 /* - loopback */
882 #define EMAC_PROM 0x08 /* - promiscuous */
883 #define EMAC_RDT 0x04 /* - ignore transmissions */
884 #define EMAC_ALL_MCAST 0x02 /* - ignore transmissions */
885 #define EMAC_NO_BCAST 0x01 /* - ignore transmissions */
886
887
888 uint32 rxMaxLength; /* (04) receive max length */
889 uint32 txMaxLength; /* (08) transmit max length */
890 uint32 unused1[1];
891 uint32 mdioFreq; /* (10) mdio frequency */
892 #define EMAC_MII_PRE_EN 0x0100 /* prepend preamble sequence */
893 #define EMAC_MDIO_PRE 0x100 /* - enable MDIO preamble */
894 #define EMAC_MDC_FREQ 0x0ff /* - mdio frequency */
895
896 uint32 mdioData; /* (14) mdio data */
897 #define MDIO_WR 0x50020000 /* - write framing */
898 #define MDIO_RD 0x60020000 /* - read framing */
899 #define MDIO_PMD_SHIFT 23
900 #define MDIO_REG_SHIFT 18
901
902 uint32 intMask; /* (18) int mask */
903 uint32 intStatus; /* (1c) int status */
904 #define EMAC_FLOW_INT 0x04 /* - flow control event */
905 #define EMAC_MIB_INT 0x02 /* - mib event */
906 #define EMAC_MDIO_INT 0x01 /* - mdio event */
907
908 uint32 camDataLo; /* (20) cam data lo */
909 uint32 camDataHi; /* (24) cam data hi (15:0) */
910 #define EMAC_CAM_V 0x10000 /* - cam index */
911 #define EMAC_CAM_VALID 0x00010000
912
913 uint32 camControl; /* (28) cam control */
914 #define EMAC_CAM_BUSY 0x80000000 /* - cam BUSY */
915 #define EMAC_CAM_INDEX 0x3f0 /* - cam index */
916 #define EMAC_CAM_WRITE 0x008 /* - cam write */
917 #define EMAC_CAM_READ 0x004 /* - cam read */
918 #define EMAC_CAM_MKRSL 0x002 /* - cam mask reg sel */
919 #define EMAC_CAM_EN 0x001 /* - cam enable */
920
921 uint32 config; /* (2c) config */
922 #define EMAC_ENABLE 0x001 /* - enable emac */
923 #define EMAC_DISABLE 0x002 /* - disable emac */
924 #define EMAC_SOFT_RST 0x004 /* - soft reset */
925 #define EMAC_SOFT_RESET 0x004 /* - emac soft reset */
926 #define EMAC_EXT_PHY 0x008 /* - external PHY select */
927
928 uint32 txControl; /* (30) transmit control */
929 #define EMAC_FD 0x001 /* - full duplex */
930 #define EMAC_FLOWMODE 0x002 /* - flow mode */
931 #define EMAC_NOBKOFF 0x004 /* - no backoff in */
932 #define EMAC_SMALLSLT 0x008 /* - small slot time */
933
934 uint32 txThreshold; /* (34) transmit threshold */
935 uint32 mibControl; /* (38) mib control */
936 #define EMAC_NO_CLEAR 0x001 /* don't clear on read */
937
938 uint32 unused2[48]; /* (3c-fc) */
939
940 uint32 cam[64]; /* (100) cam access */
941
942 EmacTxMib tx_mib; /* (200) emac tx mib */
943 uint32 unused3[8]; /* (260-27c) */
944
945 EmacRxMib rx_mib; /* (280) rx mib */
946 uint32 unused4[10]; /* (2dc-2fc) */
947
948 uint32 txfifo[64]; /* (300) tx fifo access */
949
950 uint32 rxfifo[64]; /* (400) rx fifo access */
951
952 } EmacRegisters;
953
954 /* register offsets for subrouting access */
955 #define EMAC_RX_CONTROL 0x00
956 #define EMAC_RX_MAX_LENGTH 0x04
957 #define EMAC_TX_MAC_LENGTH 0x08
958 #define EMAC_MDIO_FREQ 0x10
959 #define EMAC_MDIO_DATA 0x14
960 #define EMAC_INT_MASK 0x18
961 #define EMAC_INT_STATUS 0x1C
962 #define EMAC_CAM_DATA_LO 0x20
963 #define EMAC_CAM_DATA_HI 0x24
964 #define EMAC_CAM_CONTROL 0x28
965 #define EMAC_CONTROL 0x2C
966 #define EMAC_TX_CONTROL 0x30
967 #define EMAC_TX_THRESHOLD 0x34
968 #define EMAC_MIB_CONTROL 0x38
969
970
971 #define EMAC ((volatile EmacRegisters * const) EMAC_BASE)
972
973 /*
974 ** USB Registers
975 */
976 typedef struct UsbRegisters {
977 byte inttf_setting;
978 byte current_config;
979 uint16 status_frameNum;
980 #define USB_BUS_RESET 0x1000
981 #define USB_SUSPENDED 0x0800
982 byte unused1;
983 byte endpt_prnt;
984 byte endpt_dirn;
985 byte endpt_status;
986 #define USB_ENDPOINT_0 0x01
987 #define USB_ENDPOINT_1 0x02
988 #define USB_ENDPOINT_2 0x04
989 #define USB_ENDPOINT_3 0x08
990 #define USB_ENDPOINT_4 0x10
991 #define USB_ENDPOINT_5 0x20
992 #define USB_ENDPOINT_6 0x40
993 #define USB_ENDPOINT_7 0x80
994 uint32 unused2;
995 byte conf_mem_ctl;
996 #define USB_CONF_MEM_RD 0x80
997 #define USB_CONF_MEM_RDY 0x40
998 byte unused2a;
999 byte conf_mem_read_address;
1000 byte conf_mem_write_address;
1001
1002 byte unused3;
1003 byte dev_req_bytesel;
1004 uint16 ext_dev_data;
1005
1006 byte unused4;
1007 byte clr_fifo;
1008 byte endpt_stall_reset; // use same endpoint #'s from above
1009 byte usb_cntl;
1010 #define USB_FORCE_ERR 0x20
1011 #define USB_SOFT_RESET 0x10
1012 #define USB_RESUME 0x08
1013 #define USB_COMMAND_ERR 0x04
1014 #define USB_COMMAND_OVER 0x02
1015 byte irq_addr;
1016 byte iso_out_in_addr;
1017 byte blk_out_in_addr;
1018 byte cntl_addr;
1019 uint32 mux_cntl;
1020 #define USB_TX_DMA_OPER 0x00000000
1021 #define USB_TX_CNTL_FIFO_OPER 0x00000004
1022 #define USB_TX_BULK_FIFO_OPER 0x00000008
1023 #define USB_TX_ISO_FIFO_OPER 0x0000000c
1024 #define USB_TX_IRQ_OPER 0x00000010
1025 #define USB_RX_DMA_OPER 0x00000000
1026 #define USB_RX_CNTL_FIFO_OPER 0x00000001
1027 #define USB_RX_BULK_FIFO_OPER 0x00000002
1028 #define USB_RX_ISO_FIFO_OPER 0x00000003
1029 uint32 rx_ram_read_port;
1030 uint32 tx_ram_write_port;
1031 uint32 fifo_status;
1032 #define USB_CTRLI_FIFO_FULL 0x00000001
1033 #define USB_CTRLI_FIFO_EMPTY 0x00000002
1034 #define USB_CTRLO_FIFO_FULL 0x00000100
1035 #define USB_CTRLO_FIFO_EMPTY 0x00000200
1036 uint32 irq_status;
1037 uint32 irq_mask;
1038 #define USB_NEW_CONFIG 0x01
1039 #define USB_SETUP_COMMAND_RECV 0x02 // non-standard setup command received
1040 #define USB_OUT_FIFO_OV 0x04
1041 #define USB_RESET_RECV 0x08
1042 #define USB_SUSPEND_RECV 0x10
1043 #define USB_FIFO_REWIND 0x20
1044 #define USB_RX_BULK_FIFO_DATA_AVAIL 0x40
1045 #define USB_RX_ISO_FIFO_DATA_AVAIL 0x80
1046 uint32 endpt_cntl;
1047 #define USB_TX_EOP 0x0200
1048 #define USB_R_WK_EN 0x0100
1049 uint32 rx_status_read_port;
1050 uint32 confmem_read_port;
1051 uint32 confmem_write_port;
1052 uint32 fifo_ovf_count;
1053 uint32 fifo_rewind_cnt;
1054 } UsbRegisters;
1055
1056 #define USB ((volatile UsbRegisters * const) USB_BASE)
1057
1058 typedef struct HdlcRegisters {
1059 uint32 config;
1060 #define HDLC_TX_EN 0x00000001
1061 #define HDLC_RX_EN 0x00000002
1062 #define HDLC_FLAG_IDLE 0x00000004
1063 #define HDLC_TX_TRANSP 0x00000010
1064 #define HDLC_RX_TRANSP 0x00000020
1065 #define HDLC_LOOPBACK 0x00000040
1066 #define HDLC_RESET 0x00000080
1067 #define HDLC_TX_NEGEDGE 0x00000100
1068 #define HDLC_RX_NEGEDGE 0x00000200
1069 uint32 max_frame;
1070 uint32 irq_status;
1071 uint32 irq_mask;
1072 #define HDLC_INT_IDLE 0x00000001
1073 #define HDLC_INT_ABORT 0x00000002
1074 #define HDLC_INT_EOP 0x00000004
1075 #define HDLC_INT_CRC_ERROR 0x00000008
1076 #define HDLC_INT_RX_TOO_SHORT 0x00000010
1077 #define HDLC_INT_RX_TOO_LONG 0x00000020
1078 #define HDLC_RX_UNDERFLOW 0x00000040
1079 #define HDLC_RX_OVERFLOW 0x00000080
1080 #define HDLC_TX_UNDERFLOW 0x00000100
1081 #define HDLC_TX_OVERFLOW 0x00000200
1082 #define HDLC_RX_DMA 0x00000400
1083 #define HDLC_TX_DMA 0x00000800
1084
1085 uint32 unused1[4];
1086
1087 uint32 rx_good_count;
1088 uint32 rx_crc_error_count;
1089 uint32 rx_about_count;
1090 uint32 hdlc_status;
1091 uint32 tx_fifo_ctrl_status;
1092 uint32 rx_fifo_ctrl_status;
1093 uint32 rx_status_fifo_info;
1094 uint32 rx_data_fifo_info;
1095
1096 uint32 unused2[10];
1097
1098 uint32 tx_data_fifo;
1099 uint32 rx_data_fifo;
1100 } HdlcRegisters;
1101
1102 #define HDLC ((volatile HdlcRegisters * const) HDLC_BASE)
1103
1104 /*
1105 ** Security Module Register Set
1106 */
1107 typedef struct SecmodRegisters {
1108 byte DesBlkCntr; /* (00) */
1109 byte AuthBlkCntr; /* (01) */
1110 uint16 SecModCtrlReg; /* (02) */
1111
1112 #define SMSFTRST 0x8000
1113 #define SMRESTART 0x4000
1114 #define MPUDESIVRDY 0x2000
1115 #define MPUDESKEYRDY 0x1000
1116 #define SMDESGOBSY 0x0800
1117 #define SMAUTHGOBSY 0x0400
1118
1119 #define SMMPUTESTMODE 0x0040
1120 #define ECHOAUTHSRCOUT 0x0020
1121 #define SMENCENABLE 0x0010
1122 #define SM3DESENABLE 0x0008
1123 #define SMCBCENABLE 0x0004
1124 #define SMECBENABLE 0x0000
1125 #define SMMD5ENABLE 0x0002
1126 #define SMSHAENABLE 0x0000
1127 #define SMAUTHSTART 0x0001
1128 byte unused0; // (4)
1129 byte IrqMask; // (5)
1130 byte unused1; // (6)
1131 byte Irq; // (7)
1132 #define SMTXUND 0x0001
1133 #define SMRXOVF 0x0002
1134 #define SMDESFMT 0x0004
1135 #define SMAUTHFMT 0x0008
1136 #define SMCNTRLFMG 0x0010
1137 byte TestMuxSelect; // (8)
1138 byte unused2; // (9)
1139 byte Cntr01; // (0a) AuthResultSel, AuthDataSel
1140 //Cntr0 0-4 AuthResult
1141 //Cntr0 5-9 ACHKVal
1142 //Cntr0 Others UNDEFINED
1143 //Cntr1 0-15 AuthData [511:0]
1144 byte Cntr23; // (0b) AuthKeySel, DesDataSel
1145 //Cntr2 0-15 AuthKey [511:0]
1146 //Cntr3 0-1 DesInputData
1147 //Cntr3 2-3 K1 Data
1148 //Cntr3 4-5 K2 Data
1149 //Cntr3 6-7 K3 Data
1150 //Cntr3 8-9 IV Data
1151 //Cntr3 10-11 DesOutputData
1152 //Cntr3 Others UNDEFINED
1153 uint32 DesData; // (0c)
1154 uint32 AuthKey; // (10)
1155 uint32 AuthData; // (14)
1156 uint32 AuthResult; // (18)
1157 uint32 RxFifoData; // (1c)
1158 uint16 RxStatus; // (20)
1159 #define RXFIFOEMT 0x0004
1160 #define RXFIFOOVF 0x0002
1161 #define RXFIFODMARDY 0x0001
1162 uint16 RxDMAStatus; // (22)
1163 #define RXDMASOP 0x4000
1164 #define RXDMAEOP 0x2000
1165 #define RXDMADATAFLAG 0x1000
1166 #define RXDMABYTEENMSK 0x0f00
1167 #define ALLENABLE 0x0000
1168 #define ENABLE3 0x0100
1169 #define ENABLE2 0x0300
1170 #define ENABLE1 0x0700
1171 #define RXDMAFIFOOVFRST 0x0002
1172 #define RXDMAFIFOWR 0x0001
1173 uint32 TxFifoData; // (24)
1174 uint16 TxDMAStatus; // (28)
1175 #define TXDMAOWN 0x8000
1176 #define TXDMAEOP 0x0800
1177 #define TXDMASOP 0x0400
1178 #define TXAUTHFAIL 0x0100
1179 #define TXDMAPROCID 0x00ff
1180 uint16 TxDMACtl; // (2a)
1181 #define TXDMABYTELEN 0x1ff0 // Mask
1182 #define TXFIFOSTATPOP 0x0008
1183 #define TXFIFODMARDY 0x0004
1184 #define TXDMAFIFOEMT 0x0002
1185 #define TXDMAFIFORD 0x0001
1186 byte CtlMsgProcId; // (2c)
1187 byte CtlMsgStat; // (2d)
1188 #define CMENCODE 0x80
1189 #define CMAUTH 0x40
1190 #define CMENCRYPT 0x20
1191 #define CM3DES 0x10
1192 #define CMCBC 0x08
1193 #define CMHMAC 0x04
1194 #define CMMD5 0x02
1195 #define CMRETACV 0x01
1196 byte CtlStat; // (2e) 4'b0, CtlStat
1197 byte AuthDesStat; // (2f) AuthStat, DesStat
1198 uint16 DHLen; // (30)
1199 uint16 AHLen; // (32)
1200 uint16 DLen; // (34)
1201 uint16 ALen; // (36)
1202 uint16 DTLen; // (38)
1203 uint16 ATLen; // (3a)
1204 } SecmodRegisters;
1205
1206
1207
1208 /* Security Command Message Structures
1209 ** - must have SecCmdHdr to start
1210 ** - must have one SecCmdSpec, two if SEC_BOTH
1211 ** - can have one or more of the Key/IV/AuthKey/ChkVal specs
1212 ** - must have DATA_FLAG clear in descriptor
1213 **
1214 ** the following are valid command messages
1215 ** { SecCmdHdr:SEC_CRYPT, SecCmdSpec:SEC_CRYPT_SPEC, SecDesKey, SecDesIV }
1216 ** crypt only, key and iv specified
1217 **
1218 ** { SecCmdHdr:SEC_CRYPT, SecCmdSpec:SEC_CRYPT_SPEC }
1219 ** crypt only, key and iv not specified (use the last one)
1220 **
1221 ** { SecCmdHdr:SEC_AUTH, SecCmdSpec:SEC_AUTH_SPEC, SecAuthKey, SecAuthMD5ChkVal }
1222 ** authenticate, key and chkval specified
1223 **
1224 ** { SecCmdHdr:SEC_AUTH, SecCmdSpec:SEC_AUTH_SPEC }
1225 ** authenticate, no key and chkval specified
1226 **
1227 */
1228
1229 /* SecCmdHdr
1230 ** - always at the start of every command message
1231 ** - defines what else is included in the commad message
1232 */
1233 typedef struct SecCmdHdr {
1234 byte type; /* operation type */
1235 #define SEC_ENCODE 0
1236 #define SEC_DECODE 1
1237 byte process; /* what to do ... */
1238 #define SEC_CRYPT 0
1239 #define SEC_AUTH 1
1240 #define SEC_BOTH 2
1241 byte seqNum; /* sequence number */
1242 byte cmdLen; /* remaining length of command message */
1243 } SecCmdHdr;
1244
1245 /* SecCmdSpec
1246 ** - one per operation (auth, crypt)
1247 */
1248 typedef struct SecCmdSpec {
1249 byte type; /* which op this spec applies to */
1250 #define SEC_CRYPT_SPEC 4 /* .. encryption/decryption spec */
1251 #define SEC_AUTH_SPEC 5 /* .. authentication spec */
1252 byte mode; /* sub modes of op */
1253 #define SEC_DES_ECB 0x00
1254 #define SEC_DES_CBC 0x10
1255 #define SEC_3DES_ECB 0x40
1256 #define SEC_3DES_CBC 0x50
1257 #define SEC_HMAC_SHA 0x00
1258 #define SEC_HMAC_MD5 0x10
1259 #define SEC_DIGEST_SHA 0x40
1260 #define SEC_DIGEST_MD5 0x50
1261 uint16 hdrLen; /* # of bytes to skip at head of packet */
1262 uint16 encLen; /* # of bytes to process */
1263 uint16 trlLen; /* # of bytes to skip at tail of packet */
1264 } SecCmdSpec;
1265
1266
1267 /*
1268 ** Command Message Data Specifiers
1269 ** - there can be zero or more of these in each
1270 ** command message
1271 */
1272 typedef struct SecCmdDesKey {
1273 byte type;
1274 #define SEC_DES_KEY 8
1275 uint8 key[8];
1276 } SecCmdDesKey;
1277
1278 typedef struct SecCmd3DesKey {
1279 byte type; /* use SEC_DES_KEY */
1280 uint8 key[24];
1281 } SecCmd3DesKey;
1282
1283 typedef struct SecCmdDesIV {
1284 byte type;
1285 #define SEC_DES_IV 9
1286 uint8 iv[8];
1287 } SecCmdDesIV;
1288
1289 typedef struct SecCmd3DesIV {
1290 byte type; /* use SEC_DES_IV */
1291 uint8 iv[24];
1292 } SecCmd3DesIV;
1293
1294 typedef struct SecCmdAuthKey {
1295 byte type;
1296 #define SEC_AUTH_KEY 10
1297 uint8 key[64];
1298 } SecCmdAuthKey;
1299
1300 typedef struct SecCmdAuthSHAChkVal {
1301 byte type;
1302 #define SEC_AUTH_CHKVAL 11
1303 uint8 chkval[20];
1304 } SecCmdAuthSHAChkVal;
1305
1306 typedef struct SecCmdAuthMD5ChkVal {
1307 byte type; /* use SEC_DES_AUTH_CHKVAL */
1308 uint8 chkval[16];
1309 } SecCmdAuthMD5ChkVal;
1310
1311 /* max size for a security command */
1312 #define MaxSecCmdSize ( sizeof(SecCmdHdr)+ 2*sizeof(SecCmdSpec)+sizeof(SecCmd3DesKey)+sizeof(SecCmd3DesIV)+sizeof(SecCmdAuthKey)+sizeof(SecCmdAuthSHAChkVal))
1313
1314 #define READ32(addr) (*(volatile UINT32 *)((ULONG)&addr))
1315 #define READ16(addr) (*(volatile UINT16 *)((ULONG)&addr))
1316 #define READ8(addr) (*(volatile UINT8 *)((ULONG)&addr))
1317
1318 #if __cplusplus
1319 }
1320 #endif
1321
1322 #endif
Tomato firmware and modifications.