release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm9635x/include/6352_common.h

   1 /*
   2 <:copyright-broadcom
   3
   4  Copyright (c) 2002 Broadcom Corporation
   5  All Rights Reserved
   6  No portions of this material may be reproduced in any form without the
   7  written permission of:
   8           Broadcom Corporation
   9           16215 Alton Parkway
  10           Irvine, California 92619
  11  All information contained in this document is Broadcom Corporation
  12  company private, proprietary, and trade secret.
  13
  14 :>
  15 */
  16 /***********************************************************************/
  17 /*                                                                     */
  18 /*   MODULE: 6352_common.h                                             */
  19 /*   DATE:    96/12/19                                                 */
  20 /*   PURPOSE: Define addresses of major hardware components of         */
  21 /*            BCM6352                                                  */
  22 /*                                                                     */
  23 /***********************************************************************/
  24 #ifndef __BCM6352_MAP_COMMON_H
  25 #define __BCM6352_MAP_COMMON_H
  26
  27 #if __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 /* matches isb_decoder.v */
  32 #define INTC_BASE     0xfffe0000    /* interrupts controller registers */
  33 #define BB_BASE       0xfffe0100    /* bus bridge registers */
  34 #define TIMR_BASE     0xfffe0200    /* timer registers */
  35 #define UART_BASE     0xfffe0300    /* uart registers */
  36 #define GPIO_BASE     0xfffe0400    /* gpio registers */
  37 #define APM_BASE      0xfffe0a00    /* APM Registers */
  38 #define VPM_BASE      0xfffe0b00    /* VPM Registers */
  39 #define MTACTL_BASE   0xfffe0c00    /* APM/VPM/ORM Control Registers */
  40 #define ESWITCH_BASE  0xfffe1000    /* Ethernet switch registers */
  41 #define EBIC_BASE     0xfffe2000    /* EBI control registers */
  42 #define USB_BASE      0xfffe2100    /* USB controll registers */
  43 #define SEC_BASE      0xfffe2200    /* security module registers */
  44 #define SDRAM_BASE    0xfffe2300    /* SDRAM control registers */
  45 #define HDLC_BASE     0xfffe2400    /* HDLC registers */
  46 #define DMA_BASE      0xfffe2800    /* DMA control registers */
  47 #define ATM_BASE      0xfffe3000    /* ATM registers */
  48 #define DSP_BASE      0xfffe4000    /* DSP registers */
  49
  50 /* DMA channel assignments */
  51 #define EMAC_RX_CHAN            1
  52 #define EMAC_TX_CHAN            2
  53 #define DSP_RX_CHAN             3
  54 #define DSP_TX_CHAN             4
  55 #define EBI_RX_CHAN             5
  56 #define EBI_TX_CHAN             6
  57 #define HDLC_RX_CHAN            7
  58 #define HDLC_TX_CHAN            8
  59 #define RESERVED_RX_CHAN        9
  60 #define RESERVED_TX_CHAN        10
  61 #define SEC_RX_CHAN             11
  62 #define SEC_TX_CHAN             12
  63 #define USB_BULK_RX_CHAN        13
  64 #define USB_BULK_TX_CHAN        14
  65 #define USB_ISO_RX_CHAN         15
  66 #define USB_ISO_TX_CHAN         16
  67 #define USB_CNTL_RX_CHAN        17
  68 #define USB_CNTL_TX_CHAN        18
  69
  70 /*
  71 #-----------------------------------------------------------------------*
  72 #                                                                       *
  73 #************************************************************************
  74 */
  75 #define SDR_INIT_CTL        0x00
  76     /* Control Bits */
  77 #define SDR_9BIT_COL        (1<<11)
  78 #define SDR_32BIT           (1<<10)
  79 #define SDR_PWR_DN          (1<<9)
  80 #define SDR_SELF_REF        (1<<8)
  81 #define SDR_SOFT_RST        (1<<7)
  82 #define SDR_64x32           (3<<4)
  83 #define SDR_128MEG          (2<<4)
  84 #define SDR_64MEG           (1<<4)
  85 #define SDR_16MEG           (0<<4)
  86 #define SDR_ENABLE          (1<<3)
  87 #define SDR_MRS_CMD         (1<<2)
  88 #define SDR_PRE_CMD         (1<<1)
  89 #define SDR_CBR_CMD         (1<<0)
  90
  91 #define SDR_CFG_REG         0x04
  92     /* Control Bits */
  93 #define SDR_FULL_PG         0x00
  94 #define SDR_BURST8          0x01
  95 #define SDR_BURST4          0x02
  96 #define SDR_BURST2          0x03
  97 #define SDR_FAST_MEM        (1<<2)
  98 #define SDR_SLOW_MEM        0x00
  99
 100 #define SDR_REF_CTL         0x08
 101     /* Control Bits */
 102 #define SDR_REF_EN          (1<<15)
 103
 104 #define SDR_MEM_BASE        0x0c
 105     /*  Control Bits */
 106 #define DRAM2MBSPC          0x00000000
 107 #define DRAM8MBSPC          0x00000001
 108 #define DRAM16MBSPC         0x00000002
 109 #define DRAM32MBSPC         0x00000003
 110 #define DRAM64MBSPC         0x00000004
 111
 112 #define DRAM2MEG            0x00000000  /*  See SDRAM config */
 113 #define DRAM8MEG            0x00000001  /*  See SDRAM config */
 114 #define DRAM16MEG           0x00000002  /*  See SDRAM config */
 115 #define DRAM32MEG           0x00000003  /*  See SDRAM config */
 116 #define DRAM64MEG           0x00000004  /*  See SDRAM config */
 117
 118 /*
 119 #-----------------------------------------------------------------------*
 120 #                                                                       *
 121 #************************************************************************
 122 */
 123 #define CS0BASE         0x00
 124 #define CS0CNTL         0x04
 125 #define CS1BASE         0x08
 126 #define CS1CNTL         0x0c
 127 #define CS2BASE         0x10
 128 #define CS2CNTL         0x14
 129 #define CS3BASE         0x18
 130 #define CS3CNTL         0x1c
 131 #define CS4BASE         0x20
 132 #define CS4CNTL         0x24
 133 #define CS5BASE         0x28
 134 #define CS5CNTL         0x2c
 135 #define CS6BASE         0x30
 136 #define CS6CNTL         0x34
 137 #define CS7BASE         0x38
 138 #define CS7CNTL         0x3c
 139 #define EBICONFIG       0x40
 140
 141 /*
 142 # CSxBASE settings
 143 #   Size in low 4 bits
 144 #   Base Address for match in upper 24 bits
 145 */
 146 #define EBI_SIZE_8K         0
 147 #define EBI_SIZE_16K        1
 148 #define EBI_SIZE_32K        2
 149 #define EBI_SIZE_64K        3
 150 #define EBI_SIZE_128K       4
 151 #define EBI_SIZE_256K       5
 152 #define EBI_SIZE_512K       6
 153 #define EBI_SIZE_1M         7
 154 #define EBI_SIZE_2M         8
 155 #define EBI_SIZE_4M         9
 156 #define EBI_SIZE_8M         10
 157 #define EBI_SIZE_16M        11
 158 #define EBI_SIZE_32M        12
 159 #define EBI_SIZE_64M        13
 160 #define EBI_SIZE_128M       14
 161 #define EBI_SIZE_256M       15
 162
 163 /* CSxCNTL settings */
 164 #define EBI_ENABLE          0x00000001  /* .. enable this range */
 165 #define EBI_WAIT_STATES     0x0000000e  /* .. mask for wait states */
 166 #define ZEROWT              0x00000000  /* ..  0 WS */
 167 #define ONEWT               0x00000002  /* ..  1 WS */
 168 #define TWOWT               0x00000004  /* ..  2 WS */
 169 #define THREEWT             0x00000006  /* ..  3 WS */
 170 #define FOURWT              0x00000008  /* ..  4 WS */
 171 #define FIVEWT              0x0000000a  /* ..  5 WS */
 172 #define SIXWT               0x0000000c  /* ..  6 WS */
 173 #define SEVENWT             0x0000000e  /* ..  7 WS */
 174 #define EBI_WORD_WIDE       0x00000010  /* .. 16-bit peripheral, else 8 */
 175 #define EBI_POLARITY        0x00000040  /* .. set to invert chip select polarity */
 176 #define EBI_TS_TA_MODE      0x00000080  /* .. use TS/TA mode */
 177 #define EBI_TS_SEL          0x00000100  /* .. drive tsize, not bs_b */
 178 #define EBI_FIFO            0x00000200  /* .. enable fifo */
 179 #define EBI_RE              0x00000400  /* .. Reverse Endian */
 180
 181 /* EBICONFIG settings */
 182 #define EBI_MASTER_ENABLE   0x80000000  /* allow external masters */
 183 #define EBI_EXT_MAST_PRIO   0x40000000  /* maximize ext master priority */
 184 #define EBI_CTRL_ENABLE     0x20000000
 185 #define EBI_TA_ENABLE       0x10000000
 186
 187 #define BRGEN            0x80   /* Control register bit defs */
 188 #define TXEN             0x40
 189 #define RXEN             0x20
 190 #define LOOPBK           0x10
 191 #define TXPARITYEN       0x08
 192 #define TXPARITYEVEN     0x04
 193 #define RXPARITYEN       0x02
 194 #define RXPARITYEVEN     0x01
 195 #define XMITBREAK        0x40
 196 #define BITS5SYM         0x00
 197 #define BITS6SYM         0x10
 198 #define BITS7SYM         0x20
 199 #define BITS8SYM         0x30
 200 #define BAUD115200       0x0a
 201 #define ONESTOP          0x07
 202 #define TWOSTOP          0x0f
 203 #define TX4              0x40
 204 #define RX4              0x04
 205 #define RSTTXFIFOS       0x80
 206 #define RSTRXFIFOS       0x40
 207 #define DELTAIP          0x0001
 208 #define TXUNDERR         0x0002
 209 #define TXOVFERR         0x0004
 210 #define TXFIFOTHOLD      0x0008
 211 #define TXREADLATCH      0x0010
 212 #define TXFIFOEMT        0x0020
 213 #define RXUNDERR         0x0040
 214 #define RXOVFERR         0x0080
 215 #define RXTIMEOUT        0x0100
 216 #define RXFIFOFULL       0x0200
 217 #define RXFIFOTHOLD      0x0400
 218 #define RXFIFONE         0x0800
 219 #define RXFRAMERR        0x1000
 220 #define RXPARERR         0x2000
 221 #define RXBRK            0x4000
 222
 223 #define RXIRQS           0x7fc0
 224 #define TXIRQS           0x003e
 225
 226 #define CPU_CLK_EN       0x0001
 227 #define UART_CLK_EN      0x0008
 228
 229 #define BLKEN            06
 230 #define FMSEL            0x08
 231
 232 #define UART0CONTROL     0x01
 233 #define UART0CONFIG      0x02
 234 #define UART0RXTIMEOUT   0x03
 235 #define UART0BAUD        0x04
 236 #define UART0FIFOCFG     0x0a
 237 #define UART0INTMASK     0x10
 238 #define UART0INTSTAT     0x12
 239 #define UART0DATA        0x17
 240
 241 #define GPIOTBUSSEL      0x03
 242 #define GPIODIR          0x06
 243 #define GPIOLED          0x09
 244 #define GPIOIO           0x0a
 245 #define GPIOUARTCTL      0x0c
 246
 247 /*Defines below show which bit enables which UART signals */
 248 #define RI1_EN          0x0001
 249 #define CTS1_EN         0x0002
 250 #define DCD1_EN         0x0004
 251 #define DSR1_EN         0x0008
 252 #define DTR1_EN         0x0010
 253 #define RTS1_EN         0x0020
 254 #define DO1_EN          0x0040
 255 #define DI1_EN          0x0080
 256 #define RI0_EN          0x0100
 257 #define CTS0_EN         0x0200
 258 #define DCD0_EN         0x0400
 259 #define DSR0_EN         0x0800
 260 #define DTR0_EN         0x1000
 261 #define RTS0_EN         0x2000
 262
 263 #if __cplusplus
 264 }
 265 #endif
 266
 267 #endif