release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm96345/src/bcm6345_init.S

   1 #include "sbmips.h"
   2 #include "bsp_config.h"
   3
   4 #include "6345_cpu.h"
   5 #include "6345_common.h"
   6 #include "board.h"
   7
   8 /*
   9 #************************************************************************
  10 #*     InitEbi: Initializes the EBI for proper chip-select operation    *
  11 #*                                                                      *
  12 #*      SYNTAX: void  InitEbi(void);                                    *
  13 #*     RETURNS:                                                         *
  14 #*                                                                      *
  15 #*     Configuration                                                    *
  16 #*       CS[0] - Flash        @ 1fc0_0000 BASE_ADDR must already be set *
  17 #*                                      because we have boot from flash *
  18 #*       CS[1] - Unused                                                 *
  19 #*       CS[2] - ITeX ADSL    @ PHYS_ITEX_BASE                          *
  20 #*       CS[3] - Unused                                                 *
  21 #*       CS[4] - BCM42xx      @ PHYS_BCM42xx_BASE                       *
  22 #*       CS[5] - Unused                                                 *
  23 #*       CS[6] - Unused                                                 *
  24 #*       CS[7] - Unused                                                 *
  25 #*                                                                      *
  26 #************************************************************************
  27 */
  28
  29 /*  *********************************************************************
  30     *  BOARD_EARLYINIT()
  31     *
  32     *  Initialize board registers.  This is the earliest
  33     *  time the BSP gets control.  This routine cannot assume that
  34     *  memory is operational, and therefore all code in this routine
  35     *  must run from registers only.  The $ra register must not
  36     *  be modified, as it contains the return address.
  37     *
  38     *  This routine will be called from uncached space, before
  39     *  the caches are initialized.  If you want to make
  40     *  subroutine calls from here, you must use the CALLKSEG1 macro.
  41     *
  42     *  Among other things, this is where the GPIO registers get
  43     *  programmed to make on-board LEDs function, or other startup
  44     *  that has to be done before anything will work.
  45     *
  46     *  Input parameters:
  47     *      nothing
  48     *
  49     *  Return value:
  50     *      nothing
  51     ********************************************************************* */
  52
  53 LEAF(board_earlyinit)
  54
  55         .set    noreorder
  56         mtc0    zero,C0_SR
  57         li      v0,1<<22                                # seanl: Why? SR_BEV
  58         mtc0    v0,C0_SR                # state unknown on reset
  59         mtc0    zero,C0_CAUSE           # clear software interrupts
  60         nop                             # paranoia
  61         .set    reorder
  62
  63         /**--------------------------------------------------------------**/
  64         /** platform specific code                                       **/
  65         /**--------------------------------------------------------------**/
  66
  67         .set    noreorder
  68         /**----- Disable Caches -----------------------------------------**/
  69         mfc0    t1, BCM6345_CONFIG
  70         nop
  71         and     t1, t1, ~(CP0_CFG_ICSHEN|CP0_CFG_DCSHEN)
  72         mtc0    t1, BCM6345_CONFIG      # disable I&D Caches
  73         .set    reorder
  74
  75         /**----- Initialize EBI -----------------------------------------**/
  76         li      t1,EBIC_BASE
  77         li      t2,PHYS_FLASH_BASE|EBI_SIZE_8M
  78         sw      t2,CS0BASE(t1)        # CS[0] Base
  79         li      t2,THREEWT|EBI_WORD_WIDE|EBI_ENABLE
  80         sw      t2,CS0CNTL(t1)        # CS[0] Control
  81
  82         /*
  83         # Supposedly, this enables the master WR_POST for the EBI, as well as
  84         # setting something else.  However, with A3 silicon, it seems that we
  85         # need to set the individual WR_POST bits for each CS#CNTL in order for
  86         # it to work.  It isn't clear whether or not the master enable is needed
  87         # for A3.
  88         #
  89         # We believe that this used to work for the A2, but perhaps that change
  90         # didn't get rolled in to A3?
  91         */
  92 1:
  93         li      t2,0x00000400
  94         sw      t2,EBICONFIG(t1)
  95
  96                 /**--- End of InitEbi -------------------------------------------**/
  97
  98         /**----- Initialize MIPS Clock ----------------------------------**/
  99                 li              t0, INTC_BASE           # The address of the PLL register
 100         lw              t1, FMSEL(t0)
 101         and             t1, ~FMDIV_MASK
 102         sw              t1, FMSEL(t0)           # Set Mips Clock
 103         nop
 104
 105 END(board_earlyinit)
 106
 107
 108 /*  *********************************************************************
 109     *  BOARD_DRAMINFO
 110     *
 111     *  Return the address of the DRAM information table
 112     *
 113     *  Input parameters:
 114     *      nothing
 115     *
 116     *  Return value:
 117     *      v0 - DRAM info table, return 0 to use default table
 118     ********************************************************************* */
 119
 120
 121 LEAF(board_draminfo)
 122
 123                 j       ra
 124
 125 END(board_draminfo)
 126
 127
 128 /*  *********************************************************************
 129     *  BOARD_DRAMINIT
 130     *
 131     *  This routine should activate memory.
 132     *
 133     *  Input parameters:
 134     *      a0 - points to configuration table returned by board_draminfo
 135     *           or 0 to use an automatic table
 136     *
 137     *  Return value:
 138     *      v0 - total memory installed
 139     *
 140     *  Registers used:
 141     *      can use all registers.
 142     ********************************************************************* */
 143
 144 LEAF(board_draminit)
 145
 146 /*
 147 #************************************************************************
 148 #* RC32364
 149 #*     InitSdram: Initializes the Sdram for proper operation            *
 150 #*                                                                      *
 151 #*      SYNTAX: void  InitSdram(void);                                  *
 152 #*     RETURNS:                                                         *
 153 #*  Note:  We must be running UnCached before executing this routine    *
 154 #*         for delay purposes                                           *
 155 #************************************************************************
 156 */
 157 InitSdram:
 158         .set    noreorder
 159
 160                 /* check memory config type 64MB, 32MB, 16MB and default to 8MB */
 161         li      t1,SDRAM_BASE
 162                 li              t0,BOARD_SDRAM_TYPE_ADDRESS
 163                 lw              t0,0(t0)
 164
 165                 /* setting for 64MB, 2 chip */
 166                 li      t3,SDR_ENABLE|SDR_MRS_CMD|SDR_64MEG     |SDR_128MEG                     /* 0x0000003C */
 167         li      t2,PHYS_DRAM_BASE|DRAM64MBSPC                                                   /* 64mg */
 168                 li              v0,64
 169                 li              t4,MEMORY_64MB_2_CHIP
 170                 beq             t0,t4,1f
 171                 nop
 172
 173                 /* setting for 32MB, 1 chip */
 174                 li      t3,SDR_ENABLE|SDR_MRS_CMD|SDR_128MEG                                    /* 0x0000002C */
 175         li      t2,PHYS_DRAM_BASE|DRAM32MBSPC                                                   /* 32mg */
 176                 li              v0,32
 177                 li              t4,MEMORY_32MB_1_CHIP
 178                 beq             t0,t4,1f
 179                 nop
 180
 181                 /* setting for 16MB, 1 chip */
 182                 li      t3,SDR_ENABLE|SDR_MRS_CMD|SDR_128MEG|SDR_9BIT_COL               /* 0x0000082C */
 183         li      t2,PHYS_DRAM_BASE|DRAM16MBSPC                                                   /* 16mg */
 184                 li              v0,16
 185                 li              t4,MEMORY_16MB_1_CHIP
 186                 beq             t0,t4,1f
 187                 nop
 188
 189         /* Default SDRAM settings for BCM6345 board (8MB, 1 chip) */
 190         li      t3,SDR_ENABLE|SDR_MRS_CMD|SDR_64MEG                                             /* 0x0000001c */
 191         li      t2,PHYS_DRAM_BASE|DRAM8MBSPC                                                    /* 8mg */
 192         li              v0,8
 193
 194 1:
 195         sw      t2,SDR_MEM_BASE(t1)   # Set Memory Base address and size
 196         li      t2,SDR_FULL_PG|SDR_FAST_MEM
 197         sw      t2,SDR_CFG_REG(t1)    # Full page burst, slow memory
 198         li      t2,SDR_ENABLE|SDR_PRE_CMD
 199         sw      t2,SDR_INIT_CTL(t1)   # Pre-charge powerup sequence
 200         li      t2,SDR_ENABLE|SDR_CBR_CMD
 201         sw      t2,SDR_INIT_CTL(t1)   # 8 or more auto-refresh cmds
 202         sw      t2,SDR_INIT_CTL(t1)
 203         sw      t2,SDR_INIT_CTL(t1)
 204         sw      t2,SDR_INIT_CTL(t1)
 205         sw      t2,SDR_INIT_CTL(t1)
 206         sw      t2,SDR_INIT_CTL(t1)
 207         sw      t2,SDR_INIT_CTL(t1)
 208         sw      t2,SDR_INIT_CTL(t1)
 209         sw      t3,SDR_INIT_CTL(t1)   # Mode Register set,
 210         li      t2,SDR_REF_EN|0x40
 211         sw      t2,SDR_REF_CTL(t1)    # Refresh period 0x40, Enable
 212
 213         j       ra
 214         nop
 215         .set    reorder
 216 END(board_draminit)
 217
 218
 219 /*  *********************************************************************
 220     *  BOARD_SETLEDS(x)
 221     *
 222     *  Set LEDs for boot-time progress indication.  Not used if
 223     *  the board does not have progress LEDs.  This routine
 224     *  must not call any other routines, since it may be invoked
 225     *  either from KSEG0 or KSEG1 and it may be invoked
 226     *  whether or not the icache is operational.
 227     *
 228     *  Input parameters:
 229     *      a0 - LED value (8 bits per character, 4 characters)
 230     *
 231     *  Return value:
 232     *      nothing
 233     *
 234     *  Registers used:
 235     *      t0,t1,t2,t3
 236     ********************************************************************* */
 237
 238
 239 LEAF(board_setleds)
 240
 241                 j       ra
 242
 243 END(board_setleds)