release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm96345/include/6345_cpu.h

   1 /*
   2 #************************************************************************
   3 #* Coprocessor 0 Register Names
   4 #************************************************************************
   5 */
   6 #define BCM6345_INDEX           $0
   7 #define BCM6345_ENTRY           $2
   8 #define BCM6345_BVADDR          $8
   9 #define BCM6345_COUNT           $9
  10 #define BCM6345_COMPARE         $11
  11 #define BCM6345_STATUS          $12
  12 #define BCM6345_CAUSE           $13
  13 #define BCM6345_EPC             $14
  14 #define BCM6345_PRID            $15
  15 #define BCM6345_PROCCFG         $16
  16 #define BCM6345_CONFIG          $22
  17 #define BCM6345_DEBUG           $23
  18 #define BCM6345_DBEXCPC         $24
  19 #define BCM6345_DESAVE          $31
  20
  21 #define BRCM_CONFIG             $22
  22
  23 /*
  24 #************************************************************************
  25 #* Coprocessor 0 Index Register Bits
  26 #************************************************************************
  27 # No known functionality (32-bit register)
  28 */
  29
  30 /*
  31 #************************************************************************
  32 #* Coprocessor 0 Entry Register Bits
  33 #************************************************************************
  34 # No known functionality (32-bit register)
  35 */
  36
  37 /*
  38 #************************************************************************
  39 #* Coprocessor 0 BvAddr Register Bits
  40 #************************************************************************
  41 # Contains offending address (32-bit register)
  42 */
  43
  44 /*
  45 #************************************************************************
  46 #* Coprocessor 0 Status Register Bits
  47 #************************************************************************
  48
  49 # Notes: COP2 is forced, then allowed to be overwritten
  50 #               writing a '1' to bit 20 force bit 20 to '0' but no effect
  51 */
  52 #define CP0SR_COP3              (1<<31)
  53 #define CP0SR_COP2              (1<<30)
  54 #define CP0SR_COP1              (1<<29)
  55 #define CP0SR_COP0              (1<<28)
  56 #define CP0SR_IST               (1<<23)
  57 #define CP0SR_BEV               (1<<22)
  58 #define CP0SR_SWC               (1<<17)
  59 #define CP0SR_ISC               (1<<16)
  60 #define CP0SR_KRNL              (1<<1)
  61 #define CP0SR_IE                (1<<0)
  62 #define CP0SR_IM5               (1<<15)
  63 #define CP0SR_IM4               (1<<14)
  64 #define CP0SR_IM3               (1<<13)
  65 #define CP0SR_IM2               (1<<12)
  66 #define CP0SR_IM1               (1<<11)
  67 #define CP0SR_IM0               (1<<10)
  68 #define CP0SR_SWM1              (1<<9)
  69 #define CP0SR_SWM0              (1<<8)
  70
  71 /*
  72 #************************************************************************
  73 #* Coprocessor 0 Cause Register Bits
  74 #************************************************************************
  75 # Notes: 5:2 hold exception cause
  76 # Notes: 29:28 hold Co-processor Number reference by Coproc unusable excptn
  77 # Notes: 7:6, 1:0, 27:15, 30 ***UNUSED***
  78 */
  79 #define CP0CR_BD                        (1<<31)
  80 #define CP0CR_EXTIRQ4                   (1<<14)
  81 #define CP0CR_EXTIRQ3                   (1<<13)
  82 #define CP0CR_EXTIRQ2                   (1<<12)
  83 #define CP0CR_EXTIRQ1                   (1<<11)
  84 #define CP0CR_EXTIRQ0                   (1<<10)
  85 #define CP0CR_SW1                       (1<<9)
  86 #define CP0CR_SW0                       (1<<8)
  87 #define CP0CR_EXC_CAUSE_MASK            (0xf << 2)
  88 #define CP0CR_EXC_COP_MASK              (0x3 << 28)
  89
  90 /*
  91 #************************************************************************
  92 #* Coprocessor 0 EPC Register Bits
  93 #************************************************************************
  94 # Contains PC or PC-4 for resuming program after exception (32-bit register)
  95 */
  96
  97 /*
  98 #************************************************************************
  99 #* Coprocessor 0 PrID Register Bits
 100 #************************************************************************
 101 # Notes: Company Options=0
 102 #        Company ID=0
 103 #        Processor ID = 0xa
 104 #        Revision = 0xa
 105 */
 106
 107 /*
 108 #************************************************************************
 109 #* Coprocessor 0 Debug Register Bits
 110 #************************************************************************
 111 # Notes: Bits [29:13],[11], [9], [6] read as zero
 112 */
 113 #define CP0_DBG_BRDLY           (0x1 << 31)
 114 #define CP0_DBG_DBGMD           (0x1 << 30)
 115 #define CP0_DBG_EXSTAT          (0x1 << 12)
 116 #define CP0_DBG_BUS_ERR         (0x1 << 10)
 117 #define CP0_DBG_1STEP           (0x1 << 8)
 118 #define CP0_DBG_JTGRST          (0x1 << 7)
 119 #define CP0_DBG_PBUSBRK         (0x1 << 5)
 120 #define CP0_DBG_IADBRK          (0x1 << 4)
 121 #define CP0_DBG_DABRKST         (0x1 << 3)
 122 #define CP0_DBG_DABRKLD         (0x1 << 2)
 123 #define CP0_DBG_SDBBPEX         (0x1 << 1)
 124 #define CP0_DBG_SSEX            (0x1 << 0)
 125
 126 /*
 127 #************************************************************************
 128 #* Coprocessor 0 DBEXCPC Register Bits
 129 #************************************************************************
 130 # Debug Exception Program Counter (32-bits)
 131 */
 132
 133 /*
 134 #************************************************************************
 135 #* Coprocessor 0 PROCCFG Register Bits
 136 #************************************************************************
 137 # Select 0
 138 */
 139 #define CP0_CFG1EN              (0x1 << 31)
 140 #define CP0_BE                  (0x1 << 15)
 141 #define CP0_MIPS32MSK           (0x3 << 13) /* 0 = MIPS32 Arch */
 142 #define CP0_ARMSK               (0x7 << 10) /* Architecture Rev 0 */
 143 #define CP0_MMUMSK              (0x7 << 7)  /* 0 no MMU */
 144
 145 #define CP0_K0Coherency         (0x7 << 0)  /* 0 no Coherency */
 146 #define CP0_K0WriteThrough      (0x1 << 0)  /* 1 = Cached, Dcache write thru */
 147 #define CP0_K0Uncached          (0x2 << 0)  /* 2 = Uncached */
 148 #define CP0_K0Writeback         (0x3 << 0)  /* 3 = Cached, Dcache write back */
 149
 150 /*
 151 # Select 1
 152 #  Bit  31:   unused
 153 #  Bits 30:25 MMU Size (Num TLB entries-1)
 154 #  Bits 24:22 ICache sets/way (2^n * 64)
 155 #  Bits 21:19 ICache Line size (2^(n+1) bytes) 0=No Icache
 156 #  Bits 18:16 ICache Associativity (n+1) way
 157 #  Bits 15:13 DCache sets/way (2^n * 64)
 158 #  Bits 12:10 DCache Line size (2^(n+1) bytes) 0=No Dcache
 159 #  Bits 9:7   DCache Associativity (n+1) way
 160 #  Bits 6:4   unused
 161 #  Bit  3:    1=At least 1 watch register
 162 #  Bit  2:    1=MIPS16 code compression implemented
 163 #  Bit  1:    1=EJTAG implemented
 164 #  Bit  0:    1=FPU implemented
 165 */
 166 #define CP0_CFG_ISMSK      (0x7 << 22)
 167 #define CP0_CFG_ISSHF      22
 168 #define CP0_CFG_ILMSK      (0x7 << 19)
 169 #define CP0_CFG_ILSHF      19
 170 #define CP0_CFG_IAMSK      (0x7 << 16)
 171 #define CP0_CFG_IASHF      16
 172 #define CP0_CFG_DSMSK      (0x7 << 13)
 173 #define CP0_CFG_DSSHF      13
 174 #define CP0_CFG_DLMSK      (0x7 << 10)
 175 #define CP0_CFG_DLSHF      10
 176 #define CP0_CFG_DAMSK      (0x7 << 7)
 177 #define CP0_CFG_DASHF      7
 178
 179 /*
 180 #************************************************************************
 181 #* Coprocessor 0 Config Register Bits
 182 #************************************************************************
 183 */
 184 #define CP0_CFG_ICSHEN         (0x1 << 31)
 185 #define CP0_CFG_DCSHEN         (0x1 << 30)
 186 #define CP0_CFG_FMEN           (0x1 << 29)
 187
 188 /*
 189 #************************************************************************
 190 #* Coprocessor 0 DeSave Register Bits
 191 #************************************************************************
 192 # Note: No apparent functionality 32-b R/W
 193 */