release/src-rt-6.x.4708/cfe/cfe/arch/mips/board/bcm91120c/src/bcm91120c_init.S

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  Board-specific initialization            File: BCM91120C_INIT.S
   5     *
   6     *  This module contains the assembly-language part of the init
   7     *  code for this board support package.  The routine
   8     *  "board_earlyinit" lives here.
   9     *
  10     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  11     *
  12     *********************************************************************
  13     *
  14     *  Copyright 2000,2001,2002,2003
  15     *  Broadcom Corporation. All rights reserved.
  16     *
  17     *  This software is furnished under license and may be used and
  18     *  copied only in accordance with the following terms and
  19     *  conditions.  Subject to these conditions, you may download,
  20     *  copy, install, use, modify and distribute modified or unmodified
  21     *  copies of this software in source and/or binary form.  No title
  22     *  or ownership is transferred hereby.
  23     *
  24     *  1) Any source code used, modified or distributed must reproduce
  25     *     and retain this copyright notice and list of conditions
  26     *     as they appear in the source file.
  27     *
  28     *  2) No right is granted to use any trade name, trademark, or
  29     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  30     *     name may not be used to endorse or promote products derived
  31     *     from this software without the prior written permission of
  32     *     Broadcom Corporation.
  33     *
  34     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  35     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  36     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  37     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  38     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  39     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  40     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  41     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  42     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  43     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  44     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  45     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  46     *     THE POSSIBILITY OF SUCH DAMAGE.
  47     ********************************************************************* */
  48
  49
  50 #include "sbmips.h"
  51 #include "sb1250_genbus.h"
  52 #include "sb1250_regs.h"
  53 #include "sb1250_scd.h"
  54 #include "sb1250_mc.h"
  55 #include "sb1250_mac.h"
  56 #include "bsp_config.h"
  57 #include "bcm91120c.h"
  58 #include "mipsmacros.h"
  59 #include "sb1250_draminit.h"
  60
  61                 .text
  62
  63 #if defined(_BCM91120C_DIAG_CFG_)
  64 #define _SERIAL_PORT_LEDS_
  65 #endif
  66
  67 /*  *********************************************************************
  68     *  Macros
  69     ********************************************************************* */
  70
  71 #ifdef _SERIAL_PORT_LEDS_
  72 #define BOARD_PROMICE_BASE      (0x1FDFFC00)
  73 #define BOARD_PROMICE_ZERO      (0)
  74 #define BOARD_PROMICE_ONE       (1)
  75 #define BOARD_PROMICE_DATA      (2)
  76 #define BOARD_PROMICE_STATUS    (3)
  77
  78 #define TDA 0x01        /* Target data available */
  79 #define HDA 0x02        /* Host data available */
  80 #define OVR 0x04        /* Host data overflow */
  81 #endif
  82
  83
  84 /*  *********************************************************************
  85     *  BOARD_EARLYINIT()
  86     *
  87     *  Initialize board registers.  This is the earliest
  88     *  time the BSP gets control.  This routine cannot assume that
  89     *  memory is operational, and therefore all code in this routine
  90     *  must run from registers only.  The $ra register must not
  91     *  be modified, as it contains the return address.
  92     *
  93     *  This routine will be called from uncached space, before
  94     *  the caches are initialized.  If you want to make
  95     *  subroutine calls from here, you must use the CALLKSEG1 macro.
  96     *
  97     *  Among other things, this is where the GPIO registers get
  98     *  programmed to make on-board LEDs function, or other startup
  99     *  that has to be done before anything will work.
 100     *
 101     *  Input parameters:
 102     *      nothing
 103     *
 104     *  Return value:
 105     *      nothing
 106     ********************************************************************* */
 107
 108 LEAF(board_earlyinit)
 109
 110        #
 111        # Configure the GPIOs
 112        #
 113
 114                 li      t0,PHYS_TO_K1(A_GPIO_DIRECTION)
 115                 li      t1,GPIO_OUTPUT_MASK
 116                 sd      t1,0(t0)
 117
 118                 li      t0,PHYS_TO_K1(A_GPIO_INT_TYPE)
 119                 li      t1,GPIO_INTERRUPT_MASK
 120                 sd      t1,0(t0)
 121
 122        #
 123        # Set both loopback pins to "disable"
 124        #
 125                 li      t0,PHYS_TO_K1(A_GPIO_PIN_CLR)
 126                 li      t1,M_GPIO_SERIAL0_LOOPBACK | M_GPIO_SERIAL1_LOOPBACK
 127                 sd      t1,0(t0)
 128
 129
 130        #
 131        # Configure the LEDs
 132        #
 133
 134                 li      t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(LEDS_CS))
 135                 li      t1,LEDS_PHYS >> S_IO_ADDRBASE
 136                 sd      t1,R_IO_EXT_START_ADDR(t0)
 137
 138                 li      t1,LEDS_SIZE-1  /* Needs to be 1 smaller, se UM for details */
 139                 sd      t1,R_IO_EXT_MULT_SIZE(t0)
 140
 141                 li      t1,LEDS_TIMING0
 142                 sd      t1,R_IO_EXT_TIME_CFG0(t0)
 143
 144                 li      t1,LEDS_TIMING1
 145                 sd      t1,R_IO_EXT_TIME_CFG1(t0)
 146
 147                 li      t1,LEDS_CONFIG
 148                 sd      t1,R_IO_EXT_CFG(t0)
 149
 150
 151
 152        #
 153        # Configure the alternate boot ROM
 154        #
 155
 156                 li      t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(ALT_BOOTROM_CS))
 157
 158                 li      t1,ALT_BOOTROM_PHYS >> S_IO_ADDRBASE
 159                 sd      t1,R_IO_EXT_START_ADDR(t0)
 160
 161                 li      t1,ALT_BOOTROM_SIZE-1
 162                 sd      t1,R_IO_EXT_MULT_SIZE(t0)
 163
 164                 li      t1,ALT_BOOTROM_TIMING0
 165                 sd      t1,R_IO_EXT_TIME_CFG0(t0)
 166
 167                 li      t1,ALT_BOOTROM_TIMING1
 168                 sd      t1,R_IO_EXT_TIME_CFG1(t0)
 169
 170                 li      t1,ALT_BOOTROM_CONFIG
 171                 sd      t1,R_IO_EXT_CFG(t0)
 172
 173
 174
 175
 176        #
 177        # Configure the Big Flash
 178        #
 179
 180                 li      t0,PHYS_TO_K1(A_IO_EXT_CS_BASE(BIG_FLASH_CS))
 181
 182                 li      t1,BIG_FLASH_PHYS >> S_IO_ADDRBASE
 183                 sd      t1,R_IO_EXT_START_ADDR(t0)
 184
 185                 li      t1,BIG_FLASH_SIZE-1
 186                 sd      t1,R_IO_EXT_MULT_SIZE(t0)
 187
 188                 li      t1,BIG_FLASH_TIMING0
 189                 sd      t1,R_IO_EXT_TIME_CFG0(t0)
 190
 191                 li      t1,BIG_FLASH_TIMING1
 192                 sd      t1,R_IO_EXT_TIME_CFG1(t0)
 193
 194                 li      t1,BIG_FLASH_CONFIG
 195                 sd      t1,R_IO_EXT_CFG(t0)
 196
 197         /*
 198          * If the CPU is a 1250 or hybrid, certain initialization has
 199          * to be done so that the chip can be used like an 112x.
 200          */
 201
 202         /* First, figure out what type of SOC we're on. */
 203         ld      t1, PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
 204         SYS_SOC_TYPE(t3, t1)
 205         bne     t3, K_SYS_SOC_TYPE_BCM1250, is_bcm112x
 206
 207         /*
 208          * We have a 1250 or hybrid.  Initialize registers as appropriate.
 209          */
 210
 211         /*
 212          * If we're not already running as a uniprocessor, get us there.
 213          */
 214         dsrl    t1, t1, S_SYS_PART      # part number now in t1
 215         and     t3, t1, 0xf00
 216         dsrl    t3, t3, 8               # t3 = numcpus
 217
 218         ld      t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG)
 219         or      t4, t4, M_SYS_SB_SOFTRES
 220         xor     t4, t4, M_SYS_SB_SOFTRES
 221         sd      t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG)        /* clear soft reset */
 222
 223         beq     t3, 1, 2f
 224
 225         or      t4, t4, M_SYS_SB_SOFTRES | M_SYS_UNICPU0
 226         sd      t4, PHYS_TO_K1(A_SCD_SYSTEM_CFG)        /* go unicpu */
 227         sync
 228 1:
 229         b       1b
 230 2:
 231
 232         /*
 233          * Clean up MC 0.
 234          */
 235
 236         li      t0, PHYS_TO_K1(A_MC_BASE_0)
 237         dli     t1, V_MC_CONFIG_DEFAULT | M_MC_ECC_DISABLE | \
 238                     V_MC_CS_MODE_MSB_CS
 239         sd      t1, R_MC_CONFIG(t0)
 240         sd      zero, R_MC_CS_START(t0)
 241         sd      zero, R_MC_CS_END(t0)
 242         sd      zero, R_MC_CS_INTERLEAVE(t0)
 243         sd      zero, R_MC_CS_ATTR(t0)
 244         sd      zero, R_MC_TEST_DATA(t0)
 245         sd      zero, R_MC_TEST_ECC(t0)
 246
 247         /*
 248          * Zero out MAC 2's address register.  (This has
 249          * undefined value after reset, but OSes may check
 250          * it on some parts to see if they should init
 251          * the interface.  This is a convenient place
 252          * to zero it.)
 253          */
 254
 255         li      t0, PHYS_TO_K1(A_MAC_BASE_2)
 256         sd      zero, R_MAC_ETHERNET_ADDR(t0)
 257
 258 is_bcm112x:
 259
 260         j       ra
 261
 262 END(board_earlyinit)
 263
 264
 265 /*  *********************************************************************
 266     *  BOARD_DRAMINFO
 267     *
 268     *  Return the address of the DRAM information table
 269     *
 270     *  Input parameters:
 271     *      nothing
 272     *
 273     *  Return value:
 274     *      v0 - DRAM info table, return 0 to use default table
 275     ********************************************************************* */
 276
 277 #define BOARD_CONFIG_STAKTEK     0
 278 #define BOARD_CONFIG_NONSTAKTEK  1
 279 #define BOARD_CONFIG_TBD1        2
 280 #define BOARD_CONFIG_TBD2        3
 281
 282
 283 LEAF(board_draminfo)
 284
 285                 move    t0,ra
 286
 287                 /* First, figure out what type of SOC we're on. */
 288                 ld      t3, PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
 289                 SYS_SOC_TYPE(t3, t3)
 290
 291                 /* t3 now contains "SOC type."  */
 292
 293         /*
 294          * Read the config bits to decide if we have staktek rams or not
 295          */
 296
 297                 li      t1,PHYS_TO_K1(A_SCD_SYSTEM_CFG)
 298                 ld      t1,0(t1)                /* read system config register */
 299                 dsrl    t1,S_SYS_CONFIG         /* move config bits to bottom */
 300                 and     t1,3                    /* isolate bottom 2 bits */
 301                 /* t1 now contains board config, t3 still has SOC type.  */
 302
 303                 /*
 304                  * Pick from different init tables, depending on whether
 305                  * the chip is a hybrid.
 306                  */
 307
 308                 /*
 309                  * If not a bcm1250, must be real 112x (w/pass3 SOC features).
 310                  */
 311                 bne     t3, K_SYS_SOC_TYPE_BCM1250, bcm1120y_pass2_or_later_draminit
 312
 313                 /* If 1250 (hybrid), need to check rev.  */
 314                 li      t3, PHYS_TO_K1(A_SCD_SYSTEM_REVISION)
 315                 ld      t3, 0(t3)               /* read system rev register */
 316                 and     t3, M_SYS_REVISION      /* mask off all but rev */
 317                 dsrl    t3, S_SYS_REVISION      /* move rev bits to bottom */
 318
 319                 /* Less than starting pass2 revision -> pass1 hybrid.  */
 320                 blt     t3, K_SYS_REVISION_PASS2, bcm1120y_pass1_draminit
 321
 322         /*
 323          * Pick the table for Pass2 BCM1120Y parts, or real BCM1120 parts.
 324          */
 325 bcm1120y_pass2_or_later_draminit:
 326                 beq     t1, BOARD_CONFIG_NONSTAKTEK, non_staktek
 327
 328                 LOADREL(v0,staktek_drams)
 329                 b       draminfo_done
 330
 331 non_staktek:
 332                 LOADREL(v0,non_staktek_drams)
 333
 334 draminfo_done:
 335
 336 #ifdef _FUNCSIM_
 337                 LOADREL(v0,sim_drams)
 338 #endif
 339
 340                 move    ra,t0
 341                 jr      ra
 342
 343
 344         /*
 345          * Pick the table for Pass1 BCM1120Y parts.
 346          */
 347 bcm1120y_pass1_draminit:
 348                 beq     t1, BOARD_CONFIG_NONSTAKTEK, bcm1120y_pass1_non_staktek
 349
 350                 LOADREL(v0,staktek_drams_bcm1120y_pass1)
 351                 b       draminfo_done
 352
 353 bcm1120y_pass1_non_staktek:
 354                 LOADREL(v0,non_staktek_drams_bcm1120y_pass1)
 355                 b       draminfo_done
 356
 357
 358 staktek_drams:
 359
 360         /*
 361          * 512MB on MC 1 (JEDEC SDRAM)
 362          * Staktek RAMs
 363          *
 364          * NOTE: THERE IS NO MC0 ON THE 11xx!
 365          *
 366          * Minimum tMEMCLK: 8.0ns (125Mhz max freq)
 367          *
 368          * CS0 Geometry: 13 rows, 9 columns, 2 bankbits
 369          * CS1 Geometry: 13 rows, 9 columns, 2 bankbits
 370          * CS2 Geometry: 13 rows, 9 columns, 2 bankbits
 371          * CS3 Geometry: 13 rows, 9 columns, 2 bankbits
 372          *
 373          * 64khz refresh, CAS Latency 2.5
 374          * Timing (ns):   tCK=7.50 tRAS=45 tRP=20.0 tRRD=15.0 tRCD=20.0 tRFC=auto tRC=auto
 375          *
 376          * Clock Config: Addrskew 0x08, DQOskew 0x08, DQIskew 0x08,
 377          *               addrdrive 0x0f, datadrive 0x0f, clockdrive 0x0f
 378          */
 379
 380         /*
 381          * Globals: Only one memory controller, no port interleaving
 382          */
 383
 384         DRAM_GLOBALS(0)
 385
 386         DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
 387         DRAM_CHAN_CLKCFG(0x08, 0x08, 0x08, 0x0f, 0x0f, 0x0f)
 388
 389         DRAM_CS_GEOM(MC_CS0, 13, 9, 2)
 390         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 391
 392         DRAM_CS_GEOM(MC_CS1, 13, 9, 2)
 393         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 394
 395         DRAM_CS_GEOM(MC_CS2, 13, 9, 2)
 396         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 397
 398         DRAM_CS_GEOM(MC_CS3, 13, 9, 2)
 399         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 400
 401         DRAM_EOT
 402
 403
 404 staktek_drams_bcm1120y_pass1:
 405
 406         /*
 407          * Same as above, but no DRAM_CHAN_CLKCFG line so that clock config
 408          * is default, and OK for 1250pass1 die used in pass1 hybrids.
 409          */
 410
 411         DRAM_GLOBALS(0)
 412
 413         DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
 414
 415         DRAM_CS_GEOM(MC_CS0, 13, 9, 2)
 416         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 417
 418         DRAM_CS_GEOM(MC_CS1, 13, 9, 2)
 419         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 420
 421         DRAM_CS_GEOM(MC_CS2, 13, 9, 2)
 422         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 423
 424         DRAM_CS_GEOM(MC_CS3, 13, 9, 2)
 425         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 426
 427         DRAM_EOT
 428
 429
 430 non_staktek_drams:
 431
 432         /*
 433          * 256MB on MC 1 (JEDEC SDRAM)
 434          *
 435          * NOTE: THERE IS NO MC0 ON THE 11xx!
 436          *
 437          * Minimum tMEMCLK: 8.0ns (125Mhz max freq)
 438          *
 439          * CS0 Geometry: 13 rows, 9 columns, 2 bankbits
 440          * CS2 Geometry: 13 rows, 9 columns, 2 bankbits
 441          *
 442          * 64khz refresh, CAS Latency 2.5
 443          * Timing (ns):   tCK=7.50 tRAS=45 tRP=20.0 tRRD=15.0 tRCD=20.0 tRFC=auto tRC=auto
 444          *
 445          * Clock Config: Addrskew 0x08, DQOskew 0x08, DQIskew 0x08,
 446          *               addrdrive 0x0f, datadrive 0x0f, clockdrive 0x0f
 447          */
 448
 449         /*
 450          * Globals: Only one memory controller, no port interleaving
 451          */
 452
 453         DRAM_GLOBALS(0)
 454
 455         DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
 456         DRAM_CHAN_CLKCFG(0x08, 0x08, 0x08, 0x0f, 0x0f, 0x0f)
 457
 458         DRAM_CS_GEOM(MC_CS0, 13, 9, 2)
 459         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 460
 461         DRAM_CS_GEOM(MC_CS2, 13, 9, 2)
 462         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 463
 464         DRAM_EOT
 465
 466
 467 non_staktek_drams_bcm1120y_pass1:
 468
 469         /*
 470          * Same as above, but no DRAM_CHAN_CLKCFG line so that clock config
 471          * is default, and OK for 1250pass1 die used in pass1 hybrids.
 472          */
 473
 474         DRAM_GLOBALS(0)
 475
 476         DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
 477
 478         DRAM_CS_GEOM(MC_CS0, 13, 9, 2)
 479         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 480
 481         DRAM_CS_GEOM(MC_CS2, 13, 9, 2)
 482         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 483
 484         DRAM_EOT
 485
 486
 487 sim_drams:
 488
 489         /* Note: there is NO MC0 on the 11xx */
 490         /* 64MB on MC1 CS0 (SDRAM) */
 491
 492         DRAM_GLOBALS(0)
 493
 494         DRAM_CHAN_CFG(MC_CHAN1, DRT10(8,0), JEDEC, CASCHECK, BLKSIZE32, CFG_DRAM_CSINTERLEAVE, CFG_DRAM_ECC, 0)
 495
 496         DRAM_CS_GEOM(MC_CS0, 12, 9, 2)
 497         DRAM_CS_TIMING(DRT10(7,5), JEDEC_RFSH_64khz, JEDEC_CASLAT_25, 0,  45, DRT4(20,0), DRT4(15,0),  DRT4(20,0),  0, 0)
 498
 499         DRAM_EOT
 500
 501
 502
 503 END(board_draminfo)
 504
 505
 506 /*  *********************************************************************
 507     *  BOARD_PIAI2_TXCHAR
 508     *
 509     *  Transmit a single character via UART A
 510     *
 511     *  Input parameters:
 512     *      a0 - character to transmit (low-order 8 bits)
 513     *
 514     *  Return value:
 515     *      nothing
 516     *
 517     *  Registers used:
 518     *      t0,t1
 519     ********************************************************************* */
 520
 521 #ifdef _SERIAL_PORT_LEDS_
 522
 523 LEAF(board_piai2_txchar)
 524
 525         # Wait until there is space in the transmit buffer
 526
 527                 li      t0,PHYS_TO_K1(BOARD_PROMICE_BASE)
 528
 529 1:              lb      t1,BOARD_PROMICE_STATUS(t0)
 530                 andi    t1,TDA
 531                 bne     t1,zero,1b
 532
 533         # Okay, now send the character.
 534
 535                 sb      a0,BOARD_PROMICE_ZERO(t0)
 536
 537         # done!
 538
 539                 j       ra
 540
 541 END(board_piai2_txchar)
 542 #endif
 543
 544 /*  *********************************************************************
 545     *  BOARD_SETLEDS(x)
 546     *
 547     *  Set LEDs for boot-time progress indication.  Not used if
 548     *  the board does not have progress LEDs.  This routine
 549     *  must not call any other routines, since it may be invoked
 550     *  either from KSEG0 or KSEG1 and it may be invoked
 551     *  whether or not the icache is operational.
 552     *
 553     *  Input parameters:
 554     *      a0 - LED value (8 bits per character, 4 characters)
 555     *
 556     *  Return value:
 557     *      nothing
 558     *
 559     *  Registers used:
 560     *      t0,t1,t2,t3
 561     ********************************************************************* */
 562
 563 #define LED_CHAR0       (32+8*3)
 564 #define LED_CHAR1       (32+8*2)
 565 #define LED_CHAR2       (32+8*1)
 566 #define LED_CHAR3       (32+8*0)
 567
 568 LEAF(board_setleds)
 569
 570 #ifdef _SERIAL_PORT_LEDS_
 571                 move    t3,ra
 572                 move    t2,a0
 573
 574                 li      a0,'['
 575                 bal     board_piai2_txchar
 576
 577                 move    a0,t2
 578                 rol     a0,8
 579                 li      t0,PHYS_TO_K1(LEDS_PHYS)
 580                 sb      a0,LED_CHAR0(t0)
 581                 bal     board_piai2_txchar
 582
 583                 rol     a0,8
 584                 li      t0,PHYS_TO_K1(LEDS_PHYS)
 585                 sb      a0,LED_CHAR1(t0)
 586                 bal     board_piai2_txchar
 587
 588                 rol     a0,8
 589                 li      t0,PHYS_TO_K1(LEDS_PHYS)
 590                 sb      a0,LED_CHAR2(t0)
 591                 bal     board_piai2_txchar
 592
 593                 rol     a0,8
 594                 li      t0,PHYS_TO_K1(LEDS_PHYS)
 595                 sb      a0,LED_CHAR3(t0)
 596                 bal     board_piai2_txchar
 597
 598                 li      a0,']'
 599                 bal     board_piai2_txchar
 600                 li      a0,13
 601                 bal     board_piai2_txchar
 602                 li      a0,10
 603                 bal     board_piai2_txchar
 604
 605                 move    ra,t3
 606 #else
 607
 608         /*
 609          * Sending to LEDs
 610          */
 611                 li      t0,PHYS_TO_K1(LEDS_PHYS)
 612
 613                 rol     a0,a0,8
 614                 and     t1,a0,0xFF
 615                 sb      t1,LED_CHAR0(t0)
 616
 617                 rol     a0,a0,8
 618                 and     t1,a0,0xFF
 619                 sb      t1,LED_CHAR1(t0)
 620
 621                 rol     a0,a0,8
 622                 and     t1,a0,0xFF
 623                 sb      t1,LED_CHAR2(t0)
 624
 625                 rol     a0,a0,8
 626                 and     t1,a0,0xFF
 627                 sb      t1,LED_CHAR3(t0)
 628
 629 #endif
 630                 j       ra
 631
 632 END(board_setleds)