release/src-rt-6.x.4708/cfe/cfe/arch/arm/board/bcm947xx/include/platform.h

   1 /*
   2 ** Copyright 2000, 2001  Broadcom Corporation
   3 ** All Rights Reserved
   4 **
   5 ** No portions of this material may be reproduced in any form
   6 ** without the written permission of:
   7 **
   8 **   Broadcom Corporation
   9 **   5300 California Avenue
  10 **   Irvine, California 92617
  11 **
  12 ** All information contained in this document is Broadcom
  13 ** Corporation company private proprietary, and trade secret.
  14 **
  15 ** ----------------------------------------------------------
  16 **
  17 **
  18 **
  19 ** $Id::                                                          $:
  20 ** $Rev::file =  : Global SVN Revision = 1780                     $:
  21 **
  22 */
  23
  24 #ifndef PLATFORM_H__
  25 #define PLATFORM_H__
  26
  27 /* Define some default miscellaneous macros (to remove compiler's warning) */
  28 #ifndef NOT_DEFINED
  29 #define NOT_DEFINED  1
  30 #endif
  31
  32 /* Public declaration of the shmoo algorithm implementation
  33  */
  34 #include <shmoo_public.h>
  35
  36 /* Declaration of the low-level interface used by the shmoo algorithm.
  37  * This interface may be implemented or redefined differently on different platforms,
  38  * see platform specific platform_xxx.h and platform_xxx.c files
  39  */
  40 /* #include "platform_shmoo_priv.h" */
  41
  42 /*
  43  * Include API file with low-leval external API that need to be implemented for particular platform
  44  */
  45 /* DEFINE TYPES */
  46 #define uint32_t unsigned int
  47 #define int32_t int
  48 #define true  1
  49
  50 #ifndef ARRAY_SIZE
  51 #define  ARRAY_SIZE(A) (sizeof(A) / sizeof(A[0]))
  52 #endif
  53
  54 /*
  55  * Redefine TIMEOUT_VAL const
  56  */
  57 #undef TIMEOUT_VAL
  58 #define TIMEOUT_VAL     (9000)
  59
  60
  61 /*
  62  * PHY_REG_OFFSET_PER_WL is the offset in address for the two identical registers in difference WL
  63  * For BLAST, this difference is 0x200
  64  * This is for support a loop to do the same procedures for different WL
  65  */
  66 #define PHY_REG_OFFSET_PER_WL 0x200
  67 #define PHY_REG_OFFSET_PER_BL 0x0A0
  68
  69
  70 /*
  71  * Define for "read eye" test
  72  *
  73  * 1 - build shmoo procedure application
  74  * 0 - build "read eye" test application without shmoo.
  75  * It is artifact of sharing code with another platform where there was not enough memory
  76  * to build both shmoo and "read eye" applications.
  77  * for the S2_A platform SHMOO_BUILD will always be 1
  78  */
  79 #define SHMOO_BUILD                             1
  80
  81
  82 /*
  83  * Redefine function style cast that is used in the tinymt.* files
  84  */
  85 #undef UINT32_C
  86 #define UINT32_C(V) ((uint32_t)(V))
  87
  88 #undef UINT64_C
  89 #define UINT64_C(V) ((uint64_t)(V))
  90
  91 #ifndef FALSE
  92 #define FALSE           0
  93 #endif
  94 #ifndef TRUE
  95 #define TRUE            (!(FALSE))
  96 #endif
  97
  98 /*
  99  * Include original RDB file
 100  */
 101
 102 /*
 103  * PHY platform independent registers description
 104  */
 105 #include "ddr40_phy_registers.h"
 106
 107 /*
 108  * Output functions for 2-dimensional printing of the logs using Linux printk() function
 109  */
 110
 111 #define PHY_VER_D       0
 112
 113 /*
 114  * DRAM read/write functions
 115  * Undefine existing macros
 116  */
 117 #undef SHMOO_DRAM_READ_32
 118 #undef SHMOO_DRAM_WRITE_32
 119
 120 unsigned int SHMOO_DRAM_READ_32(ddr40_addr_t Address);
 121 void SHMOO_DRAM_WRITE_32(ddr40_addr_t Addres, unsigned int Data);
 122
 123
 124 /*
 125  * Those defines are not used in S2_A platform because start address of the DRAM range
 126  * is dynamic
 127  */
 128 #undef SHMOO_DRAM_START_ADDR
 129 #define SHMOO_DRAM_START_ADDR   (0x80000000u)
 130
 131 #undef SHMOO_DRAM_END_ADDR
 132 #define SHMOO_DRAM_END_ADDR     (SHMOO_DRAM_START_ADDR + 0x00008000u)
 133
 134
 135 /*
 136  * Registers read/write functions
 137  * Undefine existing macros and replace them with the functions
 138  */
 139 #undef tb_r
 140 #undef tb_w
 141
 142 unsigned int tb_r(ddr40_addr_t Address);
 143 void tb_w(ddr40_addr_t Addres, unsigned int Data);
 144
 145 /*
 146  * Undefine NL macro and replace it with the function
 147  */
 148 #undef NL
 149 void NL(void);
 150
 151 /*
 152  * Redefine macros from the PHY init code to use functions that will print
 153  * C-style messages
 154  */
 155 #ifdef BCMDBG
 156 void PrintfLog(char * const ptFormatStr, ...);
 157 void PrintfErr(char * const ptFormatStr, ...);
 158 void PrintfFatal(char * const ptFormatStr, ...);
 159
 160 #define  print_log   PrintfLog
 161 #define  error_log   PrintfErr
 162 #define  fatal_log   PrintfFatal
 163 #else
 164 #define  print_log(args...)
 165 #define  error_log(args...)
 166 #define  fatal_log(args...)
 167 #endif
 168
 169
 170 /*
 171  * It is 0 because DDR PHY RDB will have physical base address (not relative)
 172  */
 173 #define GLOBAL_REG_RBUS_START   (0)
 174
 175 /*
 176  * This define is not necessary for the S2_A platform because it has other
 177  * memory controller
 178  */
 179 #define MEMC_BASE_ADDR          (0)
 180
 181 /*
 182  * This is the base address of the PHY registers.
 183  * First block of the registers is control registers
 184  * two following are WL 0 and WL 1 registers
 185  */
 186 #define PHY_CONTROL_BASE_ADDRESS        (DDR_R_DDR40_PHY_ADDR_CTL_REVISION_MEMADDR)
 187
 188
 189 /*
 190  * Verify some defines
 191  */
 192 #if defined(SHMOO_DRAM_START_ADDR)
 193 #if (SHMOO_DRAM_START_ADDR == NOT_DEFINED)
 194 #error DRAM start address is not redefined
 195 #endif
 196 #else
 197 #error DRAM start address is not defined
 198 #endif /* defined(SHMOO_DRAM_START_ADDR) */
 199
 200 #if defined(SHMOO_DRAM_END_ADDR)
 201 #if (SHMOO_DRAM_END_ADDR == NOT_DEFINED)
 202 #error DRAM end address is not redefined
 203 #endif
 204 #else
 205 #error DRAM end address is not defined
 206 #endif /* defined(SHMOO_DRAM_END_ADDR) */
 207
 208 #ifndef GLOBAL_REG_RBUS_START
 209 #error Registers address is not defined
 210 #endif
 211
 212 #ifndef PHY_CONTROL_BASE_ADDRESS
 213 #error PHY Control registers base address is not defined
 214 #endif
 215
 216 #ifndef MEMC_BASE_ADDR
 217 #error MEMC base address is not defined
 218 #endif
 219
 220 void timeout_ns(unsigned int nsec);
 221 #endif /* PLATFORM_H__ */