release/src-rt-6.x.4708/cfe/build/broadcom/tiny/tiny.h

   1 /*  *********************************************************************
   2     *  SB1250 Board Support Package
   3     *
   4     *  Swarm (CSWARM) Definitions                  File: swarm.h
   5     *
   6     *  This file contains I/O, chip select, and GPIO assignments
   7     *  for the BCM912500A checkout board.
   8     *
   9     *  Author:  Mitch Lichtenberg (mpl@broadcom.com)
  10     *
  11     *********************************************************************
  12     *
  13     *  Copyright 2000,2001,2002,2003
  14     *  Broadcom Corporation. All rights reserved.
  15     *
  16     *  This software is furnished under license and may be used and
  17     *  copied only in accordance with the following terms and
  18     *  conditions.  Subject to these conditions, you may download,
  19     *  copy, install, use, modify and distribute modified or unmodified
  20     *  copies of this software in source and/or binary form.  No title
  21     *  or ownership is transferred hereby.
  22     *
  23     *  1) Any source code used, modified or distributed must reproduce
  24     *     and retain this copyright notice and list of conditions
  25     *     as they appear in the source file.
  26     *
  27     *  2) No right is granted to use any trade name, trademark, or
  28     *     logo of Broadcom Corporation.  The "Broadcom Corporation"
  29     *     name may not be used to endorse or promote products derived
  30     *     from this software without the prior written permission of
  31     *     Broadcom Corporation.
  32     *
  33     *  3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
  34     *     IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
  35     *     WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
  36     *     PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
  37     *     SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
  38     *     PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
  39     *     INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  40     *     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
  41     *     GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
  42     *     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
  43     *     OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  44     *     TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
  45     *     THE POSSIBILITY OF SUCH DAMAGE.
  46     ********************************************************************* */
  47
  48
  49 /*
  50  * I/O Address assignments for the CSWARM board
  51  *
  52  * Summary of address map:
  53  *
  54  * Address         Size   CSel    Description
  55  * --------------- ----   ------  --------------------------------
  56  * 0x1FC00000      2MB     CS0    Boot ROM
  57  * 0x1F800000      2MB     CS1    Alternate boot ROM
  58  *                         CS2    Unused
  59  * 0x100A0000      64KB    CS3    LED display
  60  * 0x100B0000      64KB    CS4    IDE Disk
  61  *                         CS5    Unused
  62  * 0x11000000      64MB    CS6    PCMCIA
  63  *                         CS7    Unused
  64  *
  65  * GPIO assignments
  66  *
  67  * GPIO#    Direction   Description
  68  * -------  ---------   ------------------------------------------
  69  * GPIO0    Output      Debug LED
  70  * GPIO1    Output      Sturgeon NMI
  71  * GPIO2    Input       PHY Interrupt               (interrupt)
  72  * GPIO3    Input       Nonmaskable Interrupt       (interrupt)
  73  * GPIO4    Input       IDE Disk Interrupt          (interrupt)
  74  * GPIO5    Input       Temperature Sensor Alert    (interrupt)
  75  * GPIO6    N/A         PCMCIA interface
  76  * GPIO7    N/A         PCMCIA interface
  77  * GPIO8    N/A         PCMCIA interface
  78  * GPIO9    N/A         PCMCIA interface
  79  * GPIO10   N/A         PCMCIA interface
  80  * GPIO11   N/A         PCMCIA interface
  81  * GPIO12   N/A         PCMCIA interface
  82  * GPIO13   N/A         PCMCIA interface
  83  * GPIO14   N/A         PCMCIA interface
  84  * GPIO15   N/A         PCMCIA interface
  85  */
  86
  87 /*  *********************************************************************
  88     *  Macros
  89     ********************************************************************* */
  90
  91 #define MB (1024*1024)
  92 #define K64 65536
  93 #define NUM64K(x) (((x)+(K64-1))/K64)
  94
  95
  96 /*  *********************************************************************
  97     *  GPIO pins
  98     ********************************************************************* */
  99
 100 #define GPIO_DEBUG_LED          0
 101 #define GPIO_STURGEON_NMI       1
 102 #define GPIO_PHY_INTERRUPT      2
 103 #define GPIO_NONMASKABLE_INT    3
 104 #define GPIO_IDE_INTERRUPT      4
 105 #define GPIO_TEMP_SENSOR_INT    5
 106
 107 #define M_GPIO_DEBUG_LED        _SB_MAKEMASK1(GPIO_DEBUG_LED)
 108 #define M_GPIO_STURGEON_NMI     _SB_MAKEMASK1(GPIO_STURGEON_NMI)
 109
 110 #define GPIO_OUTPUT_MASK (_SB_MAKEMASK1(GPIO_DEBUG_LED) | \
 111                           _SB_MAKEMASK1(GPIO_STURGEON_NMI) )
 112
 113 #define GPIO_INTERRUPT_MASK ((V_GPIO_INTR_TYPEX(GPIO_PHY_INTERRUPT,K_GPIO_INTR_LEVEL)) | \
 114                              (V_GPIO_INTR_TYPEX(GPIO_IDE_INTERRUPT,K_GPIO_INTR_LEVEL)))
 115
 116
 117 /*  *********************************************************************
 118     *  Generic Bus
 119     ********************************************************************* */
 120
 121 #define BOOTROM_CS              0
 122 #define BOOTROM_PHYS            0x1FC00000      /* address of boot ROM (CS0) */
 123 #define BOOTROM_SIZE            NUM64K(2*MB)    /* size of boot ROM */
 124 #define BOOTROM_TIMING0         V_IO_ALE_WIDTH(4) | \
 125                                 V_IO_ALE_TO_CS(2) | \
 126                                 V_IO_CS_WIDTH(24) | \
 127                                 V_IO_RDY_SMPLE(1)
 128 #define BOOTROM_TIMING1         V_IO_ALE_TO_WRITE(7) | \
 129                                 V_IO_WRITE_WIDTH(7) | \
 130                                 V_IO_IDLE_CYCLE(6) | \
 131                                 V_IO_CS_TO_OE(0) | \
 132                                 V_IO_OE_TO_CS(0)
 133 #define BOOTROM_CONFIG          V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 134
 135 #define ALT_BOOTROM_CS          1
 136 #define ALT_BOOTROM_PHYS        0x1F800000      /* address of alternate boot ROM (CS1) */
 137 #define ALT_BOOTROM_SIZE        NUM64K(2*MB)    /* size of alternate boot ROM */
 138 #define ALT_BOOTROM_TIMING0     V_IO_ALE_WIDTH(4) | \
 139                                 V_IO_ALE_TO_CS(2) | \
 140                                 V_IO_CS_WIDTH(24) | \
 141                                 V_IO_RDY_SMPLE(1)
 142 #define ALT_BOOTROM_TIMING1     V_IO_ALE_TO_WRITE(7) | \
 143                                 V_IO_WRITE_WIDTH(7) | \
 144                                 V_IO_IDLE_CYCLE(6) | \
 145                                 V_IO_CS_TO_OE(0) | \
 146                                 V_IO_OE_TO_CS(0)
 147 #define ALT_BOOTROM_CONFIG      V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 148
 149 /*
 150  * LEDs:  non-multiplexed, byte width, no parity, no ack
 151  */
 152 #define LEDS_CS                 3
 153 #define LEDS_PHYS               0x100A0000
 154 #define LEDS_SIZE               NUM64K(4)
 155 #define LEDS_TIMING0            V_IO_ALE_WIDTH(4) | \
 156                                 V_IO_ALE_TO_CS(2) | \
 157                                 V_IO_CS_WIDTH(13) | \
 158                                 V_IO_RDY_SMPLE(1)
 159 #define LEDS_TIMING1            V_IO_ALE_TO_WRITE(2) | \
 160                                 V_IO_WRITE_WIDTH(8) | \
 161                                 V_IO_IDLE_CYCLE(6) | \
 162                                 V_IO_CS_TO_OE(0) | \
 163                                 V_IO_OE_TO_CS(0)
 164 #define LEDS_CONFIG             V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_1) | M_IO_NONMUX
 165
 166
 167 /*
 168  * IDE: non-multiplexed, word(16) width, no parity, ack mode
 169  * See BCM12500 Application Note: "BCM12500 Generic Bus Interface
 170  * to ATA/ATAPI PIO Mode 3 (IDE) Hard Disk"
 171  */
 172 #define IDE_CS                  4
 173 #define IDE_PHYS                0x100B0000
 174 #define IDE_SIZE                NUM64K(256)
 175 #define IDE_TIMING0             V_IO_ALE_WIDTH(3) | \
 176                                 V_IO_ALE_TO_CS(1) | \
 177                                 V_IO_CS_WIDTH(8) | \
 178                                 V_IO_RDY_SMPLE(2)
 179 #define IDE_TIMING1             V_IO_ALE_TO_WRITE(4) | \
 180                                 V_IO_WRITE_WIDTH(0xA) | \
 181                                 V_IO_IDLE_CYCLE(1) | \
 182                                 V_IO_CS_TO_OE(3) | \
 183                                 V_IO_OE_TO_CS(2)
 184 #define IDE_CONFIG              V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2) | \
 185                                 M_IO_RDY_ACTIVE | \
 186                                 M_IO_ENA_RDY
 187
 188
 189
 190 /*
 191  * PCMCIA: this information was derived from chapter 12, table 12-5
 192  */
 193 #define PCMCIA_CS               6
 194 #define PCMCIA_PHYS             0x11000000
 195 #define PCMCIA_SIZE             NUM64K(64*MB)
 196 #define PCMCIA_TIMING0          V_IO_ALE_WIDTH(3) | \
 197                                 V_IO_ALE_TO_CS(1) | \
 198                                 V_IO_CS_WIDTH(17) | \
 199                                 V_IO_RDY_SMPLE(1)
 200 #define PCMCIA_TIMING1          V_IO_ALE_TO_WRITE(8) | \
 201                                 V_IO_WRITE_WIDTH(8) | \
 202                                 V_IO_IDLE_CYCLE(2) | \
 203                                 V_IO_CS_TO_OE(0) | \
 204                                 V_IO_OE_TO_CS(0)
 205 #define PCMCIA_CONFIG           V_IO_WIDTH_SEL(K_IO_WIDTH_SEL_2)
 206
 207
 208 /*  *********************************************************************
 209     *  SMBus Devices
 210     ********************************************************************* */
 211
 212 #define TEMPSENSOR_SMBUS_CHAN   0
 213 #define TEMPSENSOR_SMBUS_DEV    0x2A
 214 #define DRAM_SMBUS_CHAN         0
 215 #define DRAM_SMBUS_DEV          0x54
 216 #define BIGEEPROM_SMBUS_CHAN    0
 217 #define BIGEEPROM_SMBUS_DEV     0x50
 218 #define X1240_SMBUS_CHAN        1
 219 #define X1240_SMBUS_DEV         0x50