2 * Broadcom 53xx RoboSwitch device driver.
4 * Copyright 2007, Broadcom Corporation
7 * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8 * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9 * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10 * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
22 #include <bcmendian.h>
23 #include <bcmparams.h>
27 #include <proto/ethernet.h>
29 #define ET_ERROR(args)
33 * Switch can be programmed through SPI interface, which
34 * has a rreg and a wreg functions to read from and write to
38 /* MII access registers */
39 #define PSEUDO_PHYAD 0x1E /* MII Pseudo PHY address */
40 #define REG_MII_PAGE 0x10 /* MII Page register */
41 #define REG_MII_ADDR 0x11 /* MII Address register */
42 #define REG_MII_DATA0 0x18 /* MII Data register 0 */
43 #define REG_MII_DATA1 0x19 /* MII Data register 1 */
44 #define REG_MII_DATA2 0x1a /* MII Data register 2 */
45 #define REG_MII_DATA3 0x1b /* MII Data register 3 */
48 #define PAGE_CTRL 0x00 /* Control page */
49 #define PAGE_MMR 0x02 /* 5397 Management/Mirroring page */
50 #define PAGE_VTBL 0x05 /* ARL/VLAN Table access page */
51 #define PAGE_VLAN 0x34 /* VLAN page */
53 /* Control page registers */
54 #define REG_CTRL_PORT0 0x00 /* Port 0 traffic control register */
55 #define REG_CTRL_PORT1 0x01 /* Port 1 traffic control register */
56 #define REG_CTRL_PORT2 0x02 /* Port 2 traffic control register */
57 #define REG_CTRL_PORT3 0x03 /* Port 3 traffic control register */
58 #define REG_CTRL_PORT4 0x04 /* Port 4 traffic control register */
59 #define REG_CTRL_PORT5 0x05 /* Port 5 traffic control register */
60 #define REG_CTRL_PORT6 0x06 /* Port 6 traffic control register */
61 #define REG_CTRL_PORT7 0x07 /* Port 7 traffic control register */
62 #define REG_CTRL_MODE 0x0B /* Switch Mode register */
63 #define REG_CTRL_MIIPO 0x0E /* 5325: MII Port Override register */
64 #define REG_CTRL_SRST 0x79 /* Software reset control register */
66 #define REG_DEVICE_ID 0x30 /* 539x Device id: */
67 #define DEVID5325 0x25 /* 5325 (Not really be we fake it) */
68 #define DEVID5395 0x95 /* 5395 */
69 #define DEVID5397 0x97 /* 5397 */
70 #define DEVID5398 0x98 /* 5398 */
72 /* VLAN page registers */
73 #define REG_VLAN_CTRL0 0x00 /* VLAN Control 0 register */
74 #define REG_VLAN_CTRL1 0x01 /* VLAN Control 1 register */
75 #define REG_VLAN_CTRL4 0x04 /* VLAN Control 4 register */
76 #define REG_VLAN_CTRL5 0x05 /* VLAN Control 5 register */
77 #define REG_VLAN_ACCESS 0x06 /* VLAN Table Access register */
78 #define REG_VLAN_ACCESS_5365 0x08 /* 5365 VLAN Table Access register */
79 #define REG_VLAN_WRITE 0x08 /* VLAN Write register */
80 #define REG_VLAN_WRITE_5365 0x0A /* 5365 VLAN Write register */
81 #define REG_VLAN_READ 0x0C /* VLAN Read register */
82 #define REG_VLAN_PTAG0 0x10 /* VLAN Default Port Tag register - port 0 */
83 #define REG_VLAN_PTAG1 0x12 /* VLAN Default Port Tag register - port 1 */
84 #define REG_VLAN_PTAG2 0x14 /* VLAN Default Port Tag register - port 2 */
85 #define REG_VLAN_PTAG3 0x16 /* VLAN Default Port Tag register - port 3 */
86 #define REG_VLAN_PTAG4 0x18 /* VLAN Default Port Tag register - port 4 */
87 #define REG_VLAN_PTAG5 0x1a /* VLAN Default Port Tag register - port 5 */
88 #define REG_VLAN_PTAG6 0x1c /* VLAN Default Port Tag register - port 6 */
89 #define REG_VLAN_PTAG7 0x1e /* VLAN Default Port Tag register - port 7 */
90 #define REG_VLAN_PTAG8 0x20 /* 539x: VLAN Default Port Tag register - IMP port */
91 #define REG_VLAN_PMAP 0x20 /* 5325: VLAN Priority Re-map register */
93 #define VLAN_NUMVLANS 16 /* # of VLANs */
96 /* ARL/VLAN Table Access page registers */
97 #define REG_VTBL_CTRL 0x00 /* ARL Read/Write Control */
98 #define REG_VTBL_MINDX 0x02 /* MAC Address Index */
99 #define REG_VTBL_VINDX 0x08 /* VID Table Index */
100 #define REG_VTBL_ARL_E0 0x10 /* ARL Entry 0 */
101 #define REG_VTBL_ARL_E1 0x18 /* ARL Entry 1 */
102 #define REG_VTBL_DAT_E0 0x18 /* ARL Table Data Entry 0 */
103 #define REG_VTBL_SCTRL 0x20 /* ARL Search Control */
104 #define REG_VTBL_SADDR 0x22 /* ARL Search Address */
105 #define REG_VTBL_SRES 0x24 /* ARL Search Result */
106 #define REG_VTBL_SREXT 0x2c /* ARL Search Result */
107 #define REG_VTBL_VID_E0 0x30 /* VID Entry 0 */
108 #define REG_VTBL_VID_E1 0x32 /* VID Entry 1 */
109 #define REG_VTBL_PREG 0xFF /* Page Register */
110 #define REG_VTBL_ACCESS 0x60 /* VLAN table access register */
111 #define REG_VTBL_INDX 0x61 /* VLAN table address index register */
112 #define REG_VTBL_ENTRY 0x63 /* VLAN table entry register */
113 #define REG_VTBL_ACCESS_5395 0x80 /* VLAN table access register */
114 #define REG_VTBL_INDX_5395 0x81 /* VLAN table address index register */
115 #define REG_VTBL_ENTRY_5395 0x83 /* VLAN table entry register */
118 #define REG_SPI_PAGE 0xff /* SPI Page register */
120 /* Access switch registers through GPIO/SPI */
122 /* Minimum timing constants */
123 #define SCK_EDGE_TIME 2 /* clock edge duration - 2us */
124 #define MOSI_SETUP_TIME 1 /* input setup duration - 1us */
125 #define SS_SETUP_TIME 1 /* select setup duration - 1us */
127 /* misc. constants */
128 #define SPI_MAX_RETRY 100
130 /* Enable GPIO access to the chip */
132 gpio_enable(robo_info_t
*robo
)
134 /* Enable GPIO outputs with SCK and MOSI low, SS high */
135 sb_gpioout(robo
->sbh
, robo
->ss
| robo
->sck
| robo
->mosi
, robo
->ss
, GPIO_DRV_PRIORITY
);
136 sb_gpioouten(robo
->sbh
, robo
->ss
| robo
->sck
| robo
->mosi
,
137 robo
->ss
| robo
->sck
| robo
->mosi
, GPIO_DRV_PRIORITY
);
140 /* Disable GPIO access to the chip */
142 gpio_disable(robo_info_t
*robo
)
144 /* Disable GPIO outputs with all their current values */
145 sb_gpioouten(robo
->sbh
, robo
->ss
| robo
->sck
| robo
->mosi
, 0, GPIO_DRV_PRIORITY
);
148 /* Write a byte stream to the chip thru SPI */
150 spi_write(robo_info_t
*robo
, uint8
*buf
, uint len
)
155 /* Byte bang from LSB to MSB */
156 for (i
= 0; i
< len
; i
++) {
157 /* Bit bang from MSB to LSB */
158 for (mask
= 0x80; mask
; mask
>>= 1) {
160 sb_gpioout(robo
->sbh
, robo
->sck
, 0, GPIO_DRV_PRIORITY
);
161 OSL_DELAY(SCK_EDGE_TIME
);
163 /* Sample on rising edge */
165 sb_gpioout(robo
->sbh
, robo
->mosi
, robo
->mosi
, GPIO_DRV_PRIORITY
);
167 sb_gpioout(robo
->sbh
, robo
->mosi
, 0, GPIO_DRV_PRIORITY
);
168 OSL_DELAY(MOSI_SETUP_TIME
);
171 sb_gpioout(robo
->sbh
, robo
->sck
, robo
->sck
, GPIO_DRV_PRIORITY
);
172 OSL_DELAY(SCK_EDGE_TIME
);
179 /* Read a byte stream from the chip thru SPI */
181 spi_read(robo_info_t
*robo
, uint8
*buf
, uint len
)
184 uint8 rack
, mask
, byte
;
186 /* Timeout after 100 tries without RACK */
187 for (i
= 0, rack
= 0, timeout
= SPI_MAX_RETRY
; i
< len
&& timeout
;) {
188 /* Bit bang from MSB to LSB */
189 for (mask
= 0x80, byte
= 0; mask
; mask
>>= 1) {
191 sb_gpioout(robo
->sbh
, robo
->sck
, 0, GPIO_DRV_PRIORITY
);
192 OSL_DELAY(SCK_EDGE_TIME
);
194 /* Sample on falling edge */
195 if (sb_gpioin(robo
->sbh
) & robo
->miso
)
199 sb_gpioout(robo
->sbh
, robo
->sck
, robo
->sck
, GPIO_DRV_PRIORITY
);
200 OSL_DELAY(SCK_EDGE_TIME
);
202 /* RACK when bit 0 is high */
208 /* Byte bang from LSB to MSB */
214 ET_ERROR(("spi_read: timeout"));
221 /* Enable/disable SPI access */
223 spi_select(robo_info_t
*robo
, uint8 spi
)
226 /* Enable SPI access */
227 sb_gpioout(robo
->sbh
, robo
->ss
, 0, GPIO_DRV_PRIORITY
);
229 /* Disable SPI access */
230 sb_gpioout(robo
->sbh
, robo
->ss
, robo
->ss
, GPIO_DRV_PRIORITY
);
232 OSL_DELAY(SS_SETUP_TIME
);
236 /* Select chip and page */
238 spi_goto(robo_info_t
*robo
, uint8 page
)
240 uint8 reg8
= REG_SPI_PAGE
; /* page select register */
243 /* Issue the command only when we are on a different page */
244 if (robo
->page
== page
)
249 /* Enable SPI access */
252 /* Select new page with CID 0 */
253 cmd8
= ((6 << 4) | /* normal SPI */
255 spi_write(robo
, &cmd8
, 1);
256 spi_write(robo
, ®8
, 1);
257 spi_write(robo
, &page
, 1);
259 /* Disable SPI access */
263 /* Write register thru SPI */
265 spi_wreg(robo_info_t
*robo
, uint8 page
, uint8 addr
, void *val
, int len
)
275 /* validate value length and buffer address */
276 ASSERT(len
== 1 || (len
== 2 && !((int)val
& 1)) ||
277 (len
== 4 && !((int)val
& 3)));
279 /* Select chip and page */
280 spi_goto(robo
, page
);
282 /* Enable SPI access */
285 /* Write with CID 0 */
286 cmd8
= ((6 << 4) | /* normal SPI */
288 spi_write(robo
, &cmd8
, 1);
289 spi_write(robo
, &addr
, 1);
292 bytes
.val8
= *(uint8
*)val
;
295 bytes
.val16
= htol16(*(uint16
*)val
);
298 bytes
.val32
= htol32(*(uint32
*)val
);
301 spi_write(robo
, (uint8
*)val
, len
);
303 ET_MSG(("%s: [0x%x-0x%x] := 0x%x (len %d)\n", __FUNCTION__
, page
, addr
,
304 *(uint16
*)val
, len
));
305 /* Disable SPI access */
310 /* Read register thru SPI in fast SPI mode */
312 spi_rreg(robo_info_t
*robo
, uint8 page
, uint8 addr
, void *val
, int len
)
322 /* validate value length and buffer address */
323 ASSERT(len
== 1 || (len
== 2 && !((int)val
& 1)) ||
324 (len
== 4 && !((int)val
& 3)));
326 /* Select chip and page */
327 spi_goto(robo
, page
);
329 /* Enable SPI access */
332 /* Fast SPI read with CID 0 and byte offset 0 */
333 cmd8
= (1 << 4); /* fast SPI */
334 spi_write(robo
, &cmd8
, 1);
335 spi_write(robo
, &addr
, 1);
336 status
= spi_read(robo
, (uint8
*)&bytes
, len
);
339 *(uint8
*)val
= bytes
.val8
;
342 *(uint16
*)val
= ltoh16(bytes
.val16
);
345 *(uint32
*)val
= ltoh32(bytes
.val32
);
349 ET_MSG(("%s: [0x%x-0x%x] => 0x%x (len %d)\n", __FUNCTION__
, page
, addr
,
350 *(uint16
*)val
, len
));
352 /* Disable SPI access */
357 /* SPI/gpio interface functions */
358 static dev_ops_t spigpio
= {
367 /* Access switch registers through MII (MDC/MDIO) */
369 #define MII_MAX_RETRY 100
371 /* Write register thru MDC/MDIO */
373 mii_wreg(robo_info_t
*robo
, uint8 page
, uint8 reg
, void *val
, int len
)
378 uint8
*ptr
= (uint8
*)val
;
380 /* validate value length and buffer address */
381 ASSERT(len
== 1 || len
== 6 || len
== 8 ||
382 ((len
== 2) && !((int)val
& 1)) || ((len
== 4) && !((int)val
& 3)));
384 ET_MSG(("%s: [0x%x-0x%x] := 0x%x (len %d)\n", __FUNCTION__
, page
, reg
,
385 *(uint16
*)val
, len
));
387 /* set page number - MII register 0x10 */
388 if (robo
->page
!= page
) {
389 cmd16
= ((page
<< 8) | /* page number */
390 1); /* mdc/mdio access enable */
391 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_PAGE
, cmd16
);
398 val16
= ((val16
<< 8) | ptr
[6]);
399 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_DATA3
, val16
);
404 val16
= ((val16
<< 8) | ptr
[4]);
405 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_DATA2
, val16
);
407 val16
= ((val16
<< 8) | ptr
[2]);
408 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_DATA1
, val16
);
410 val16
= ((val16
<< 8) | ptr
[0]);
411 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_DATA0
, val16
);
415 val16
= (uint16
)((*(uint32
*)val
) >> 16);
416 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_DATA1
, val16
);
417 val16
= (uint16
)(*(uint32
*)val
);
418 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_DATA0
, val16
);
422 val16
= *(uint16
*)val
;
423 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_DATA0
, val16
);
427 val16
= *(uint8
*)val
;
428 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_DATA0
, val16
);
432 /* set register address - MII register 0x11 */
433 cmd16
= ((reg
<< 8) | /* register address */
434 1); /* opcode write */
435 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_ADDR
, cmd16
);
437 /* is operation finished? */
438 for (i
= MII_MAX_RETRY
; i
> 0; i
--) {
439 val16
= robo
->miird(h
, PSEUDO_PHYAD
, REG_MII_ADDR
);
440 if ((val16
& 3) == 0)
446 ET_ERROR(("mii_wreg: timeout"));
452 /* Read register thru MDC/MDIO */
454 mii_rreg(robo_info_t
*robo
, uint8 page
, uint8 reg
, void *val
, int len
)
459 uint8
*ptr
= (uint8
*)val
;
461 /* validate value length and buffer address */
462 ASSERT(len
== 1 || len
== 6 || len
== 8 ||
463 ((len
== 2) && !((int)val
& 1)) || ((len
== 4) && !((int)val
& 3)));
465 /* set page number - MII register 0x10 */
466 if (robo
->page
!= page
) {
467 cmd16
= ((page
<< 8) | /* page number */
468 1); /* mdc/mdio access enable */
469 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_PAGE
, cmd16
);
473 /* set register address - MII register 0x11 */
474 cmd16
= ((reg
<< 8) | /* register address */
475 2); /* opcode read */
476 robo
->miiwr(h
, PSEUDO_PHYAD
, REG_MII_ADDR
, cmd16
);
478 /* is operation finished? */
479 for (i
= MII_MAX_RETRY
; i
> 0; i
--) {
480 val16
= robo
->miird(h
, PSEUDO_PHYAD
, REG_MII_ADDR
);
481 if ((val16
& 3) == 0)
486 ET_ERROR(("mii_rreg: timeout"));
490 ET_MSG(("%s: [0x%x-0x%x] => 0x%x (len %d)\n", __FUNCTION__
, page
, reg
, val16
, len
));
494 val16
= robo
->miird(h
, PSEUDO_PHYAD
, REG_MII_DATA3
);
495 ptr
[7] = (val16
>> 8);
496 ptr
[6] = (val16
& 0xff);
500 val16
= robo
->miird(h
, PSEUDO_PHYAD
, REG_MII_DATA2
);
501 ptr
[5] = (val16
>> 8);
502 ptr
[4] = (val16
& 0xff);
503 val16
= robo
->miird(h
, PSEUDO_PHYAD
, REG_MII_DATA1
);
504 ptr
[3] = (val16
>> 8);
505 ptr
[2] = (val16
& 0xff);
506 val16
= robo
->miird(h
, PSEUDO_PHYAD
, REG_MII_DATA0
);
507 ptr
[1] = (val16
>> 8);
508 ptr
[0] = (val16
& 0xff);
512 val16
= robo
->miird(h
, PSEUDO_PHYAD
, REG_MII_DATA1
);
513 *(uint32
*)val
= (((uint32
)val16
) << 16);
514 val16
= robo
->miird(h
, PSEUDO_PHYAD
, REG_MII_DATA0
);
515 *(uint32
*)val
|= val16
;
519 val16
= robo
->miird(h
, PSEUDO_PHYAD
, REG_MII_DATA0
);
520 *(uint16
*)val
= val16
;
524 val16
= robo
->miird(h
, PSEUDO_PHYAD
, REG_MII_DATA0
);
525 *(uint8
*)val
= (uint8
)(val16
& 0xff);
532 /* MII interface functions */
533 static dev_ops_t mdcmdio
= {
541 /* High level switch configuration functions. */
543 /* Get access to the RoboSwitch */
545 bcm_robo_attach(sb_t
*sbh
, void *h
, char *vars
, miird_f miird
, miiwr_f miiwr
)
550 /* Allocate and init private state */
551 if (!(robo
= MALLOC(sb_osh(sbh
), sizeof(robo_info_t
)))) {
552 ET_ERROR(("robo_attach: out of memory, malloced %d bytes", MALLOCED(sb_osh(sbh
))));
555 bzero(robo
, sizeof(robo_info_t
));
564 /* Trigger external reset by nvram variable existance */
565 if ((reset
= getgpiopin(robo
->vars
, "robo_reset", GPIO_PIN_NOTDEFINED
)) !=
566 GPIO_PIN_NOTDEFINED
) {
568 * Reset sequence: RESET low(50ms)->high(20ms)
570 * We have to perform a full sequence for we don't know how long
571 * it has been from power on till now.
573 ET_MSG(("%s: Using external reset in gpio pin %d\n", __FUNCTION__
, reset
));
576 /* Keep RESET low for 50 ms */
577 sb_gpioout(robo
->sbh
, reset
, 0, GPIO_DRV_PRIORITY
);
578 sb_gpioouten(robo
->sbh
, reset
, reset
, GPIO_DRV_PRIORITY
);
581 /* Keep RESET high for at least 20 ms */
582 sb_gpioout(robo
->sbh
, reset
, reset
, GPIO_DRV_PRIORITY
);
585 /* In case we need it */
586 idx
= sb_coreidx(robo
->sbh
);
588 if (sb_setcore(robo
->sbh
, SB_ROBO
, 0)) {
589 /* If we have an internal robo core, reset it using sb_core_reset */
590 ET_MSG(("%s: Resetting internal robo core\n", __FUNCTION__
));
591 sb_core_reset(robo
->sbh
, 0, 0);
594 sb_setcoreidx(robo
->sbh
, idx
);
597 if (miird
&& miiwr
) {
599 int rc
, retry_count
= 0;
601 /* Read the PHY ID */
602 tmp
= miird(h
, PSEUDO_PHYAD
, 2);
605 rc
= mii_rreg(robo
, PAGE_MMR
, REG_DEVICE_ID
, \
606 &robo
->devid
, sizeof(uint16
));
610 } while ((robo
->devid
== 0) && (retry_count
< 10));
612 ET_MSG(("%s: devid read %ssuccesfully via mii: 0x%x\n", __FUNCTION__
, \
613 rc
? "un" : "", robo
->devid
));
614 ET_MSG(("%s: mii access to switch works\n", __FUNCTION__
));
615 robo
->ops
= &mdcmdio
;
616 if ((rc
!= 0) || (robo
->devid
== 0)) {
617 ET_MSG(("%s: error reading devid, assuming 5325e\n", __FUNCTION__
));
618 robo
->devid
= DEVID5325
;
620 ET_MSG(("%s: devid: 0x%x\n", __FUNCTION__
, robo
->devid
));
624 if ((robo
->devid
== DEVID5395
) ||
625 (robo
->devid
== DEVID5397
) ||
626 (robo
->devid
== DEVID5398
)) {
629 /* If it is a 539x switch, use the soft reset register */
630 ET_MSG(("%s: Resetting 539x robo switch\n", __FUNCTION__
));
632 /* Reset the 539x switch core and register file */
634 mii_wreg(robo
, PAGE_CTRL
, REG_CTRL_SRST
, &srst_ctrl
, sizeof(uint8
));
636 mii_wreg(robo
, PAGE_CTRL
, REG_CTRL_SRST
, &srst_ctrl
, sizeof(uint8
));
640 int mosi
, miso
, ss
, sck
;
642 robo
->ops
= &spigpio
;
643 robo
->devid
= DEVID5325
;
645 /* Init GPIO mapping. Default 2, 3, 4, 5 */
646 ss
= getgpiopin(vars
, "robo_ss", 2);
647 if (ss
== GPIO_PIN_NOTDEFINED
) {
648 ET_ERROR(("robo_attach: robo_ss gpio fail: GPIO 2 in use"));
652 sck
= getgpiopin(vars
, "robo_sck", 3);
653 if (sck
== GPIO_PIN_NOTDEFINED
) {
654 ET_ERROR(("robo_attach: robo_sck gpio fail: GPIO 3 in use"));
657 robo
->sck
= 1 << sck
;
658 mosi
= getgpiopin(vars
, "robo_mosi", 4);
659 if (mosi
== GPIO_PIN_NOTDEFINED
) {
660 ET_ERROR(("robo_attach: robo_mosi gpio fail: GPIO 4 in use"));
663 robo
->mosi
= 1 << mosi
;
664 miso
= getgpiopin(vars
, "robo_miso", 5);
665 if (miso
== GPIO_PIN_NOTDEFINED
) {
666 ET_ERROR(("robo_attach: robo_miso gpio fail: GPIO 5 in use"));
669 robo
->miso
= 1 << miso
;
670 ET_MSG(("%s: ss %d sck %d mosi %d miso %d\n", __FUNCTION__
,
671 ss
, sck
, mosi
, miso
));
676 ASSERT(robo
->ops
->write_reg
);
677 ASSERT(robo
->ops
->read_reg
);
678 ASSERT((robo
->devid
== DEVID5325
) ||
679 (robo
->devid
== DEVID5395
) ||
680 (robo
->devid
== DEVID5397
) ||
681 (robo
->devid
== DEVID5398
));
686 bcm_robo_detach(robo
);
690 /* Release access to the RoboSwitch */
692 bcm_robo_detach(robo_info_t
*robo
)
694 MFREE(sb_osh(robo
->sbh
), robo
, sizeof(robo_info_t
));
697 /* Enable the device and set it to a known good state */
699 bcm_robo_enable_device(robo_info_t
*robo
)
701 uint8 reg_offset
, reg_val
;
704 /* Enable management interface access */
705 if (robo
->ops
->enable_mgmtif
)
706 robo
->ops
->enable_mgmtif(robo
);
708 if (robo
->devid
== DEVID5398
) {
709 /* Disable unused ports: port 6 and 7 */
710 for (reg_offset
= REG_CTRL_PORT6
; reg_offset
<= REG_CTRL_PORT7
; reg_offset
++) {
711 /* Set bits [1:0] to disable RX and TX */
713 robo
->ops
->write_reg(robo
, PAGE_CTRL
, reg_offset
, ®_val
,
718 if (robo
->devid
== DEVID5325
) {
719 /* Must put the switch into Reverse MII mode! */
721 /* MII port state override (page 0 register 14) */
722 robo
->ops
->read_reg(robo
, PAGE_CTRL
, REG_CTRL_MIIPO
, ®_val
, sizeof(reg_val
));
724 /* Bit 4 enables reverse MII mode */
725 if (!(reg_val
& (1 << 4))) {
728 robo
->ops
->write_reg(robo
, PAGE_CTRL
, REG_CTRL_MIIPO
, ®_val
,
732 robo
->ops
->read_reg(robo
, PAGE_CTRL
, REG_CTRL_MIIPO
, ®_val
,
734 if (!(reg_val
& (1 << 4))) {
735 ET_ERROR(("robo_enable_device: enabling RvMII mode failed\n"));
741 /* Disable management interface access */
742 if (robo
->ops
->disable_mgmtif
)
743 robo
->ops
->disable_mgmtif(robo
);
749 #define FLAG_TAGGED 't' /* output tagged (external ports only) */
750 #define FLAG_UNTAG 'u' /* input & output untagged (CPU port only, for OS (linux, ...) */
751 #define FLAG_LAN '*' /* input & output untagged (CPU port only, for CFE */
753 /* port descriptor */
755 uint32 untag
; /* untag enable bit (Page 0x05 Address 0x63-0x66 Bit[17:9]) */
756 uint32 member
; /* vlan member bit (Page 0x05 Address 0x63-0x66 Bit[7:0]) */
757 uint8 ptagr
; /* port tag register address (Page 0x34 Address 0x10-0x1F) */
758 uint8 cpu
; /* is this cpu port? */
761 pdesc_t pdesc97
[] = {
762 /* 5395/5397/5398 is 0 ~ 7. port 8 is IMP port. */
763 /* port 0 */ {1 << 9, 1 << 0, REG_VLAN_PTAG0
, 0},
764 /* port 1 */ {1 << 10, 1 << 1, REG_VLAN_PTAG1
, 0},
765 /* port 2 */ {1 << 11, 1 << 2, REG_VLAN_PTAG2
, 0},
766 /* port 3 */ {1 << 12, 1 << 3, REG_VLAN_PTAG3
, 0},
767 /* port 4 */ {1 << 13, 1 << 4, REG_VLAN_PTAG4
, 0},
768 /* port 5 */ {1 << 14, 1 << 5, REG_VLAN_PTAG5
, 0},
769 /* port 6 */ {1 << 15, 1 << 6, REG_VLAN_PTAG6
, 0},
770 /* port 7 */ {1 << 16, 1 << 7, REG_VLAN_PTAG7
, 0},
771 /* mii port */ {1 << 17, 1 << 8, REG_VLAN_PTAG8
, 1},
774 pdesc_t pdesc25
[] = {
775 /* port 0 */ {1 << 6, 1 << 0, REG_VLAN_PTAG0
, 0},
776 /* port 1 */ {1 << 7, 1 << 1, REG_VLAN_PTAG1
, 0},
777 /* port 2 */ {1 << 8, 1 << 2, REG_VLAN_PTAG2
, 0},
778 /* port 3 */ {1 << 9, 1 << 3, REG_VLAN_PTAG3
, 0},
779 /* port 4 */ {1 << 10, 1 << 4, REG_VLAN_PTAG4
, 0},
780 /* mii port */ {1 << 11, 1 << 5, REG_VLAN_PTAG5
, 1},
783 /* Configure the VLANs */
785 bcm_robo_config_vlan(robo_info_t
*robo
, uint8
*mac_addr
)
793 uint8 arl_entry
[8] = { 0 }, arl_entry1
[8] = { 0 };
795 /* Enable management interface access */
796 if (robo
->ops
->enable_mgmtif
)
797 robo
->ops
->enable_mgmtif(robo
);
799 /* setup global vlan configuration */
800 /* VLAN Control 0 Register (Page 0x34, Address 0) */
801 val8
= ((1 << 7) | /* enable 802.1Q VLAN */
802 (3 << 5)); /* individual VLAN learning mode */
803 robo
->ops
->write_reg(robo
, PAGE_VLAN
, REG_VLAN_CTRL0
, &val8
, sizeof(val8
));
805 /* VLAN Control 1 Register (Page 0x34, Address 1) */
806 val8
= ((1 << 2) | /* enable RSV multicast V Fwdmap */
807 (1 << 3)); /* enable RSV multicast V Untagmap */
808 if (robo
->devid
== DEVID5325
)
809 val8
|= (1 << 1); /* enable RSV multicast V Tagging */
810 robo
->ops
->write_reg(robo
, PAGE_VLAN
, REG_VLAN_CTRL1
, &val8
, sizeof(val8
));
812 arl_entry
[0] = mac_addr
[5];
813 arl_entry
[1] = mac_addr
[4];
814 arl_entry
[2] = mac_addr
[3];
815 arl_entry
[3] = mac_addr
[2];
816 arl_entry
[4] = mac_addr
[1];
817 arl_entry
[5] = mac_addr
[0];
819 if (robo
->devid
== DEVID5325
) {
820 /* Init the entry 1 of the bin */
821 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_ARL_E1
, \
822 arl_entry1
, sizeof(arl_entry1
));
823 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_VID_E1
, \
826 /* Init the entry 0 of the bin */
827 arl_entry
[6] = 0x8; /* Port Id: MII */
828 arl_entry
[7] = 0xc0; /* Static Entry, Valid */
830 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_ARL_E0
, \
831 arl_entry
, sizeof(arl_entry
));
832 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_MINDX
, \
833 arl_entry
, ETHER_ADDR_LEN
);
835 /* VLAN Control 4 Register (Page 0x34, Address 4) */
836 val8
= (1 << 6); /* drop frame with VID violation */
837 robo
->ops
->write_reg(robo
, PAGE_VLAN
, REG_VLAN_CTRL4
, &val8
, sizeof(val8
));
839 /* VLAN Control 5 Register (Page 0x34, Address 5) */
840 val8
= (1 << 3); /* drop frame when miss V table */
841 robo
->ops
->write_reg(robo
, PAGE_VLAN
, REG_VLAN_CTRL5
, &val8
, sizeof(val8
));
844 pdescsz
= sizeof(pdesc25
) / sizeof(pdesc_t
);
846 /* Initialize the MAC Addr Index Register */
847 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_MINDX
, \
848 arl_entry
, ETHER_ADDR_LEN
);
851 pdescsz
= sizeof(pdesc97
) / sizeof(pdesc_t
);
854 vid0
= getintvar(robo
->vars
, "vlan0tag");
856 /* setup each vlan. max. 16 vlans. */
857 /* force vlan id to be equal to vlan number */
858 for (vid
= 0; vid
< VLAN_NUMVLANS
; vid
++) {
859 char vlanports
[] = "vlanXXXXports";
860 char port
[] = "XXXX", *ports
, *next
, *cur
;
865 /* no members if VLAN id is out of limitation */
866 if (vid
> VLAN_MAXVID
)
869 /* get vlan member ports from nvram */
870 sprintf(vlanports
, "vlan%dports", vid
);
871 ports
= getvar(robo
->vars
, vlanports
);
873 /* In 539x vid == 0 us invalid?? */
874 if ((robo
->devid
!= DEVID5325
) && (vid
== 0)) {
876 ET_ERROR(("VID 0 is set in nvram, Ignoring\n"));
880 /* disable this vlan if not defined */
885 * setup each port in the vlan. cpu port needs special handing
886 * (with or without output tagging) to support linux/pmon/cfe.
888 for (cur
= ports
; cur
; cur
= next
) {
889 /* tokenize the port list */
892 next
= bcmstrstr(cur
, " ");
893 len
= next
? next
- cur
: strlen(cur
);
896 if (len
> sizeof(port
) - 1)
897 len
= sizeof(port
) - 1;
898 strncpy(port
, cur
, len
);
901 /* make sure port # is within the range */
902 pid
= bcm_atoi(port
);
903 if (pid
>= pdescsz
) {
904 ET_ERROR(("robo_config_vlan: port %d in vlan%dports is out "
905 "of range[0-%d]\n", pid
, vid
, pdescsz
));
909 /* build VLAN registers values */
911 if ((!pdesc
[pid
].cpu
&& !strchr(port
, FLAG_TAGGED
)) ||
912 (pdesc
[pid
].cpu
&& strchr(port
, FLAG_UNTAG
)))
914 untag
|= pdesc
[pid
].untag
;
916 member
|= pdesc
[pid
].member
;
918 /* set port tag - applies to untagged ingress frames */
919 /* Default Port Tag Register (Page 0x34, Address 0x10-0x1D) */
923 #define FL FLAG_UNTAG
925 if ((!pdesc
[pid
].cpu
&& !strchr(port
, FLAG_TAGGED
)) ||
927 val16
= ((0 << 13) | /* priority - always 0 */
928 vid0
| vid
); /* vlan id */
929 robo
->ops
->write_reg(robo
, PAGE_VLAN
, pdesc
[pid
].ptagr
,
930 &val16
, sizeof(val16
));
934 /* Add static ARL entries */
935 if (robo
->devid
== DEVID5325
) {
937 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_VID_E0
, \
938 &val8
, sizeof(val8
));
939 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_VINDX
, \
940 &val8
, sizeof(val8
));
942 /* Write the entry */
944 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_CTRL
, \
945 &val8
, sizeof(val8
));
946 /* Wait for write to complete */
947 SPINWAIT((robo
->ops
->read_reg(robo
, PAGE_VTBL
, REG_VTBL_CTRL
, \
948 &val8
, sizeof(val8
)), ((val8
& 0x80) != 0)),
951 /* Set the VLAN Id in VLAN ID Index Register */
953 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_VINDX
, \
954 &val8
, sizeof(val8
));
956 /* Set the MAC addr and VLAN Id in ARL Table MAC/VID Entry 0
961 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_ARL_E0
, \
962 arl_entry
, sizeof(arl_entry
));
964 /* Set the Static bit , Valid bit and Port ID fields in
965 * ARL Table Data Entry 0 Register
968 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_DAT_E0
, \
969 &val16
, sizeof(val16
));
971 /* Clear the ARL_R/W bit and set the START/DONE bit in
972 * the ARL Read/Write Control Register.
975 robo
->ops
->write_reg(robo
, PAGE_VTBL
, REG_VTBL_CTRL
, \
976 &val8
, sizeof(val8
));
977 /* Wait for write to complete */
978 SPINWAIT((robo
->ops
->read_reg(robo
, PAGE_VTBL
, REG_VTBL_CTRL
, \
979 &val8
, sizeof(val8
)), ((val8
& 0x80) != 0)),
984 /* setup VLAN ID and VLAN memberships */
986 val32
= (untag
| /* untag enable */
987 member
); /* vlan members */
988 if (sb_chip(robo
->sbh
) == BCM5365_CHIP_ID
)
990 /* VLAN Write Register (Page 0x34, Address 0x0A) */
991 val32
= ((1 << 14) | /* valid write */
992 (untag
<< 1) | /* untag enable */
993 member
); /* vlan members */
994 robo
->ops
->write_reg(robo
, PAGE_VLAN
, REG_VLAN_WRITE_5365
, &val32
,
996 /* VLAN Table Access Register (Page 0x34, Address 0x08) */
997 val16
= ((1 << 13) | /* start command */
998 (1 << 12) | /* write state */
999 vid0
| vid
); /* vlan id */
1000 robo
->ops
->write_reg(robo
, PAGE_VLAN
, REG_VLAN_ACCESS_5365
, &val16
,
1002 } else if (robo
->devid
== DEVID5325
) {
1003 val32
|= ((1 << 20) | /* valid write */
1004 ((vid0
>> 4) << 12)); /* vlan id bit[11:4] */
1005 /* VLAN Write Register (Page 0x34, Address 0x08-0x0B) */
1006 robo
->ops
->write_reg(robo
, PAGE_VLAN
, REG_VLAN_WRITE
, &val32
,
1008 /* VLAN Table Access Register (Page 0x34, Address 0x06-0x07) */
1009 val16
= ((1 << 13) | /* start command */
1010 (1 << 12) | /* write state */
1011 vid0
| vid
); /* vlan id */
1012 robo
->ops
->write_reg(robo
, PAGE_VLAN
, REG_VLAN_ACCESS
, &val16
,
1015 uint8 vtble
, vtbli
, vtbla
;
1017 if (robo
->devid
== DEVID5395
) {
1018 vtble
= REG_VTBL_ENTRY_5395
;
1019 vtbli
= REG_VTBL_INDX_5395
;
1020 vtbla
= REG_VTBL_ACCESS_5395
;
1022 vtble
= REG_VTBL_ENTRY
;
1023 vtbli
= REG_VTBL_INDX
;
1024 vtbla
= REG_VTBL_ACCESS
;
1027 /* VLAN Table Entry Register (Page 0x05, Address 0x63-0x66/0x83-0x86) */
1028 robo
->ops
->write_reg(robo
, PAGE_VTBL
, vtble
, &val32
,
1030 /* VLAN Table Address Index Reg (Page 0x05, Address 0x61-0x62/0x81-0x82) */
1031 val16
= vid0
| vid
; /* vlan id */
1032 robo
->ops
->write_reg(robo
, PAGE_VTBL
, vtbli
, &val16
,
1035 /* VLAN Table Access Register (Page 0x34, Address 0x60/0x80) */
1036 val8
= ((1 << 7) | /* start command */
1038 robo
->ops
->write_reg(robo
, PAGE_VTBL
, vtbla
, &val8
,
1043 if (robo
->devid
== DEVID5325
) {
1044 /* setup priority mapping - applies to tagged ingress frames */
1045 /* Priority Re-map Register (Page 0x34, Address 0x20-0x23) */
1046 val32
= ((0 << 0) | /* 0 -> 0 */
1047 (1 << 3) | /* 1 -> 1 */
1048 (2 << 6) | /* 2 -> 2 */
1049 (3 << 9) | /* 3 -> 3 */
1050 (4 << 12) | /* 4 -> 4 */
1051 (5 << 15) | /* 5 -> 5 */
1052 (6 << 18) | /* 6 -> 6 */
1053 (7 << 21)); /* 7 -> 7 */
1054 robo
->ops
->write_reg(robo
, PAGE_VLAN
, REG_VLAN_PMAP
, &val32
, sizeof(val32
));
1057 /* Disable management interface access */
1058 if (robo
->ops
->disable_mgmtif
)
1059 robo
->ops
->disable_mgmtif(robo
);
1064 /* Enable switching/forwarding */
1066 bcm_robo_enable_switch(robo_info_t
*robo
)
1068 int i
, max_port_ind
, ret
= 0;
1071 /* Enable management interface access */
1072 if (robo
->ops
->enable_mgmtif
)
1073 robo
->ops
->enable_mgmtif(robo
);
1075 /* Switch Mode register (Page 0, Address 0x0B) */
1076 robo
->ops
->read_reg(robo
, PAGE_CTRL
, REG_CTRL_MODE
, &val8
, sizeof(val8
));
1078 /* Bit 1 enables switching/forwarding */
1079 if (!(val8
& (1 << 1))) {
1080 /* Set unmanaged mode */
1081 val8
&= (~(1 << 0));
1083 /* Enable forwarding */
1085 robo
->ops
->write_reg(robo
, PAGE_CTRL
, REG_CTRL_MODE
, &val8
, sizeof(val8
));
1088 robo
->ops
->read_reg(robo
, PAGE_CTRL
, REG_CTRL_MODE
, &val8
, sizeof(val8
));
1089 if (!(val8
& (1 << 1))) {
1090 ET_ERROR(("robo_enable_switch: enabling forwarding failed\n"));
1094 /* No spanning tree for unmanaged mode */
1096 max_port_ind
= ((robo
->devid
== DEVID5398
) ? REG_CTRL_PORT7
: REG_CTRL_PORT4
);
1097 for (i
= REG_CTRL_PORT0
; i
<= max_port_ind
; i
++) {
1098 robo
->ops
->write_reg(robo
, PAGE_CTRL
, i
, &val8
, sizeof(val8
));
1102 /* Enable WAN port (#0) on the asus wl-500g deluxe boxes */
1103 if (sb_chip(robo
->sbh
) == BCM5365_CHIP_ID
) {
1105 robo
->ops
->write_reg(robo
, PAGE_CTRL
, REG_CTRL_PORT0
, &val8
, sizeof(val8
));
1108 /* Disable management interface access */
1109 if (robo
->ops
->disable_mgmtif
)
1110 robo
->ops
->disable_mgmtif(robo
);