release/src/linux/linux/arch/mips/kernel/proc.c

   1 /*
   2  *  linux/arch/mips/kernel/proc.c
   3  *
   4  *  Copyright (C) 1995, 1996, 2001  Ralf Baechle
   5  *  Copyright (C) 2001  MIPS Technologies, Inc.
   6  */
   7 #include <linux/config.h>
   8 #include <linux/delay.h>
   9 #include <linux/kernel.h>
  10 #include <linux/sched.h>
  11 #include <linux/seq_file.h>
  12 #include <asm/bootinfo.h>
  13 #include <asm/cpu.h>
  14 #include <asm/mipsregs.h>
  15 #include <asm/processor.h>
  16 #include <asm/watch.h>
  17
  18 unsigned int vced_count, vcei_count;
  19 extern int bcm947xx_cpu_clk; //Tomato RAF features
  20
  21 #ifndef CONFIG_CPU_HAS_LLSC
  22 unsigned long ll_ops, sc_ops;
  23 #endif
  24
  25 extern unsigned long unaligned_instructions;
  26
  27 static const char *cpu_name[] = {
  28         [CPU_UNKNOWN]   "unknown",
  29         [CPU_R2000]     "R2000",
  30         [CPU_R3000]     "R3000",
  31         [CPU_R3000A]    "R3000A",
  32         [CPU_R3041]     "R3041",
  33         [CPU_R3051]     "R3051",
  34         [CPU_R3052]     "R3052",
  35         [CPU_R3081]     "R3081",
  36         [CPU_R3081E]    "R3081E",
  37         [CPU_R4000PC]   "R4000PC",
  38         [CPU_R4000SC]   "R4000SC",
  39         [CPU_R4000MC]   "R4000MC",
  40         [CPU_R4200]     "R4200",
  41         [CPU_R4400PC]   "R4400PC",
  42         [CPU_R4400SC]   "R4400SC",
  43         [CPU_R4400MC]   "R4400MC",
  44         [CPU_R4600]     "R4600",
  45         [CPU_R6000]     "R6000",
  46         [CPU_R6000A]    "R6000A",
  47         [CPU_R8000]     "R8000",
  48         [CPU_R10000]    "R10000",
  49         [CPU_R12000]    "R12000",
  50         [CPU_R4300]     "R4300",
  51         [CPU_R4650]     "R4650",
  52         [CPU_R4700]     "R4700",
  53         [CPU_R5000]     "R5000",
  54         [CPU_R5000A]    "R5000A",
  55         [CPU_R4640]     "R4640",
  56         [CPU_NEVADA]    "Nevada",
  57         [CPU_RM7000]    "RM7000",
  58         [CPU_R5432]     "R5432",
  59         [CPU_4KC]       "MIPS 4Kc",
  60         [CPU_5KC]       "MIPS 5Kc",
  61         [CPU_R4310]     "R4310",
  62         [CPU_SB1]       "SiByte SB1",
  63         [CPU_TX3912]    "TX3912",
  64         [CPU_TX3922]    "TX3922",
  65         [CPU_TX3927]    "TX3927",
  66         [CPU_AU1000]    "Au1000",
  67         [CPU_4KEC]      "MIPS 4KEc",
  68         [CPU_4KSC]      "MIPS 4KSc",
  69         [CPU_VR41XX]    "NEC Vr41xx",
  70         [CPU_R5500]     "R5500",
  71         [CPU_TX49XX]    "TX49xx",
  72         [CPU_AU1500]    "Au1500",
  73         [CPU_20KC]      "MIPS 20Kc",
  74         [CPU_VR4111]    "NEC VR4111",
  75         [CPU_VR4121]    "NEC VR4121",
  76         [CPU_VR4122]    "NEC VR4122",
  77         [CPU_VR4131]    "NEC VR4131",
  78         [CPU_VR4181]    "NEC VR4181",
  79         [CPU_VR4181A]   "NEC VR4181A",
  80         [CPU_AU1100]    "Au1100",
  81         [CPU_SR71000]   "Sandcraft SR71000",
  82         [CPU_RM9000]    "RM9000",
  83         [CPU_25KF]      "MIPS 25Kf",
  84         [CPU_VR4133]    "NEC VR4133",
  85         [CPU_AU1550]    "Au1550",
  86         [CPU_24K]       "MIPS 24K",
  87         [CPU_AU1200]    "Au1200",
  88         [CPU_BCM4710]   "BCM4710",
  89         [CPU_BCM3302]   "BCM3302",
  90 };
  91
  92 static int show_cpuinfo(struct seq_file *m, void *v)
  93 {
  94         unsigned int version = current_cpu_data.processor_id;
  95         unsigned int fp_vers = current_cpu_data.fpu_id;
  96         unsigned long n = (unsigned long) v - 1;
  97         char fmt [64];
  98
  99 #ifdef CONFIG_SMP
 100         if (!CPUMASK_TSTB(cpu_online_map, n))
 101                 return 0;
 102 #endif
 103
 104         /*
 105          * For the first processor also print the system type
 106          */
 107         if (n == 0)
 108                 seq_printf(m, "system type\t\t: %s\n", get_system_type());
 109
 110         seq_printf(m, "processor\t\t: %ld\n", n);
 111         sprintf(fmt, "cpu model\t\t: %%s V%%d.%%d%s\n",
 112                 cpu_has_fpu ? "  FPU V%d.%d" : "");
 113         seq_printf(m, fmt, cpu_name[current_cpu_data.cputype <= CPU_LAST ?
 114                                     current_cpu_data.cputype : CPU_UNKNOWN],
 115                                    (version >> 4) & 0x0f, version & 0x0f,
 116                                    (fp_vers >> 4) & 0x0f, fp_vers & 0x0f);
 117         seq_printf(m, "BogoMIPS\t\t: %lu.%02lu\n",
 118                       loops_per_jiffy / (500000/HZ),
 119                       (loops_per_jiffy / (5000/HZ)) % 100);
 120         seq_printf(m, "cpu MHz   \t\t: %d\n", bcm947xx_cpu_clk); //Tomato RAF features
 121         seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
 122         seq_printf(m, "microsecond timers\t: %s\n",
 123                       cpu_has_counter ? "yes" : "no");
 124         seq_printf(m, "tlb_entries\t\t: %d\n", current_cpu_data.tlbsize);
 125         seq_printf(m, "extra interrupt vector\t: %s\n",
 126                       cpu_has_divec ? "yes" : "no");
 127         seq_printf(m, "hardware watchpoint\t: %s\n",
 128                       cpu_has_watch ? "yes" : "no");
 129         seq_printf(m, "ASEs implemented\t:%s%s%s%s%s%s\n",
 130                       cpu_has_mips16 ? " mips16" : "",
 131                       cpu_has_mdmx ? " mdmx" : "",
 132                       cpu_has_mips3d ? " mips3d" : "",
 133                       cpu_has_smartmips ? " smartmips" : "",
 134                       cpu_has_dsp ? " dsp" : "",
 135                       cpu_has_mipsmt ? " mt" : ""
 136                 );
 137
 138         sprintf(fmt, "VCE%%c exceptions\t\t: %s\n",
 139                 cpu_has_vce ? "%u" : "not available");
 140         seq_printf(m, fmt, 'D', vced_count);
 141         seq_printf(m, fmt, 'I', vcei_count);
 142
 143 #ifndef CONFIG_CPU_HAS_LLSC
 144         seq_printf(m, "ll emulations\t\t: %lu\n", ll_ops);
 145         seq_printf(m, "sc emulations\t\t: %lu\n", sc_ops);
 146 #endif
 147
 148         seq_printf(m, "unaligned_instructions\t: %lu\n", unaligned_instructions);
 149
 150 #if defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
 151         seq_printf(m, "dcache hits\t\t: %u\n",
 152                    read_perf_cntr(0));
 153         seq_printf(m, "dcache misses\t\t: %u\n",
 154                    read_perf_cntr(1));
 155         seq_printf(m, "icache hits\t\t: %u\n",
 156                    read_perf_cntr(2));
 157         seq_printf(m, "icache misses\t\t: %u\n",
 158                    read_perf_cntr(3));
 159         seq_printf(m, "instructions\t\t: %u\n",
 160                    read_perf_cntr(4));
 161 #endif
 162
 163         return 0;
 164 }
 165
 166 static void *c_start(struct seq_file *m, loff_t *pos)
 167 {
 168         unsigned long i = *pos;
 169
 170         return i < NR_CPUS ? (void *) (i + 1) : NULL;
 171 }
 172
 173 static void *c_next(struct seq_file *m, void *v, loff_t *pos)
 174 {
 175         ++*pos;
 176         return c_start(m, pos);
 177 }
 178
 179 static void c_stop(struct seq_file *m, void *v)
 180 {
 181 }
 182
 183 struct seq_operations cpuinfo_op = {
 184         .start  = c_start,
 185         .next   = c_next,
 186         .stop   = c_stop,
 187         .show   = show_cpuinfo,
 188 };