release/src-rt/shared/sbutils.c

   1 /*
   2  * Misc utility routines for accessing chip-specific features
   3  * of the SiliconBackplane-based Broadcom chips.
   4  *
   5  * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  14  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  16  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  17  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  * $Id: sbutils.c,v 1.687 2009-11-05 01:06:56 Exp $
  20  */
  21
  22 #include <typedefs.h>
  23 #include <bcmdefs.h>
  24 #include <osl.h>
  25 #include <bcmutils.h>
  26 #include <siutils.h>
  27 #include <bcmdevs.h>
  28 #include <hndsoc.h>
  29 #include <sbchipc.h>
  30 #include <pci_core.h>
  31 #include <pcicfg.h>
  32 #include <sbpcmcia.h>
  33
  34 #include "siutils_priv.h"
  35
  36
  37 /* local prototypes */
  38 static uint _sb_coreidx(si_info_t *sii, uint32 sba);
  39 static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba,
  40                      uint ncores);
  41 static uint32 _sb_coresba(si_info_t *sii);
  42 static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
  43
  44 #define SET_SBREG(sii, r, mask, val)    \
  45                 W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
  46 #define REGS2SB(va)     (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
  47
  48 /* sonicsrev */
  49 #define SONICS_2_2      (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
  50 #define SONICS_2_3      (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
  51
  52 #define R_SBREG(sii, sbr)       sb_read_sbreg((sii), (sbr))
  53 #define W_SBREG(sii, sbr, v)    sb_write_sbreg((sii), (sbr), (v))
  54 #define AND_SBREG(sii, sbr, v)  W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) & (v)))
  55 #define OR_SBREG(sii, sbr, v)   W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v)))
  56
  57 static uint32
  58 sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr)
  59 {
  60         uint8 tmp;
  61         uint32 val, intr_val = 0;
  62
  63
  64         /*
  65          * compact flash only has 11 bits address, while we needs 12 bits address.
  66          * MEM_SEG will be OR'd with other 11 bits address in hardware,
  67          * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
  68          * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
  69          */
  70         if (PCMCIA(sii)) {
  71                 INTR_OFF(sii, intr_val);
  72                 tmp = 1;
  73                 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
  74                 sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
  75         }
  76
  77         val = R_REG(sii->osh, sbr);
  78
  79         if (PCMCIA(sii)) {
  80                 tmp = 0;
  81                 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
  82                 INTR_RESTORE(sii, intr_val);
  83         }
  84
  85         return (val);
  86 }
  87
  88 static void
  89 sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v)
  90 {
  91         uint8 tmp;
  92         volatile uint32 dummy;
  93         uint32 intr_val = 0;
  94
  95
  96         /*
  97          * compact flash only has 11 bits address, while we needs 12 bits address.
  98          * MEM_SEG will be OR'd with other 11 bits address in hardware,
  99          * so we program MEM_SEG with 12th bit when necessary(access sb regsiters).
 100          * For normal PCMCIA bus(CFTable_regwinsz > 2k), do nothing special
 101          */
 102         if (PCMCIA(sii)) {
 103                 INTR_OFF(sii, intr_val);
 104                 tmp = 1;
 105                 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
 106                 sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */
 107         }
 108
 109         if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {
 110 #ifdef IL_BIGENDIAN
 111                 dummy = R_REG(sii->osh, sbr);
 112                 W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
 113                 dummy = R_REG(sii->osh, sbr);
 114                 W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
 115 #else
 116                 dummy = R_REG(sii->osh, sbr);
 117                 W_REG(sii->osh, (volatile uint16 *)sbr, (uint16)(v & 0xffff));
 118                 dummy = R_REG(sii->osh, sbr);
 119                 W_REG(sii->osh, ((volatile uint16 *)sbr + 1), (uint16)((v >> 16) & 0xffff));
 120 #endif  /* IL_BIGENDIAN */
 121         } else
 122                 W_REG(sii->osh, sbr, v);
 123
 124         if (PCMCIA(sii)) {
 125                 tmp = 0;
 126                 OSL_PCMCIA_WRITE_ATTR(sii->osh, MEM_SEG, &tmp, 1);
 127                 INTR_RESTORE(sii, intr_val);
 128         }
 129 }
 130
 131 uint
 132 sb_coreid(si_t *sih)
 133 {
 134         si_info_t *sii;
 135         sbconfig_t *sb;
 136
 137         sii = SI_INFO(sih);
 138         sb = REGS2SB(sii->curmap);
 139
 140         return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
 141 }
 142
 143 uint
 144 sb_intflag(si_t *sih)
 145 {
 146         si_info_t *sii;
 147         void *corereg;
 148         sbconfig_t *sb;
 149         uint origidx, intflag, intr_val = 0;
 150
 151         sii = SI_INFO(sih);
 152
 153         INTR_OFF(sii, intr_val);
 154         origidx = si_coreidx(sih);
 155         corereg = si_setcore(sih, CC_CORE_ID, 0);
 156         ASSERT(corereg != NULL);
 157         sb = REGS2SB(corereg);
 158         intflag = R_SBREG(sii, &sb->sbflagst);
 159         sb_setcoreidx(sih, origidx);
 160         INTR_RESTORE(sii, intr_val);
 161
 162         return intflag;
 163 }
 164
 165 uint
 166 sb_flag(si_t *sih)
 167 {
 168         si_info_t *sii;
 169         sbconfig_t *sb;
 170
 171         sii = SI_INFO(sih);
 172         sb = REGS2SB(sii->curmap);
 173
 174         return R_SBREG(sii, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
 175 }
 176
 177 void
 178 sb_setint(si_t *sih, int siflag)
 179 {
 180         si_info_t *sii;
 181         sbconfig_t *sb;
 182         uint32 vec;
 183
 184         sii = SI_INFO(sih);
 185         sb = REGS2SB(sii->curmap);
 186
 187         if (siflag == -1)
 188                 vec = 0;
 189         else
 190                 vec = 1 << siflag;
 191         W_SBREG(sii, &sb->sbintvec, vec);
 192 }
 193
 194 /* return core index of the core with address 'sba' */
 195 static uint
 196 BCMATTACHFN(_sb_coreidx)(si_info_t *sii, uint32 sba)
 197 {
 198         uint i;
 199
 200         for (i = 0; i < sii->numcores; i ++)
 201                 if (sba == sii->coresba[i])
 202                         return i;
 203         return BADIDX;
 204 }
 205
 206 /* return core address of the current core */
 207 static uint32
 208 BCMATTACHFN(_sb_coresba)(si_info_t *sii)
 209 {
 210         uint32 sbaddr;
 211
 212
 213         switch (BUSTYPE(sii->pub.bustype)) {
 214         case SI_BUS: {
 215                 sbconfig_t *sb = REGS2SB(sii->curmap);
 216                 sbaddr = sb_base(R_SBREG(sii, &sb->sbadmatch0));
 217                 break;
 218         }
 219
 220         case PCI_BUS:
 221                 sbaddr = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32));
 222                 break;
 223
 224         case PCMCIA_BUS: {
 225                 uint8 tmp = 0;
 226                 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);
 227                 sbaddr  = (uint32)tmp << 12;
 228                 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);
 229                 sbaddr |= (uint32)tmp << 16;
 230                 OSL_PCMCIA_READ_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);
 231                 sbaddr |= (uint32)tmp << 24;
 232                 break;
 233         }
 234
 235
 236 #ifdef BCMJTAG
 237         case JTAG_BUS:
 238                 sbaddr = (uint32)(uintptr)sii->curmap;
 239                 break;
 240 #endif
 241
 242         default:
 243                 sbaddr = BADCOREADDR;
 244                 break;
 245         }
 246
 247         return sbaddr;
 248 }
 249
 250 uint
 251 sb_corevendor(si_t *sih)
 252 {
 253         si_info_t *sii;
 254         sbconfig_t *sb;
 255
 256         sii = SI_INFO(sih);
 257         sb = REGS2SB(sii->curmap);
 258
 259         return ((R_SBREG(sii, &sb->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
 260 }
 261
 262 uint
 263 sb_corerev(si_t *sih)
 264 {
 265         si_info_t *sii;
 266         sbconfig_t *sb;
 267         uint sbidh;
 268
 269         sii = SI_INFO(sih);
 270         sb = REGS2SB(sii->curmap);
 271         sbidh = R_SBREG(sii, &sb->sbidhigh);
 272
 273         return (SBCOREREV(sbidh));
 274 }
 275
 276 /* set core-specific control flags */
 277 void
 278 sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val)
 279 {
 280         si_info_t *sii;
 281         sbconfig_t *sb;
 282         uint32 w;
 283
 284         sii = SI_INFO(sih);
 285         sb = REGS2SB(sii->curmap);
 286
 287         ASSERT((val & ~mask) == 0);
 288
 289         /* mask and set */
 290         w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
 291                 (val << SBTML_SICF_SHIFT);
 292         W_SBREG(sii, &sb->sbtmstatelow, w);
 293 }
 294
 295 /* set/clear core-specific control flags */
 296 uint32
 297 sb_core_cflags(si_t *sih, uint32 mask, uint32 val)
 298 {
 299         si_info_t *sii;
 300         sbconfig_t *sb;
 301         uint32 w;
 302
 303         sii = SI_INFO(sih);
 304         sb = REGS2SB(sii->curmap);
 305
 306         ASSERT((val & ~mask) == 0);
 307
 308         /* mask and set */
 309         if (mask || val) {
 310                 w = (R_SBREG(sii, &sb->sbtmstatelow) & ~(mask << SBTML_SICF_SHIFT)) |
 311                         (val << SBTML_SICF_SHIFT);
 312                 W_SBREG(sii, &sb->sbtmstatelow, w);
 313         }
 314
 315         /* return the new value
 316          * for write operation, the following readback ensures the completion of write opration.
 317          */
 318         return (R_SBREG(sii, &sb->sbtmstatelow) >> SBTML_SICF_SHIFT);
 319 }
 320
 321 /* set/clear core-specific status flags */
 322 uint32
 323 sb_core_sflags(si_t *sih, uint32 mask, uint32 val)
 324 {
 325         si_info_t *sii;
 326         sbconfig_t *sb;
 327         uint32 w;
 328
 329         sii = SI_INFO(sih);
 330         sb = REGS2SB(sii->curmap);
 331
 332         ASSERT((val & ~mask) == 0);
 333         ASSERT((mask & ~SISF_CORE_BITS) == 0);
 334
 335         /* mask and set */
 336         if (mask || val) {
 337                 w = (R_SBREG(sii, &sb->sbtmstatehigh) & ~(mask << SBTMH_SISF_SHIFT)) |
 338                         (val << SBTMH_SISF_SHIFT);
 339                 W_SBREG(sii, &sb->sbtmstatehigh, w);
 340         }
 341
 342         /* return the new value */
 343         return (R_SBREG(sii, &sb->sbtmstatehigh) >> SBTMH_SISF_SHIFT);
 344 }
 345
 346 bool
 347 sb_iscoreup(si_t *sih)
 348 {
 349         si_info_t *sii;
 350         sbconfig_t *sb;
 351
 352         sii = SI_INFO(sih);
 353         sb = REGS2SB(sii->curmap);
 354
 355         return ((R_SBREG(sii, &sb->sbtmstatelow) &
 356                  (SBTML_RESET | SBTML_REJ_MASK | (SICF_CLOCK_EN << SBTML_SICF_SHIFT))) ==
 357                 (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
 358 }
 359
 360 /*
 361  * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
 362  * switch back to the original core, and return the new value.
 363  *
 364  * When using the silicon backplane, no fidleing with interrupts or core switches are needed.
 365  *
 366  * Also, when using pci/pcie, we can optimize away the core switching for pci registers
 367  * and (on newer pci cores) chipcommon registers.
 368  */
 369 uint
 370 sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
 371 {
 372         uint origidx = 0;
 373         uint32 *r = NULL;
 374         uint w;
 375         uint intr_val = 0;
 376         bool fast = FALSE;
 377         si_info_t *sii;
 378
 379         sii = SI_INFO(sih);
 380
 381         ASSERT(GOODIDX(coreidx));
 382         ASSERT(regoff < SI_CORE_SIZE);
 383         ASSERT((val & ~mask) == 0);
 384
 385         if (coreidx >= SI_MAXCORES)
 386                 return 0;
 387
 388         if (BUSTYPE(sii->pub.bustype) == SI_BUS) {
 389                 /* If internal bus, we can always get at everything */
 390                 fast = TRUE;
 391                 /* map if does not exist */
 392                 if (!sii->regs[coreidx]) {
 393                         sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
 394                                                     SI_CORE_SIZE);
 395                         ASSERT(GOODREGS(sii->regs[coreidx]));
 396                 }
 397                 r = (uint32 *)((uchar *)sii->regs[coreidx] + regoff);
 398         } else if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
 399                 /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
 400
 401                 if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
 402                         /* Chipc registers are mapped at 12KB */
 403
 404                         fast = TRUE;
 405                         r = (uint32 *)((char *)sii->curmap + PCI_16KB0_CCREGS_OFFSET + regoff);
 406                 } else if (sii->pub.buscoreidx == coreidx) {
 407                         /* pci registers are at either in the last 2KB of an 8KB window
 408                          * or, in pcie and pci rev 13 at 8KB
 409                          */
 410                         fast = TRUE;
 411                         if (SI_FAST(sii))
 412                                 r = (uint32 *)((char *)sii->curmap +
 413                                                PCI_16KB0_PCIREGS_OFFSET + regoff);
 414                         else
 415                                 r = (uint32 *)((char *)sii->curmap +
 416                                                ((regoff >= SBCONFIGOFF) ?
 417                                                 PCI_BAR0_PCISBR_OFFSET : PCI_BAR0_PCIREGS_OFFSET) +
 418                                                regoff);
 419                 }
 420         }
 421
 422         if (!fast) {
 423                 INTR_OFF(sii, intr_val);
 424
 425                 /* save current core index */
 426                 origidx = si_coreidx(&sii->pub);
 427
 428                 /* switch core */
 429                 r = (uint32*) ((uchar*)sb_setcoreidx(&sii->pub, coreidx) + regoff);
 430         }
 431         ASSERT(r != NULL);
 432
 433         /* mask and set */
 434         if (mask || val) {
 435                 if (regoff >= SBCONFIGOFF) {
 436                         w = (R_SBREG(sii, r) & ~mask) | val;
 437                         W_SBREG(sii, r, w);
 438                 } else {
 439                         w = (R_REG(sii->osh, r) & ~mask) | val;
 440                         W_REG(sii->osh, r, w);
 441                 }
 442         }
 443
 444         /* readback */
 445         if (regoff >= SBCONFIGOFF)
 446                 w = R_SBREG(sii, r);
 447         else {
 448                 if ((CHIPID(sii->pub.chip) == BCM5354_CHIP_ID) &&
 449                     (coreidx == SI_CC_IDX) &&
 450                     (regoff == OFFSETOF(chipcregs_t, watchdog))) {
 451                         w = val;
 452                 } else
 453                         w = R_REG(sii->osh, r);
 454         }
 455
 456         if (!fast) {
 457                 /* restore core index */
 458                 if (origidx != coreidx)
 459                         sb_setcoreidx(&sii->pub, origidx);
 460
 461                 INTR_RESTORE(sii, intr_val);
 462         }
 463
 464         return (w);
 465 }
 466
 467 /* Scan the enumeration space to find all cores starting from the given
 468  * bus 'sbba'. Append coreid and other info to the lists in 'si'. 'sba'
 469  * is the default core address at chip POR time and 'regs' is the virtual
 470  * address that the default core is mapped at. 'ncores' is the number of
 471  * cores expected on bus 'sbba'. It returns the total number of cores
 472  * starting from bus 'sbba', inclusive.
 473  */
 474 #define SB_MAXBUSES     2
 475 static uint
 476 BCMATTACHFN(_sb_scan)(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba, uint numcores)
 477 {
 478         uint next;
 479         uint ncc = 0;
 480         uint i;
 481
 482         if (bus >= SB_MAXBUSES) {
 483                 SI_ERROR(("_sb_scan: bus 0x%08x at level %d is too deep to scan\n", sbba, bus));
 484                 return 0;
 485         }
 486         SI_MSG(("_sb_scan: scan bus 0x%08x assume %u cores\n", sbba, numcores));
 487
 488         /* Scan all cores on the bus starting from core 0.
 489          * Core addresses must be contiguous on each bus.
 490          */
 491         for (i = 0, next = sii->numcores; i < numcores && next < SB_BUS_MAXCORES; i++, next++) {
 492                 sii->coresba[next] = sbba + (i * SI_CORE_SIZE);
 493
 494                 /* keep and reuse the initial register mapping */
 495                 if ((BUSTYPE(sii->pub.bustype) == SI_BUS) && (sii->coresba[next] == sba)) {
 496                         SI_VMSG(("_sb_scan: reuse mapped regs %p for core %u\n", regs, next));
 497                         sii->regs[next] = regs;
 498                 }
 499
 500                 /* change core to 'next' and read its coreid */
 501                 sii->curmap = _sb_setcoreidx(sii, next);
 502                 sii->curidx = next;
 503
 504                 sii->coreid[next] = sb_coreid(&sii->pub);
 505
 506                 /* core specific processing... */
 507                 /* chipc provides # cores */
 508                 if (sii->coreid[next] == CC_CORE_ID) {
 509                         chipcregs_t *cc = (chipcregs_t *)sii->curmap;
 510                         uint32 ccrev = sb_corerev(&sii->pub);
 511
 512                         /* determine numcores - this is the total # cores in the chip */
 513                         if (((ccrev == 4) || (ccrev >= 6)))
 514                                 numcores = (R_REG(sii->osh, &cc->chipid) & CID_CC_MASK) >>
 515                                         CID_CC_SHIFT;
 516                         else {
 517                                 /* Older chips */
 518                                 uint chip = CHIPID(sii->pub.chip);
 519
 520                                 if (chip == BCM4306_CHIP_ID)    /* < 4306c0 */
 521                                         numcores = 6;
 522                                 else if (chip == BCM4704_CHIP_ID)
 523                                         numcores = 9;
 524                                 else if (chip == BCM5365_CHIP_ID)
 525                                         numcores = 7;
 526                                 else {
 527                                         SI_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n",
 528                                                   chip));
 529                                         ASSERT(0);
 530                                         numcores = 1;
 531                                 }
 532                         }
 533                         SI_VMSG(("_sb_scan: there are %u cores in the chip %s\n", numcores,
 534                                 sii->pub.issim ? "QT" : ""));
 535                 }
 536                 /* scan bridged SB(s) and add results to the end of the list */
 537                 else if (sii->coreid[next] == OCP_CORE_ID) {
 538                         sbconfig_t *sb = REGS2SB(sii->curmap);
 539                         uint32 nsbba = R_SBREG(sii, &sb->sbadmatch1);
 540                         uint nsbcc;
 541
 542                         sii->numcores = next + 1;
 543
 544                         if ((nsbba & 0xfff00000) != SI_ENUM_BASE)
 545                                 continue;
 546                         nsbba &= 0xfffff000;
 547                         if (_sb_coreidx(sii, nsbba) != BADIDX)
 548                                 continue;
 549
 550                         nsbcc = (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >> 16;
 551                         nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc);
 552                         if (sbba == SI_ENUM_BASE)
 553                                 numcores -= nsbcc;
 554                         ncc += nsbcc;
 555                 }
 556         }
 557
 558         SI_MSG(("_sb_scan: found %u cores on bus 0x%08x\n", i, sbba));
 559
 560         sii->numcores = i + ncc;
 561         return sii->numcores;
 562 }
 563
 564 /* scan the sb enumerated space to identify all cores */
 565 void
 566 BCMATTACHFN(sb_scan)(si_t *sih, void *regs, uint devid)
 567 {
 568         si_info_t *sii;
 569         uint32 origsba;
 570         sbconfig_t *sb;
 571
 572         sii = SI_INFO(sih);
 573         sb = REGS2SB(sii->curmap);
 574
 575         sii->pub.socirev = (R_SBREG(sii, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
 576
 577         /* Save the current core info and validate it later till we know
 578          * for sure what is good and what is bad.
 579          */
 580         origsba = _sb_coresba(sii);
 581
 582         /* scan all SB(s) starting from SI_ENUM_BASE */
 583         sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1);
 584 }
 585
 586 /*
 587  * This function changes logical "focus" to the indicated core;
 588  * must be called with interrupts off.
 589  * Moreover, callers should keep interrupts off during switching out of and back to d11 core
 590  */
 591 void *
 592 sb_setcoreidx(si_t *sih, uint coreidx)
 593 {
 594         si_info_t *sii;
 595
 596         sii = SI_INFO(sih);
 597
 598         if (coreidx >= sii->numcores)
 599                 return (NULL);
 600
 601         /*
 602          * If the user has provided an interrupt mask enabled function,
 603          * then assert interrupts are disabled before switching the core.
 604          */
 605         ASSERT((sii->intrsenabled_fn == NULL) || !(*(sii)->intrsenabled_fn)((sii)->intr_arg));
 606
 607         sii->curmap = _sb_setcoreidx(sii, coreidx);
 608         sii->curidx = coreidx;
 609
 610         return (sii->curmap);
 611 }
 612
 613 /* This function changes the logical "focus" to the indicated core.
 614  * Return the current core's virtual address.
 615  */
 616 static void *
 617 _sb_setcoreidx(si_info_t *sii, uint coreidx)
 618 {
 619         uint32 sbaddr = sii->coresba[coreidx];
 620         void *regs;
 621
 622         switch (BUSTYPE(sii->pub.bustype)) {
 623         case SI_BUS:
 624                 /* map new one */
 625                 if (!sii->regs[coreidx]) {
 626                         sii->regs[coreidx] = REG_MAP(sbaddr, SI_CORE_SIZE);
 627                         ASSERT(GOODREGS(sii->regs[coreidx]));
 628                 }
 629                 regs = sii->regs[coreidx];
 630                 break;
 631
 632         case PCI_BUS:
 633                 /* point bar0 window */
 634                 OSL_PCI_WRITE_CONFIG(sii->osh, PCI_BAR0_WIN, 4, sbaddr);
 635                 regs = sii->curmap;
 636                 break;
 637
 638         case PCMCIA_BUS: {
 639                 uint8 tmp = (sbaddr >> 12) & 0x0f;
 640                 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR0, &tmp, 1);
 641                 tmp = (sbaddr >> 16) & 0xff;
 642                 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR1, &tmp, 1);
 643                 tmp = (sbaddr >> 24) & 0xff;
 644                 OSL_PCMCIA_WRITE_ATTR(sii->osh, PCMCIA_ADDR2, &tmp, 1);
 645                 regs = sii->curmap;
 646                 break;
 647         }
 648
 649 #ifdef BCMJTAG
 650         case JTAG_BUS:
 651                 /* map new one */
 652                 if (!sii->regs[coreidx]) {
 653                         sii->regs[coreidx] = (void *)(uintptr)sbaddr;
 654                         ASSERT(GOODREGS(sii->regs[coreidx]));
 655                 }
 656                 regs = sii->regs[coreidx];
 657                 break;
 658 #endif  /* BCMJTAG */
 659
 660         default:
 661                 ASSERT(0);
 662                 regs = NULL;
 663                 break;
 664         }
 665
 666         return regs;
 667 }
 668
 669 /* Return the address of sbadmatch0/1/2/3 register */
 670 static volatile uint32 *
 671 sb_admatch(si_info_t *sii, uint asidx)
 672 {
 673         sbconfig_t *sb;
 674         volatile uint32 *addrm;
 675
 676         sb = REGS2SB(sii->curmap);
 677
 678         switch (asidx) {
 679         case 0:
 680                 addrm =  &sb->sbadmatch0;
 681                 break;
 682
 683         case 1:
 684                 addrm =  &sb->sbadmatch1;
 685                 break;
 686
 687         case 2:
 688                 addrm =  &sb->sbadmatch2;
 689                 break;
 690
 691         case 3:
 692                 addrm =  &sb->sbadmatch3;
 693                 break;
 694
 695         default:
 696                 SI_ERROR(("%s: Address space index (%d) out of range\n", __FUNCTION__, asidx));
 697                 return 0;
 698         }
 699
 700         return (addrm);
 701 }
 702
 703 /* Return the number of address spaces in current core */
 704 int
 705 sb_numaddrspaces(si_t *sih)
 706 {
 707         si_info_t *sii;
 708         sbconfig_t *sb;
 709
 710         sii = SI_INFO(sih);
 711         sb = REGS2SB(sii->curmap);
 712
 713         /* + 1 because of enumeration space */
 714         return ((R_SBREG(sii, &sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT) + 1;
 715 }
 716
 717 /* Return the address of the nth address space in the current core */
 718 uint32
 719 sb_addrspace(si_t *sih, uint asidx)
 720 {
 721         si_info_t *sii;
 722
 723         sii = SI_INFO(sih);
 724
 725         return (sb_base(R_SBREG(sii, sb_admatch(sii, asidx))));
 726 }
 727
 728 /* Return the size of the nth address space in the current core */
 729 uint32
 730 sb_addrspacesize(si_t *sih, uint asidx)
 731 {
 732         si_info_t *sii;
 733
 734         sii = SI_INFO(sih);
 735
 736         return (sb_size(R_SBREG(sii, sb_admatch(sii, asidx))));
 737 }
 738
 739 #if defined(BCMDBG_ERR) || defined(BCMASSERT_SUPPORT) || defined(BCMDBG_DUMP)
 740 /* traverse all cores to find and clear source of serror */
 741 static void
 742 sb_serr_clear(si_info_t *sii)
 743 {
 744         sbconfig_t *sb;
 745         uint origidx;
 746         uint i, intr_val = 0;
 747         void *corereg = NULL;
 748
 749         INTR_OFF(sii, intr_val);
 750         origidx = si_coreidx(&sii->pub);
 751
 752         for (i = 0; i < sii->numcores; i++) {
 753                 corereg = sb_setcoreidx(&sii->pub, i);
 754                 if (NULL != corereg) {
 755                         sb = REGS2SB(corereg);
 756                         if ((R_SBREG(sii, &sb->sbtmstatehigh)) & SBTMH_SERR) {
 757                                 AND_SBREG(sii, &sb->sbtmstatehigh, ~SBTMH_SERR);
 758                                 SI_ERROR(("sb_serr_clear: SError at core 0x%x\n",
 759                                           sb_coreid(&sii->pub)));
 760                         }
 761                 }
 762         }
 763
 764         sb_setcoreidx(&sii->pub, origidx);
 765         INTR_RESTORE(sii, intr_val);
 766 }
 767
 768 /*
 769  * Check if any inband, outband or timeout errors has happened and clear them.
 770  * Must be called with chip clk on !
 771  */
 772 bool
 773 sb_taclear(si_t *sih, bool details)
 774 {
 775         si_info_t *sii;
 776         sbconfig_t *sb;
 777         uint origidx;
 778         uint intr_val = 0;
 779         bool rc = FALSE;
 780         uint32 inband = 0, serror = 0, timeout = 0;
 781         void *corereg = NULL;
 782         volatile uint32 imstate, tmstate;
 783 #ifdef BCMDBG
 784         bool printed = FALSE;
 785 #endif
 786
 787         sii = SI_INFO(sih);
 788
 789         if (BUSTYPE(sii->pub.bustype) == PCI_BUS) {
 790                 volatile uint32 stcmd;
 791
 792                 /* inband error is Target abort for PCI */
 793                 stcmd = OSL_PCI_READ_CONFIG(sii->osh, PCI_CFG_CMD, sizeof(uint32));
 794                 inband = stcmd & PCI_STAT_TA;
 795                 if (inband) {
 796 #ifdef BCMDBG
 797                         if (details) {
 798                                 SI_ERROR(("\ninband:\n"));
 799                                 si_viewall((void*)sii, FALSE);
 800                                 printed = TRUE;
 801                         }
 802 #endif
 803                         OSL_PCI_WRITE_CONFIG(sii->osh, PCI_CFG_CMD, sizeof(uint32), stcmd);
 804                 }
 805
 806                 /* serror */
 807                 stcmd = OSL_PCI_READ_CONFIG(sii->osh, PCI_INT_STATUS, sizeof(uint32));
 808                 serror = stcmd & PCI_SBIM_STATUS_SERR;
 809                 if (serror) {
 810 #ifdef BCMDBG
 811                         if (details) {
 812                                 SI_ERROR(("\nserror:\n"));
 813                                 if (!printed)
 814                                         si_viewall((void*)sii, FALSE);
 815                                 printed = TRUE;
 816                         }
 817 #endif
 818                         sb_serr_clear(sii);
 819                         OSL_PCI_WRITE_CONFIG(sii->osh, PCI_INT_STATUS, sizeof(uint32), stcmd);
 820                 }
 821
 822                 /* timeout */
 823                 imstate = sb_corereg(sih, sii->pub.buscoreidx,
 824                                      SBCONFIGOFF + OFFSETOF(sbconfig_t, sbimstate), 0, 0);
 825                 if ((imstate != 0xffffffff) && (imstate & (SBIM_IBE | SBIM_TO))) {
 826                         sb_corereg(sih, sii->pub.buscoreidx,
 827                                    SBCONFIGOFF + OFFSETOF(sbconfig_t, sbimstate), ~0,
 828                                    (imstate & ~(SBIM_IBE | SBIM_TO)));
 829                         /* inband = imstate & SBIM_IBE; same as TA above */
 830                         timeout = imstate & SBIM_TO;
 831                         if (timeout) {
 832 #ifdef BCMDBG
 833                                 if (details) {
 834                                         SI_ERROR(("\ntimeout:\n"));
 835                                         if (!printed)
 836                                                 si_viewall((void*)sii, FALSE);
 837                                         printed = TRUE;
 838                                 }
 839 #endif
 840                         }
 841                 }
 842
 843                 if (inband) {
 844                         /* dump errlog for sonics >= 2.3 */
 845                         if (sii->pub.socirev == SONICS_2_2)
 846                                 ;
 847                         else {
 848                                 uint32 imerrlog, imerrloga;
 849                                 imerrlog = sb_corereg(sih, sii->pub.buscoreidx, SBIMERRLOG, 0, 0);
 850                                 if (imerrlog & SBTMEL_EC) {
 851                                         imerrloga = sb_corereg(sih, sii->pub.buscoreidx,
 852                                                                SBIMERRLOGA, 0, 0);
 853                                         /* clear errlog */
 854                                         sb_corereg(sih, sii->pub.buscoreidx, SBIMERRLOG, ~0, 0);
 855                                         SI_ERROR(("sb_taclear: ImErrLog 0x%x, ImErrLogA 0x%x\n",
 856                                                 imerrlog, imerrloga));
 857                                 }
 858                         }
 859                 }
 860
 861
 862         } else if (BUSTYPE(sii->pub.bustype) == PCMCIA_BUS) {
 863
 864                 INTR_OFF(sii, intr_val);
 865                 origidx = si_coreidx(sih);
 866
 867                 corereg = si_setcore(sih, PCMCIA_CORE_ID, 0);
 868                 if (NULL != corereg) {
 869                         sb = REGS2SB(corereg);
 870
 871                         imstate = R_SBREG(sii, &sb->sbimstate);
 872                         /* handle surprise removal */
 873                         if ((imstate != 0xffffffff) && (imstate & (SBIM_IBE | SBIM_TO))) {
 874                                 AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
 875                                 inband = imstate & SBIM_IBE;
 876                                 timeout = imstate & SBIM_TO;
 877                         }
 878                         tmstate = R_SBREG(sii, &sb->sbtmstatehigh);
 879                         if ((tmstate != 0xffffffff) && (tmstate & SBTMH_INT_STATUS)) {
 880                                 if (!inband) {
 881                                         serror = 1;
 882                                         sb_serr_clear(sii);
 883                                 }
 884                                 OR_SBREG(sii, &sb->sbtmstatelow, SBTML_INT_ACK);
 885                                 AND_SBREG(sii, &sb->sbtmstatelow, ~SBTML_INT_ACK);
 886                         }
 887                 }
 888                 sb_setcoreidx(sih, origidx);
 889                 INTR_RESTORE(sii, intr_val);
 890
 891         }
 892
 893
 894         if (inband | timeout | serror) {
 895                 rc = TRUE;
 896                 SI_ERROR(("sb_taclear: inband 0x%x, serror 0x%x, timeout 0x%x!\n",
 897                           inband, serror, timeout));
 898         }
 899
 900         return (rc);
 901 }
 902 #endif
 903
 904 /* do buffered registers update */
 905 void
 906 sb_commit(si_t *sih)
 907 {
 908         si_info_t *sii;
 909         uint origidx;
 910         uint intr_val = 0;
 911
 912         sii = SI_INFO(sih);
 913
 914         origidx = sii->curidx;
 915         ASSERT(GOODIDX(origidx));
 916
 917         INTR_OFF(sii, intr_val);
 918
 919         /* switch over to chipcommon core if there is one, else use pci */
 920         if (sii->pub.ccrev != NOREV) {
 921                 chipcregs_t *ccregs = (chipcregs_t *)si_setcore(sih, CC_CORE_ID, 0);
 922
 923                 /* do the buffer registers update */
 924                 W_REG(sii->osh, &ccregs->broadcastaddress, SB_COMMIT);
 925                 W_REG(sii->osh, &ccregs->broadcastdata, 0x0);
 926         } else if (PCI(sii)) {
 927                 sbpciregs_t *pciregs = (sbpciregs_t *)si_setcore(sih, PCI_CORE_ID, 0);
 928
 929                 /* do the buffer registers update */
 930                 W_REG(sii->osh, &pciregs->bcastaddr, SB_COMMIT);
 931                 W_REG(sii->osh, &pciregs->bcastdata, 0x0);
 932         } else
 933                 ASSERT(0);
 934
 935         /* restore core index */
 936         sb_setcoreidx(sih, origidx);
 937         INTR_RESTORE(sii, intr_val);
 938 }
 939
 940 void
 941 sb_core_disable(si_t *sih, uint32 bits)
 942 {
 943         si_info_t *sii;
 944         volatile uint32 dummy;
 945         sbconfig_t *sb;
 946
 947         sii = SI_INFO(sih);
 948
 949         ASSERT(GOODREGS(sii->curmap));
 950         sb = REGS2SB(sii->curmap);
 951
 952         /* if core is already in reset, just return */
 953         if (R_SBREG(sii, &sb->sbtmstatelow) & SBTML_RESET)
 954                 return;
 955
 956         /* if clocks are not enabled, put into reset and return */
 957         if ((R_SBREG(sii, &sb->sbtmstatelow) & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) == 0)
 958                 goto disable;
 959
 960         /* set target reject and spin until busy is clear (preserve core-specific bits) */
 961         OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);
 962         dummy = R_SBREG(sii, &sb->sbtmstatelow);
 963         OSL_DELAY(1);
 964         SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
 965         if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)
 966                 SI_ERROR(("%s: target state still busy\n", __FUNCTION__));
 967
 968         if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {
 969                 OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);
 970                 dummy = R_SBREG(sii, &sb->sbimstate);
 971                 OSL_DELAY(1);
 972                 SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);
 973         }
 974
 975         /* set reset and reject while enabling the clocks */
 976         W_SBREG(sii, &sb->sbtmstatelow,
 977                 (((bits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
 978                  SBTML_REJ | SBTML_RESET));
 979         dummy = R_SBREG(sii, &sb->sbtmstatelow);
 980         OSL_DELAY(10);
 981
 982         /* don't forget to clear the initiator reject bit */
 983         if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)
 984                 AND_SBREG(sii, &sb->sbimstate, ~SBIM_RJ);
 985
 986 disable:
 987         /* leave reset and reject asserted */
 988         W_SBREG(sii, &sb->sbtmstatelow, ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));
 989         OSL_DELAY(1);
 990 }
 991
 992 /* reset and re-enable a core
 993  * inputs:
 994  * bits - core specific bits that are set during and after reset sequence
 995  * resetbits - core specific bits that are set only during reset sequence
 996  */
 997 void
 998 sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits)
 999 {
1000         si_info_t *sii;
1001         sbconfig_t *sb;
1002         volatile uint32 dummy;
1003
1004         sii = SI_INFO(sih);
1005         ASSERT(GOODREGS(sii->curmap));
1006         sb = REGS2SB(sii->curmap);
1007
1008         /*
1009          * Must do the disable sequence first to work for arbitrary current core state.
1010          */
1011         sb_core_disable(sih, (bits | resetbits));
1012
1013         /*
1014          * Now do the initialization sequence.
1015          */
1016
1017         /* set reset while enabling the clock and forcing them on throughout the core */
1018         W_SBREG(sii, &sb->sbtmstatelow,
1019                 (((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
1020                  SBTML_RESET));
1021         dummy = R_SBREG(sii, &sb->sbtmstatelow);
1022         OSL_DELAY(1);
1023
1024         if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR) {
1025                 W_SBREG(sii, &sb->sbtmstatehigh, 0);
1026         }
1027         if ((dummy = R_SBREG(sii, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
1028                 AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
1029         }
1030
1031         /* clear reset and allow it to propagate throughout the core */
1032         W_SBREG(sii, &sb->sbtmstatelow,
1033                 ((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
1034         dummy = R_SBREG(sii, &sb->sbtmstatelow);
1035         OSL_DELAY(1);
1036
1037         /* leave clock enabled */
1038         W_SBREG(sii, &sb->sbtmstatelow, ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
1039         dummy = R_SBREG(sii, &sb->sbtmstatelow);
1040         OSL_DELAY(1);
1041 }
1042
1043 /*
1044  * Set the initiator timeout for the "master core".
1045  * The master core is defined to be the core in control
1046  * of the chip and so it issues accesses to non-memory
1047  * locations (Because of dma *any* core can access memeory).
1048  *
1049  * The routine uses the bus to decide who is the master:
1050  *      SI_BUS => mips
1051  *      JTAG_BUS => chipc
1052  *      PCI_BUS => pci or pcie
1053  *      PCMCIA_BUS => pcmcia
1054  *      SDIO_BUS => pcmcia
1055  *
1056  * This routine exists so callers can disable initiator
1057  * timeouts so accesses to very slow devices like otp
1058  * won't cause an abort. The routine allows arbitrary
1059  * settings of the service and request timeouts, though.
1060  *
1061  * Returns the timeout state before changing it or -1
1062  * on error.
1063  */
1064
1065 #define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
1066
1067 uint32
1068 sb_set_initiator_to(si_t *sih, uint32 to, uint idx)
1069 {
1070         si_info_t *sii;
1071         uint origidx;
1072         uint intr_val = 0;
1073         uint32 tmp, ret = 0xffffffff;
1074         sbconfig_t *sb;
1075
1076         sii = SI_INFO(sih);
1077
1078         if ((to & ~TO_MASK) != 0)
1079                 return ret;
1080
1081         /* Figure out the master core */
1082         if (idx == BADIDX) {
1083                 switch (BUSTYPE(sii->pub.bustype)) {
1084                 case PCI_BUS:
1085                         idx = sii->pub.buscoreidx;
1086                         break;
1087                 case JTAG_BUS:
1088                         idx = SI_CC_IDX;
1089                         break;
1090                 case PCMCIA_BUS:
1091                         idx = si_findcoreidx(sih, PCMCIA_CORE_ID, 0);
1092                         break;
1093                 case SI_BUS:
1094                         idx = si_findcoreidx(sih, MIPS33_CORE_ID, 0);
1095                         break;
1096                 default:
1097                         ASSERT(0);
1098                 }
1099                 if (idx == BADIDX)
1100                         return ret;
1101         }
1102
1103         INTR_OFF(sii, intr_val);
1104         origidx = si_coreidx(sih);
1105
1106         sb = REGS2SB(sb_setcoreidx(sih, idx));
1107
1108         tmp = R_SBREG(sii, &sb->sbimconfiglow);
1109         ret = tmp & TO_MASK;
1110         W_SBREG(sii, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
1111
1112         sb_commit(sih);
1113         sb_setcoreidx(sih, origidx);
1114         INTR_RESTORE(sii, intr_val);
1115         return ret;
1116 }
1117
1118 uint32
1119 sb_base(uint32 admatch)
1120 {
1121         uint32 base;
1122         uint type;
1123
1124         type = admatch & SBAM_TYPE_MASK;
1125         ASSERT(type < 3);
1126
1127         base = 0;
1128
1129         if (type == 0) {
1130                 base = admatch & SBAM_BASE0_MASK;
1131         } else if (type == 1) {
1132                 ASSERT(!(admatch & SBAM_ADNEG));        /* neg not supported */
1133                 base = admatch & SBAM_BASE1_MASK;
1134         } else if (type == 2) {
1135                 ASSERT(!(admatch & SBAM_ADNEG));        /* neg not supported */
1136                 base = admatch & SBAM_BASE2_MASK;
1137         }
1138
1139         return (base);
1140 }
1141
1142 uint32
1143 sb_size(uint32 admatch)
1144 {
1145         uint32 size;
1146         uint type;
1147
1148         type = admatch & SBAM_TYPE_MASK;
1149         ASSERT(type < 3);
1150
1151         size = 0;
1152
1153         if (type == 0) {
1154                 size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
1155         } else if (type == 1) {
1156                 ASSERT(!(admatch & SBAM_ADNEG));        /* neg not supported */
1157                 size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
1158         } else if (type == 2) {
1159                 ASSERT(!(admatch & SBAM_ADNEG));        /* neg not supported */
1160                 size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
1161         }
1162
1163         return (size);
1164 }
1165
1166 #if defined(BCMDBG) || defined(BCMDBG_DUMP)
1167 /* print interesting sbconfig registers */
1168 void
1169 sb_dumpregs(si_t *sih, struct bcmstrbuf *b)
1170 {
1171         si_info_t *sii;
1172         sbconfig_t *sb;
1173         uint origidx, i, intr_val = 0;
1174
1175         sii = SI_INFO(sih);
1176         origidx = sii->curidx;
1177
1178         INTR_OFF(sii, intr_val);
1179
1180         for (i = 0; i < sii->numcores; i++) {
1181                 sb = REGS2SB(sb_setcoreidx(sih, i));
1182
1183                 bcm_bprintf(b, "core 0x%x: \n", sii->coreid[i]);
1184
1185                 if (sii->pub.socirev > SONICS_2_2)
1186                         bcm_bprintf(b, "sbimerrlog 0x%x sbimerrloga 0x%x\n",
1187                                   sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOG, 0, 0),
1188                                   sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOGA, 0, 0));
1189
1190                 bcm_bprintf(b, "sbtmstatelow 0x%x sbtmstatehigh 0x%x sbidhigh 0x%x "
1191                             "sbimstate 0x%x\n sbimconfiglow 0x%x sbimconfighigh 0x%x\n",
1192                             R_SBREG(sii, &sb->sbtmstatelow), R_SBREG(sii, &sb->sbtmstatehigh),
1193                             R_SBREG(sii, &sb->sbidhigh), R_SBREG(sii, &sb->sbimstate),
1194                             R_SBREG(sii, &sb->sbimconfiglow), R_SBREG(sii, &sb->sbimconfighigh));
1195         }
1196
1197         sb_setcoreidx(sih, origidx);
1198         INTR_RESTORE(sii, intr_val);
1199 }
1200 #endif  /* BCMDBG || BCMDBG_DUMP */
1201
1202 #if defined(BCMDBG)
1203 void
1204 sb_view(si_t *sih, bool verbose)
1205 {
1206         si_info_t *sii;
1207         sbconfig_t *sb;
1208
1209         sii = SI_INFO(sih);
1210         sb = REGS2SB(sii->curmap);
1211
1212         SI_ERROR(("\nCore ID: 0x%x\n", sb_coreid(&sii->pub)));
1213
1214         if (sii->pub.socirev > SONICS_2_2)
1215                 SI_ERROR(("sbimerrlog 0x%x sbimerrloga 0x%x\n",
1216                          sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOG, 0, 0),
1217                          sb_corereg(sih, si_coreidx(&sii->pub), SBIMERRLOGA, 0, 0)));
1218
1219         /* Print important or helpful registers */
1220         SI_ERROR(("sbtmerrloga 0x%x sbtmerrlog 0x%x\n",
1221                   R_SBREG(sii, &sb->sbtmerrloga), R_SBREG(sii, &sb->sbtmerrlog)));
1222         SI_ERROR(("sbimstate 0x%x sbtmstatelow 0x%x sbtmstatehigh 0x%x\n",
1223                   R_SBREG(sii, &sb->sbimstate),
1224                   R_SBREG(sii, &sb->sbtmstatelow), R_SBREG(sii, &sb->sbtmstatehigh)));
1225         SI_ERROR(("sbimconfiglow 0x%x sbtmconfiglow 0x%x\nsbtmconfighigh 0x%x sbidhigh 0x%x\n",
1226                   R_SBREG(sii, &sb->sbimconfiglow), R_SBREG(sii, &sb->sbtmconfiglow),
1227                   R_SBREG(sii, &sb->sbtmconfighigh), R_SBREG(sii, &sb->sbidhigh)));
1228
1229         /* Print more detailed registers that are otherwise not relevant */
1230         if (verbose) {
1231                 SI_ERROR(("sbipsflag 0x%x sbtpsflag 0x%x\n",
1232                           R_SBREG(sii, &sb->sbipsflag), R_SBREG(sii, &sb->sbtpsflag)));
1233                 SI_ERROR(("sbadmatch3 0x%x sbadmatch2 0x%x\nsbadmatch1 0x%x sbadmatch0 0x%x\n",
1234                           R_SBREG(sii, &sb->sbadmatch3), R_SBREG(sii, &sb->sbadmatch2),
1235                           R_SBREG(sii, &sb->sbadmatch1), R_SBREG(sii, &sb->sbadmatch0)));
1236                 SI_ERROR(("sbintvec 0x%x sbbwa0 0x%x sbimconfighigh 0x%x\n",
1237                           R_SBREG(sii, &sb->sbintvec), R_SBREG(sii, &sb->sbbwa0),
1238                           R_SBREG(sii, &sb->sbimconfighigh)));
1239                 SI_ERROR(("sbbconfig 0x%x sbbstate 0x%x\n",
1240                           R_SBREG(sii, &sb->sbbconfig), R_SBREG(sii, &sb->sbbstate)));
1241                 SI_ERROR(("sbactcnfg 0x%x sbflagst 0x%x sbidlow 0x%x \n\n",
1242                           R_SBREG(sii, &sb->sbactcnfg), R_SBREG(sii, &sb->sbflagst),
1243                           R_SBREG(sii, &sb->sbidlow)));
1244         }
1245 }
1246 #endif  /* BCMDBG */