release/src-rt/linux/linux-2.6/drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 #ifdef  __KERNEL__
  23 #ifndef BIT
  24 #define BIT(nr) (1UL << (nr))
  25 #endif
  26 #endif
  27
  28 /* definitions used for the EHCI driver */
  29
  30 /*
  31  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  32  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  33  * the host controller implementation.
  34  *
  35  * To facilitate the strongest possible byte-order checking from "sparse"
  36  * and so on, we use __leXX unless that's not practical.
  37  */
  38 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  39 typedef __u32 __bitwise __hc32;
  40 typedef __u16 __bitwise __hc16;
  41 #else
  42 #define __hc32  __le32
  43 #define __hc16  __le16
  44 #endif
  45
  46 /* statistics can be kept for for tuning/monitoring */
  47 struct ehci_stats {
  48         /* irq usage */
  49         unsigned long           normal;
  50         unsigned long           error;
  51         unsigned long           reclaim;
  52         unsigned long           lost_iaa;
  53
  54         /* termination of urbs from core */
  55         unsigned long           complete;
  56         unsigned long           unlink;
  57 };
  58
  59 /* qtdc message level */
  60 #define QTDC_MSG_ERR    (1<<0)
  61 #define QTDC_MSG_STATS  (1<<1)
  62 #define QTDC_MSG_TRACE  (1<<2)
  63
  64 #ifdef EHCI_QTD_CACHE
  65 typedef struct ehci_qtdc {
  66         void    *ehci;          /* pointer to ehci */
  67         int     num;            /* qtdc number */
  68         int     ep;             /* endpoint */
  69         int     size;           /* max qtd's in cache */
  70         int     cnt;            /* current qtd's in cache */
  71         int     timeout;        /* max time to stay in cache */
  72         struct list_head        cache;  /* the qtd cache list */
  73         struct timer_list       watchdog;
  74 #ifdef EHCI_QTDC_DEBUG
  75         unsigned long   last_printed;   /* last time when we printed stats */
  76         unsigned long   cached_qtd;     /* counter for cached qtd's */
  77         unsigned long   timeout_qtd;    /* counter for qtd's released in timeout */
  78         unsigned long   timeout_qtd_max;/* max qtd's released in timeout */
  79         unsigned long   timeout_cnt;    /* counter for timeouts */
  80         unsigned long   release_qtd;    /* counter for qtd's released normally */
  81         unsigned long   release_cnt;    /* counter for normal release */
  82         unsigned int    msglevel;
  83 #endif  /* EHCI_QTDC_DEBUG */
  84 } ehci_qtdc_t;
  85
  86 #define NUM_QTD_CACHE   2       /* # of ep's supported (1 IN 1 OUT for now) */
  87
  88 #ifdef EHCI_QTDC_DEBUG
  89 #define QTDC_ERR(qtdc, msg)     do {    \
  90                                         if (qtdc->msglevel & QTDC_MSG_ERR) {    \
  91                                                 printk("qtdc ep 0x%x: ", qtdc->ep);     \
  92                                                 printk msg; \
  93                                         }       \
  94                                 } while(0)
  95 #define QTDC_STATS(qtdc, msg)   do {    \
  96                                         if (qtdc->msglevel & QTDC_MSG_STATS) {  \
  97                                                 printk("qtdc ep 0x%x: ", qtdc->ep);     \
  98                                                 printk msg; \
  99                                         }       \
 100                                 } while(0)
 101 #define QTDC_TRACE(qtdc, msg)   do {    \
 102                                         if (qtdc->msglevel & QTDC_MSG_TRACE) {  \
 103                                                 printk("qtdc ep 0x%x: ", qtdc->ep);     \
 104                                                 printk msg; \
 105                                         }       \
 106                                 } while(0)
 107 #else
 108 #define QTDC_ERR(qtdc, msg)
 109 #define QTDC_STATS(qtdc, msg)
 110 #define QTDC_TRACE(qtdc, msg)
 111 #endif  /* EHCI_QTDC_DEBUG */
 112 #endif  /* EHCI_QTD_CACHE */
 113
 114 /* ehci_hcd->lock guards shared data against other CPUs:
 115  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
 116  *   usb_host_endpoint: hcpriv
 117  *   ehci_qh:   qh_next, qtd_list
 118  *   ehci_qtd:  qtd_list
 119  *
 120  * Also, hold this lock when talking to HC registers or
 121  * when updating hw_* fields in shared qh/qtd/... structures.
 122  */
 123
 124 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
 125
 126 struct ehci_hcd {                       /* one per controller */
 127         /* glue to PCI and HCD framework */
 128         struct ehci_caps __iomem *caps;
 129         struct ehci_regs __iomem *regs;
 130         struct ehci_dbg_port __iomem *debug;
 131
 132         __u32                   hcs_params;     /* cached register copy */
 133         spinlock_t              lock;
 134
 135         /* async schedule support */
 136         struct ehci_qh          *async;
 137         struct ehci_qh          *dummy;         /* For AMD quirk use */
 138         struct ehci_qh          *reclaim;
 139         unsigned                scanning : 1;
 140
 141         /* periodic schedule support */
 142 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
 143         unsigned                periodic_size;
 144         __hc32                  *periodic;      /* hw periodic table */
 145         dma_addr_t              periodic_dma;
 146         unsigned                i_thresh;       /* uframes HC might cache */
 147
 148         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
 149         int                     next_uframe;    /* scan periodic, start here */
 150         unsigned                periodic_sched; /* periodic activity count */
 151
 152         /* list of itds & sitds completed while clock_frame was still active */
 153         struct list_head        cached_itd_list;
 154         struct list_head        cached_sitd_list;
 155         unsigned                clock_frame;
 156
 157         /* per root hub port */
 158         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
 159
 160         /* bit vectors (one bit per port) */
 161         unsigned long           bus_suspended;          /* which ports were
 162                         already suspended at the start of a bus suspend */
 163         unsigned long           companion_ports;        /* which ports are
 164                         dedicated to the companion controller */
 165         unsigned long           owned_ports;            /* which ports are
 166                         owned by the companion during a bus suspend */
 167         unsigned long           port_c_suspend;         /* which ports have
 168                         the change-suspend feature turned on */
 169         unsigned long           suspended_ports;        /* which ports are
 170                         suspended */
 171
 172         /* per-HC memory pools (could be per-bus, but ...) */
 173         struct dma_pool         *qh_pool;       /* qh per active urb */
 174         struct dma_pool         *qtd_pool;      /* one or more per qh */
 175         struct dma_pool         *itd_pool;      /* itd per iso urb */
 176         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 177
 178         struct timer_list       iaa_watchdog;
 179         struct timer_list       watchdog;
 180         unsigned long           actions;
 181         unsigned                stamp;
 182         unsigned                random_frame;
 183         unsigned long           next_statechange;
 184         ktime_t                 last_periodic_enable;
 185         u32                     command;
 186
 187         /* SILICON QUIRKS */
 188         unsigned                no_selective_suspend:1;
 189         unsigned                has_fsl_port_bug:1; /* FreeScale */
 190         unsigned                big_endian_mmio:1;
 191         unsigned                big_endian_desc:1;
 192         unsigned                need_io_watchdog:1;
 193         unsigned                broken_periodic:1;
 194         unsigned                fs_i_thresh:1;  /* Intel iso scheduling */
 195         unsigned                use_dummy_qh:1; /* AMD Frame List table quirk*/
 196
 197         u8                      sbrn;           /* packed release number */
 198
 199 #ifdef EHCI_QTD_CACHE
 200         int                     qtdc_pid;
 201         int                     qtdc_vid;
 202         struct usb_device       *qtdc_dev;
 203         ehci_qtdc_t*            qtdc[NUM_QTD_CACHE];
 204         struct timer_list       qtdc_watchdog;
 205 #endif /* EHCI_QTD_CACHE */
 206
 207         /* irq statistics */
 208 #ifdef EHCI_STATS
 209         struct ehci_stats       stats;
 210 #       define COUNT(x) do { (x)++; } while (0)
 211 #else
 212 #       define COUNT(x) do {} while (0)
 213 #endif
 214
 215         /* debug files */
 216 #ifdef DEBUG
 217         struct dentry           *debug_dir;
 218 #endif
 219
 220         /* EHCI fastpath acceleration */
 221         struct usb_device *bypass_device;
 222         struct ehci_qh *ehci_pipes[3]; /* pointer to ep location with qh address */
 223         void (*ehci_bypass_callback)(int pipeindex, struct ehci_qh *, spinlock_t *lock);
 224         struct dma_pool *fastpath_pool; /* fastpath qtd pool */
 225 };
 226
 227 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 228 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 229 {
 230         return (struct ehci_hcd *) (hcd->hcd_priv);
 231 }
 232 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 233 {
 234         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 235 }
 236
 237
 238 static inline void
 239 iaa_watchdog_start(struct ehci_hcd *ehci)
 240 {
 241         WARN_ON(timer_pending(&ehci->iaa_watchdog));
 242         mod_timer(&ehci->iaa_watchdog,
 243                         jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
 244 }
 245
 246 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
 247 {
 248         del_timer(&ehci->iaa_watchdog);
 249 }
 250
 251 enum ehci_timer_action {
 252         TIMER_IO_WATCHDOG,
 253         TIMER_ASYNC_SHRINK,
 254         TIMER_ASYNC_OFF,
 255 };
 256
 257 static inline void
 258 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 259 {
 260         clear_bit (action, &ehci->actions);
 261 }
 262
 263 static void free_cached_lists(struct ehci_hcd *ehci);
 264
 265 /*-------------------------------------------------------------------------*/
 266
 267 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 268
 269 /* Section 2.2 Host Controller Capability Registers */
 270 struct ehci_caps {
 271         /* these fields are specified as 8 and 16 bit registers,
 272          * but some hosts can't perform 8 or 16 bit PCI accesses.
 273          */
 274         u32             hc_capbase;
 275 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
 276 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
 277         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 278 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 279 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
 280 #define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
 281 #define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
 282 #define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
 283 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
 284 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 285
 286         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 287 #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
 288 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 289 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 290 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 291 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 292 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 293         u8              portroute [8];   /* nibbles for routing - offset 0xC */
 294 };
 295
 296
 297 /* Section 2.3 Host Controller Operational Registers */
 298 struct ehci_regs {
 299
 300         /* USBCMD: offset 0x00 */
 301         u32             command;
 302 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 303 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 304 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 305 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
 306 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 307 #define CMD_ASE         (1<<5)          /* async schedule enable */
 308 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 309 /* 3:2 is periodic frame list size */
 310 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 311 #define CMD_RUN         (1<<0)          /* start/stop HC */
 312
 313         /* USBSTS: offset 0x04 */
 314         u32             status;
 315 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 316 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 317 #define STS_RECL        (1<<13)         /* Reclamation */
 318 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 319 /* some bits reserved */
 320         /* these STS_* flags are also intr_enable bits (USBINTR) */
 321 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 322 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 323 #define STS_FLR         (1<<3)          /* frame list rolled over */
 324 #define STS_PCD         (1<<2)          /* port change detect */
 325 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 326 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 327
 328         /* USBINTR: offset 0x08 */
 329         u32             intr_enable;
 330
 331         /* FRINDEX: offset 0x0C */
 332         u32             frame_index;    /* current microframe number */
 333         /* CTRLDSSEGMENT: offset 0x10 */
 334         u32             segment;        /* address bits 63:32 if needed */
 335         /* PERIODICLISTBASE: offset 0x14 */
 336         u32             frame_list;     /* points to periodic list */
 337         /* ASYNCLISTADDR: offset 0x18 */
 338         u32             async_next;     /* address of next async queue head */
 339
 340         u32             reserved [9];
 341
 342         /* CONFIGFLAG: offset 0x40 */
 343         u32             configured_flag;
 344 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
 345
 346         /* PORTSC: offset 0x44 */
 347         u32             port_status [0];        /* up to N_PORTS */
 348 /* 31:23 reserved */
 349 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 350 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 351 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 352 /* 19:16 for port testing */
 353 #define PORT_LED_OFF    (0<<14)
 354 #define PORT_LED_AMBER  (1<<14)
 355 #define PORT_LED_GREEN  (2<<14)
 356 #define PORT_LED_MASK   (3<<14)
 357 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 358 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 359 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 360 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 361 /* 9 reserved */
 362 #define PORT_RESET      (1<<8)          /* reset port */
 363 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 364 #define PORT_RESUME     (1<<6)          /* resume it */
 365 #define PORT_OCC        (1<<5)          /* over current change */
 366 #define PORT_OC         (1<<4)          /* over current active */
 367 #define PORT_PEC        (1<<3)          /* port enable change */
 368 #define PORT_PE         (1<<2)          /* port enable */
 369 #define PORT_CSC        (1<<1)          /* connect status change */
 370 #define PORT_CONNECT    (1<<0)          /* device connected */
 371 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
 372 };
 373
 374 #define USBMODE         0x68            /* USB Device mode */
 375 #define USBMODE_SDIS    (1<<3)          /* Stream disable */
 376 #define USBMODE_BE      (1<<2)          /* BE/LE endianness select */
 377 #define USBMODE_CM_HC   (3<<0)          /* host controller mode */
 378 #define USBMODE_CM_IDLE (0<<0)          /* idle state */
 379
 380 /* Appendix C, Debug port ... intended for use with special "debug devices"
 381  * that can help if there's no serial console.  (nonstandard enumeration.)
 382  */
 383 struct ehci_dbg_port {
 384         u32     control;
 385 #define DBGP_OWNER      (1<<30)
 386 #define DBGP_ENABLED    (1<<28)
 387 #define DBGP_DONE       (1<<16)
 388 #define DBGP_INUSE      (1<<10)
 389 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 390 #       define DBGP_ERR_BAD     1
 391 #       define DBGP_ERR_SIGNAL  2
 392 #define DBGP_ERROR      (1<<6)
 393 #define DBGP_GO         (1<<5)
 394 #define DBGP_OUT        (1<<4)
 395 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 396         u32     pids;
 397 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 398 #define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
 399         u32     data03;
 400         u32     data47;
 401         u32     address;
 402 #define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
 403 };
 404
 405 /*-------------------------------------------------------------------------*/
 406
 407 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 408
 409 /*
 410  * EHCI Specification 0.95 Section 3.5
 411  * QTD: describe data transfer components (buffer, direction, ...)
 412  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 413  *
 414  * These are associated only with "QH" (Queue Head) structures,
 415  * used with control, bulk, and interrupt transfers.
 416  */
 417 struct ehci_qtd {
 418         /* first part defined by EHCI spec */
 419         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 420         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 421         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 422 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 423 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 424 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 425 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 426 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 427 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 428 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 429 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 430 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 431 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 432 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 433 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 434 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 435
 436 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 437 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 438 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 439
 440         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 441         __hc32                  hw_buf_hi [5];        /* Appendix B */
 442
 443         /* the rest is HCD-private */
 444         dma_addr_t              qtd_dma;                /* qtd address */
 445         struct list_head        qtd_list;               /* sw qtd list */
 446         struct urb              *urb;                   /* qtd's urb */
 447         size_t                  length;                 /* length of buffer */
 448 } __attribute__ ((aligned (32)));
 449
 450 /* mask NakCnt+T in qh->hw_alt_next */
 451 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 452
 453 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 454
 455 /*-------------------------------------------------------------------------*/
 456
 457 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 458 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 459
 460 /*
 461  * Now the following defines are not converted using the
 462  * __constant_cpu_to_le32() macro anymore, since we have to support
 463  * "dynamic" switching between be and le support, so that the driver
 464  * can be used on one system with SoC EHCI controller using big-endian
 465  * descriptors as well as a normal little-endian PCI EHCI controller.
 466  */
 467 /* values for that type tag */
 468 #define Q_TYPE_ITD      (0 << 1)
 469 #define Q_TYPE_QH       (1 << 1)
 470 #define Q_TYPE_SITD     (2 << 1)
 471 #define Q_TYPE_FSTN     (3 << 1)
 472
 473 /* next async queue entry, or pointer to interrupt/periodic QH */
 474 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 475
 476 /* for periodic/async schedules and qtd lists, mark end of list */
 477 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 478
 479 /*
 480  * Entries in periodic shadow table are pointers to one of four kinds
 481  * of data structure.  That's dictated by the hardware; a type tag is
 482  * encoded in the low bits of the hardware's periodic schedule.  Use
 483  * Q_NEXT_TYPE to get the tag.
 484  *
 485  * For entries in the async schedule, the type tag always says "qh".
 486  */
 487 union ehci_shadow {
 488         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 489         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 490         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 491         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 492         __hc32                  *hw_next;       /* (all types) */
 493         void                    *ptr;
 494 };
 495
 496 /*-------------------------------------------------------------------------*/
 497
 498 /*
 499  * EHCI Specification 0.95 Section 3.6
 500  * QH: describes control/bulk/interrupt endpoints
 501  * See Fig 3-7 "Queue Head Structure Layout".
 502  *
 503  * These appear in both the async and (for interrupt) periodic schedules.
 504  */
 505
 506 /* first part defined by EHCI spec */
 507 struct ehci_qh_hw {
 508         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 509         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 510 #define QH_HEAD         0x00008000
 511         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 512 #define QH_SMASK        0x000000ff
 513 #define QH_CMASK        0x0000ff00
 514 #define QH_HUBADDR      0x007f0000
 515 #define QH_HUBPORT      0x3f800000
 516 #define QH_MULT         0xc0000000
 517         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 518
 519         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 520         __hc32                  hw_qtd_next;
 521         __hc32                  hw_alt_next;
 522         __hc32                  hw_token;
 523         __hc32                  hw_buf [5];
 524         __hc32                  hw_buf_hi [5];
 525 } __attribute__ ((aligned(32)));
 526
 527 struct ehci_qh {
 528         struct ehci_qh_hw       *hw;
 529         /* the rest is HCD-private */
 530         dma_addr_t              qh_dma;         /* address of qh */
 531         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 532         struct list_head        qtd_list;       /* sw qtd list */
 533         struct ehci_qtd         *dummy;
 534         struct ehci_qh          *reclaim;       /* next to reclaim */
 535
 536         struct ehci_hcd         *ehci;
 537
 538         /*
 539          * Do NOT use atomic operations for QH refcounting. On some CPUs
 540          * (PPC7448 for example), atomic operations cannot be performed on
 541          * memory that is cache-inhibited (i.e. being used for DMA).
 542          * Spinlocks are used to protect all QH fields.
 543          */
 544         u32                     refcount;
 545         unsigned                stamp;
 546
 547         u8                      needs_rescan;   /* Dequeue during giveback */
 548         u8                      qh_state;
 549 #define QH_STATE_LINKED         1               /* HC sees this */
 550 #define QH_STATE_UNLINK         2               /* HC may still see this */
 551 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 552 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 553 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 554 #define QH_STATE_DETACHED       6
 555         u8                      xacterrs;       /* XactErr retry counter */
 556 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 557
 558         /* periodic schedule info */
 559         u8                      usecs;          /* intr bandwidth */
 560         u8                      gap_uf;         /* uframes split/csplit gap */
 561         u8                      c_usecs;        /* ... split completion bw */
 562         u16                     tt_usecs;       /* tt downstream bandwidth */
 563         unsigned short          period;         /* polling interval */
 564         unsigned short          start;          /* where polling starts */
 565 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 566         struct usb_device       *dev;           /* access to TT */
 567         struct ehci_qtd         *first_qtd;     /* optimzied equivalent of the qtd_list */
 568         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 569 };
 570
 571 /*-------------------------------------------------------------------------*/
 572
 573 /* description of one iso transaction (up to 3 KB data if highspeed) */
 574 struct ehci_iso_packet {
 575         /* These will be copied to iTD when scheduling */
 576         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 577         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 578         u8                      cross;          /* buf crosses pages */
 579         /* for full speed OUT splits */
 580         u32                     buf1;
 581 };
 582
 583 /* temporary schedule data for packets from iso urbs (both speeds)
 584  * each packet is one logical usb transaction to the device (not TT),
 585  * beginning at stream->next_uframe
 586  */
 587 struct ehci_iso_sched {
 588         struct list_head        td_list;
 589         unsigned                span;
 590         struct ehci_iso_packet  packet [0];
 591 };
 592
 593 /*
 594  * ehci_iso_stream - groups all (s)itds for this endpoint.
 595  * acts like a qh would, if EHCI had them for ISO.
 596  */
 597 struct ehci_iso_stream {
 598         /* first field matches ehci_hq, but is NULL */
 599         struct ehci_qh_hw       *hw;
 600
 601         u32                     refcount;
 602         u8                      bEndpointAddress;
 603         u8                      highspeed;
 604         struct list_head        td_list;        /* queued itds/sitds */
 605         struct list_head        free_list;      /* list of unused itds/sitds */
 606         struct usb_device       *udev;
 607         struct usb_host_endpoint *ep;
 608
 609         /* output of (re)scheduling */
 610         int                     next_uframe;
 611         __hc32                  splits;
 612
 613         /* the rest is derived from the endpoint descriptor,
 614          * trusting urb->interval == f(epdesc->bInterval) and
 615          * including the extra info for hw_bufp[0..2]
 616          */
 617         u8                      usecs, c_usecs;
 618         u16                     interval;
 619         u16                     tt_usecs;
 620         u16                     maxp;
 621         u16                     raw_mask;
 622         unsigned                bandwidth;
 623
 624         /* This is used to initialize iTD's hw_bufp fields */
 625         __hc32                  buf0;
 626         __hc32                  buf1;
 627         __hc32                  buf2;
 628
 629         /* this is used to initialize sITD's tt info */
 630         __hc32                  address;
 631 };
 632
 633 /*-------------------------------------------------------------------------*/
 634
 635 /*
 636  * EHCI Specification 0.95 Section 3.3
 637  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 638  *
 639  * Schedule records for high speed iso xfers
 640  */
 641 struct ehci_itd {
 642         /* first part defined by EHCI spec */
 643         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 644         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 645 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 646 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 647 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 648 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 649 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 650 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 651
 652 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 653
 654         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 655         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 656
 657         /* the rest is HCD-private */
 658         dma_addr_t              itd_dma;        /* for this itd */
 659         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 660
 661         struct urb              *urb;
 662         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 663         struct list_head        itd_list;       /* list of stream's itds */
 664
 665         /* any/all hw_transactions here may be used by that urb */
 666         unsigned                frame;          /* where scheduled */
 667         unsigned                pg;
 668         unsigned                index[8];       /* in urb->iso_frame_desc */
 669 } __attribute__ ((aligned (32)));
 670
 671 /*-------------------------------------------------------------------------*/
 672
 673 /*
 674  * EHCI Specification 0.95 Section 3.4
 675  * siTD, aka split-transaction isochronous Transfer Descriptor
 676  *       ... describe full speed iso xfers through TT in hubs
 677  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 678  */
 679 struct ehci_sitd {
 680         /* first part defined by EHCI spec */
 681         __hc32                  hw_next;
 682 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 683         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 684         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 685         __hc32                  hw_results;             /* EHCI table 3-11 */
 686 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 687 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 688 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 689 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 690 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 691 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 692 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 693 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 694 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 695 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 696
 697 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 698
 699         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 700         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 701         __hc32                  hw_buf_hi [2];          /* Appendix B */
 702
 703         /* the rest is HCD-private */
 704         dma_addr_t              sitd_dma;
 705         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 706
 707         struct urb              *urb;
 708         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 709         struct list_head        sitd_list;      /* list of stream's sitds */
 710         unsigned                frame;
 711         unsigned                index;
 712 } __attribute__ ((aligned (32)));
 713
 714 /*-------------------------------------------------------------------------*/
 715
 716 /*
 717  * EHCI Specification 0.96 Section 3.7
 718  * Periodic Frame Span Traversal Node (FSTN)
 719  *
 720  * Manages split interrupt transactions (using TT) that span frame boundaries
 721  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 722  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 723  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 724  */
 725 struct ehci_fstn {
 726         __hc32                  hw_next;        /* any periodic q entry */
 727         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 728
 729         /* the rest is HCD-private */
 730         dma_addr_t              fstn_dma;
 731         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 732 } __attribute__ ((aligned (32)));
 733
 734 /*-------------------------------------------------------------------------*/
 735
 736 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 737
 738 /*
 739  * Some EHCI controllers have a Transaction Translator built into the
 740  * root hub. This is a non-standard feature.  Each controller will need
 741  * to add code to the following inline functions, and call them as
 742  * needed (mostly in root hub code).
 743  */
 744
 745 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 746
 747 /* Returns the speed of a device attached to a port on the root hub. */
 748 static inline unsigned int
 749 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 750 {
 751         if (ehci_is_TDI(ehci)) {
 752                 switch ((portsc>>26)&3) {
 753                 case 0:
 754                         return 0;
 755                 case 1:
 756                         return (1<<USB_PORT_FEAT_LOWSPEED);
 757                 case 2:
 758                 default:
 759                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 760                 }
 761         }
 762         return (1<<USB_PORT_FEAT_HIGHSPEED);
 763 }
 764
 765 #else
 766
 767 #define ehci_is_TDI(e)                  (0)
 768
 769 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 770 #endif
 771
 772 /*-------------------------------------------------------------------------*/
 773
 774 #ifdef CONFIG_PPC_83xx
 775 /* Some Freescale processors have an erratum in which the TT
 776  * port number in the queue head was 0..N-1 instead of 1..N.
 777  */
 778 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 779 #else
 780 #define ehci_has_fsl_portno_bug(e)              (0)
 781 #endif
 782
 783 /*
 784  * While most USB host controllers implement their registers in
 785  * little-endian format, a minority (celleb companion chip) implement
 786  * them in big endian format.
 787  *
 788  * This attempts to support either format at compile time without a
 789  * runtime penalty, or both formats with the additional overhead
 790  * of checking a flag bit.
 791  */
 792
 793 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 794 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 795 #else
 796 #define ehci_big_endian_mmio(e)         0
 797 #endif
 798
 799 /*
 800  * Big-endian read/write functions are arch-specific.
 801  * Other arches can be added if/when they're needed.
 802  *
 803  * REVISIT: arch/powerpc now has readl/writel_be, so the
 804  * definition below can die once the 4xx support is
 805  * finally ported over.
 806  */
 807 #if defined(CONFIG_PPC)
 808 #define readl_be(addr)          in_be32((__force unsigned *)addr)
 809 #define writel_be(val, addr)    out_be32((__force unsigned *)addr, val)
 810 #endif
 811
 812 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 813                 __u32 __iomem * regs)
 814 {
 815 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 816         return ehci_big_endian_mmio(ehci) ?
 817                 readl_be(regs) :
 818                 readl(regs);
 819 #else
 820         return readl(regs);
 821 #endif
 822 }
 823
 824 static inline void ehci_writel(const struct ehci_hcd *ehci,
 825                 const unsigned int val, __u32 __iomem *regs)
 826 {
 827 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 828         ehci_big_endian_mmio(ehci) ?
 829                 writel_be(val, regs) :
 830                 writel(val, regs);
 831 #else
 832         writel(val, regs);
 833 #endif
 834 }
 835
 836 /*-------------------------------------------------------------------------*/
 837
 838 /*
 839  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 840  * format, but also its DMA data structures (descriptors).
 841  *
 842  * EHCI controllers accessed through PCI work normally (little-endian
 843  * everywhere), so we won't bother supporting a BE-only mode for now.
 844  */
 845 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 846 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 847
 848 /* cpu to ehci */
 849 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 850 {
 851         return ehci_big_endian_desc(ehci)
 852                 ? (__force __hc32)cpu_to_be32(x)
 853                 : (__force __hc32)cpu_to_le32(x);
 854 }
 855
 856 /* ehci to cpu */
 857 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 858 {
 859         return ehci_big_endian_desc(ehci)
 860                 ? be32_to_cpu((__force __be32)x)
 861                 : le32_to_cpu((__force __le32)x);
 862 }
 863
 864 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 865 {
 866         return ehci_big_endian_desc(ehci)
 867                 ? be32_to_cpup((__force __be32 *)x)
 868                 : le32_to_cpup((__force __le32 *)x);
 869 }
 870
 871 #else
 872
 873 /* cpu to ehci */
 874 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 875 {
 876         return cpu_to_le32(x);
 877 }
 878
 879 /* ehci to cpu */
 880 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 881 {
 882         return le32_to_cpu(x);
 883 }
 884
 885 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 886 {
 887         return le32_to_cpup(x);
 888 }
 889
 890 #endif
 891
 892 /*-------------------------------------------------------------------------*/
 893
 894 #ifndef DEBUG
 895 #define STUB_DEBUG_FILES
 896 #endif  /* DEBUG */
 897
 898 /* EHCI fastpath acceleration */
 899 #define EHCI_FASTPATH           0x31
 900 #define EHCI_SET_EP_BYPASS      (0x4300 | EHCI_FASTPATH)
 901 #define EHCI_SET_BYPASS_CB      (0x4300 | (EHCI_FASTPATH+1))
 902 #define EHCI_SET_BYPASS_DEV     (0x4300 | (EHCI_FASTPATH+2))
 903 #define EHCI_DUMP_STATE         (0x4300 | (EHCI_FASTPATH+3))
 904 #define EHCI_SET_BYPASS_POOL    (0x4300 | (EHCI_FASTPATH+4))
 905 #define EHCI_CLR_EP_BYPASS      (0x4300 | (EHCI_FASTPATH+5))
 906
 907
 908
 909
 910
 911 /*-------------------------------------------------------------------------*/
 912
 913 #endif /* __LINUX_EHCI_HCD_H */
 914