release/src/include/sbhndmips.h

   1 /*
   2  * Broadcom SiliconBackplane MIPS definitions
   3  *
   4  * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
   5  * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
   6  * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
   7  * interface. The core revision is stored in the SB ID register in SB
   8  * configuration space.
   9  *
  10  * Copyright 2007, Broadcom Corporation
  11  * All Rights Reserved.
  12  *
  13  * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
  14  * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
  15  * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
  16  * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
  17  *
  18  * $Id$
  19  */
  20
  21 #ifndef _sbhndmips_h_
  22 #define _sbhndmips_h_
  23
  24 #include <mipsinc.h>
  25
  26 #ifndef _LANGUAGE_ASSEMBLY
  27
  28 /* cpp contortions to concatenate w/arg prescan */
  29 #ifndef PAD
  30 #define _PADLINE(line)  pad ## line
  31 #define _XSTR(line)     _PADLINE(line)
  32 #define PAD             _XSTR(__LINE__)
  33 #endif  /* PAD */
  34
  35 typedef volatile struct {
  36         uint32  corecontrol;
  37         uint32  PAD[2];
  38         uint32  biststatus;
  39         uint32  PAD[4];
  40         uint32  intstatus;
  41         uint32  intmask;
  42         uint32  timer;
  43 } mipsregs_t;
  44
  45 #endif  /* _LANGUAGE_ASSEMBLY */
  46
  47 #endif  /* _sbhndmips_h_ */