2 * Include file private to the SOC Interconnect support files.
4 * Copyright (C) 2011, Broadcom Corporation. All Rights Reserved.
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 * $Id: siutils_priv.h 302333 2011-12-11 01:47:49Z $
21 #ifndef _siutils_priv_h_
22 #define _siutils_priv_h_
25 #define SI_ERROR(args) printf args
27 #define SI_ERROR(args)
28 #endif /* BCMDBG_ERR */
31 #define SI_MSG(args) printf args
37 #define SI_VMSG(args) printf args
42 #define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
44 typedef uint32 (*si_intrsoff_t
)(void *intr_arg
);
45 typedef void (*si_intrsrestore_t
)(void *intr_arg
, uint32 arg
);
46 typedef bool (*si_intrsenabled_t
)(void *intr_arg
);
48 typedef struct gpioh_item
{
51 gpio_handler_t handler
;
53 struct gpioh_item
*next
;
56 /* misc si info needed by some of the routines */
57 typedef struct si_info
{
58 struct si_pub pub
; /* back plane public state (must be first field) */
60 void *osh
; /* osl os handle */
61 void *sdh
; /* bcmsdh handle */
63 uint dev_coreid
; /* the core provides driver functions */
64 void *intr_arg
; /* interrupt callback function arg */
65 si_intrsoff_t intrsoff_fn
; /* turns chip interrupts off */
66 si_intrsrestore_t intrsrestore_fn
; /* restore chip interrupts */
67 si_intrsenabled_t intrsenabled_fn
; /* check if interrupts are enabled */
69 void *pch
; /* PCI/E core handle */
71 gpioh_item_t
*gpioh_head
; /* GPIO event handlers list */
73 bool memseg
; /* flag to toggle MEM_SEG register */
78 void *curmap
; /* current regs va */
79 void *regs
[SI_MAXCORES
]; /* other regs va */
81 uint curidx
; /* current core index */
82 uint numcores
; /* # discovered cores */
83 uint coreid
[SI_MAXCORES
]; /* id of each core */
84 uint32 coresba
[SI_MAXCORES
]; /* backplane address of each core */
85 void *regs2
[SI_MAXCORES
]; /* va of each core second register set (usbh20) */
86 uint32 coresba2
[SI_MAXCORES
]; /* address of each core second register set (usbh20) */
87 uint32 coresba_size
[SI_MAXCORES
]; /* backplane address space size */
88 uint32 coresba2_size
[SI_MAXCORES
]; /* second address space size */
90 void *curwrap
; /* current wrapper va */
91 void *wrappers
[SI_MAXCORES
]; /* other cores wrapper va */
92 uint32 wrapba
[SI_MAXCORES
]; /* address of controlling wrapper */
94 uint32 cia
[SI_MAXCORES
]; /* erom cia entry for each core */
95 uint32 cib
[SI_MAXCORES
]; /* erom cia entry for each core */
96 uint32 oob_router
; /* oob router registers for axi */
99 #define SI_INFO(sih) (si_info_t *)(uintptr)sih
101 #define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
102 ISALIGNED((x), SI_CORE_SIZE))
103 #define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE))
104 #define BADCOREADDR 0
105 #define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
106 #define NOREV -1 /* Invalid rev */
108 #define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
109 ((si)->pub.buscoretype == PCI_CORE_ID))
111 #define PCIE_GEN1(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
112 ((si)->pub.buscoretype == PCIE_CORE_ID))
114 #define PCIE_GEN2(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \
115 ((si)->pub.buscoretype == PCIE2_CORE_ID))
117 #define PCIE(si) (PCIE_GEN1(si) || PCIE_GEN2(si))
119 #define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE))
121 /* Newer chips can access PCI/PCIE and CC core without requiring to change
124 #define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13)))
126 #define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
127 #define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
130 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
131 * after core switching to avoid invalid register accesss inside ISR.
133 #define INTR_OFF(si, intr_val) \
134 if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
135 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
136 #define INTR_RESTORE(si, intr_val) \
137 if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
138 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
140 /* dynamic clock control defines */
141 #define LPOMINFREQ 25000 /* low power oscillator min */
142 #define LPOMAXFREQ 43000 /* low power oscillator max */
143 #define XTALMINFREQ 19800000 /* 20 MHz - 1% */
144 #define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
145 #define PCIMINFREQ 25000000 /* 25 MHz */
146 #define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
148 #define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
149 #define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
151 #define PCI_FORCEHT(si) \
152 (((PCIE_GEN1(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \
153 ((PCI(si) || PCIE_GEN1(si)) && (si->pub.chip == BCM4321_CHIP_ID)) || \
154 (PCIE_GEN1(si) && (si->pub.chip == BCM4716_CHIP_ID)) || \
155 (PCIE_GEN1(si) && (si->pub.chip == BCM4748_CHIP_ID)))
157 /* GPIO Based LED powersave defines */
158 #define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
159 #define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
161 #ifndef DEFAULT_GPIOTIMERVAL
162 #define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
165 /* Silicon Backplane externs */
166 extern void sb_scan(si_t
*sih
, void *regs
, uint devid
);
167 extern uint
sb_coreid(si_t
*sih
);
168 extern uint
sb_intflag(si_t
*sih
);
169 extern uint
sb_flag(si_t
*sih
);
170 extern void sb_setint(si_t
*sih
, int siflag
);
171 extern uint
sb_corevendor(si_t
*sih
);
172 extern uint
sb_corerev(si_t
*sih
);
173 extern uint
sb_corereg(si_t
*sih
, uint coreidx
, uint regoff
, uint mask
, uint val
);
174 extern bool sb_iscoreup(si_t
*sih
);
175 extern void *sb_setcoreidx(si_t
*sih
, uint coreidx
);
176 extern uint32
sb_core_cflags(si_t
*sih
, uint32 mask
, uint32 val
);
177 extern void sb_core_cflags_wo(si_t
*sih
, uint32 mask
, uint32 val
);
178 extern uint32
sb_core_sflags(si_t
*sih
, uint32 mask
, uint32 val
);
179 extern void sb_commit(si_t
*sih
);
180 extern uint32
sb_base(uint32 admatch
);
181 extern uint32
sb_size(uint32 admatch
);
182 extern void sb_core_reset(si_t
*sih
, uint32 bits
, uint32 resetbits
);
183 extern void sb_core_disable(si_t
*sih
, uint32 bits
);
184 extern uint32
sb_addrspace(si_t
*sih
, uint asidx
);
185 extern uint32
sb_addrspacesize(si_t
*sih
, uint asidx
);
186 extern int sb_numaddrspaces(si_t
*sih
);
188 extern uint32
sb_set_initiator_to(si_t
*sih
, uint32 to
, uint idx
);
190 extern bool sb_taclear(si_t
*sih
, bool details
);
193 extern void sb_view(si_t
*sih
, bool verbose
);
194 extern void sb_viewall(si_t
*sih
, bool verbose
);
197 extern void sb_dumpregs(si_t
*sih
, struct bcmstrbuf
*b
);
200 /* Wake-on-wireless-LAN (WOWL) */
201 extern bool sb_pci_pmecap(si_t
*sih
);
203 extern bool sb_pci_fastpmecap(struct osl_info
*osh
);
204 extern bool sb_pci_pmeclr(si_t
*sih
);
205 extern void sb_pci_pmeen(si_t
*sih
);
206 extern uint
sb_pcie_readreg(void *sih
, uint addrtype
, uint offset
);
208 /* AMBA Interconnect exported externs */
209 extern si_t
*ai_attach(uint pcidev
, osl_t
*osh
, void *regs
, uint bustype
,
210 void *sdh
, char **vars
, uint
*varsz
);
211 extern si_t
*ai_kattach(osl_t
*osh
);
212 extern void ai_scan(si_t
*sih
, void *regs
, uint devid
);
214 extern uint
ai_flag(si_t
*sih
);
215 extern void ai_setint(si_t
*sih
, int siflag
);
216 extern uint
ai_coreidx(si_t
*sih
);
217 extern uint
ai_corevendor(si_t
*sih
);
218 extern uint
ai_corerev(si_t
*sih
);
219 extern bool ai_iscoreup(si_t
*sih
);
220 extern void *ai_setcoreidx(si_t
*sih
, uint coreidx
);
221 extern uint32
ai_core_cflags(si_t
*sih
, uint32 mask
, uint32 val
);
222 extern void ai_core_cflags_wo(si_t
*sih
, uint32 mask
, uint32 val
);
223 extern uint32
ai_core_sflags(si_t
*sih
, uint32 mask
, uint32 val
);
224 extern uint
ai_corereg(si_t
*sih
, uint coreidx
, uint regoff
, uint mask
, uint val
);
225 extern void ai_core_reset(si_t
*sih
, uint32 bits
, uint32 resetbits
);
226 extern void ai_core_disable(si_t
*sih
, uint32 bits
);
227 extern int ai_numaddrspaces(si_t
*sih
);
228 extern uint32
ai_addrspace(si_t
*sih
, uint asidx
);
229 extern uint32
ai_addrspacesize(si_t
*sih
, uint asidx
);
230 extern void ai_coreaddrspaceX(si_t
*sih
, uint asidx
, uint32
*addr
, uint32
*size
);
231 extern uint
ai_wrap_reg(si_t
*sih
, uint32 offset
, uint32 mask
, uint32 val
);
234 extern void ai_view(si_t
*sih
, bool verbose
);
235 extern void ai_viewall(si_t
*sih
, bool verbose
);
238 extern void ai_dumpregs(si_t
*sih
, struct bcmstrbuf
*b
);
241 #ifdef SI_ENUM_BASE_VARIABLE
242 extern void si_enum_base_init(si_t
*sih
, uint bustype
);
243 #endif /* SI_ENUM_BASE_VARIABLE */
245 #define ub_scan(a, b, c) do {} while (0)
246 #define ub_flag(a) (0)
247 #define ub_setint(a, b) do {} while (0)
248 #define ub_coreidx(a) (0)
249 #define ub_corevendor(a) (0)
250 #define ub_corerev(a) (0)
251 #define ub_iscoreup(a) (0)
252 #define ub_setcoreidx(a, b) (0)
253 #define ub_core_cflags(a, b, c) (0)
254 #define ub_core_cflags_wo(a, b, c) do {} while (0)
255 #define ub_core_sflags(a, b, c) (0)
256 #define ub_corereg(a, b, c, d, e) (0)
257 #define ub_core_reset(a, b, c) do {} while (0)
258 #define ub_core_disable(a, b) do {} while (0)
259 #define ub_numaddrspaces(a) (0)
260 #define ub_addrspace(a, b) (0)
261 #define ub_addrspacesize(a, b) (0)
262 #define ub_view(a, b) do {} while (0)
263 #define ub_dumpregs(a, b) do {} while (0)
265 #endif /* _siutils_priv_h_ */