release/src-rt/include/siutils.h

   1 /*
   2  * Misc utility routines for accessing the SOC Interconnects
   3  * of Broadcom HNBU chips.
   4  *
   5  * Copyright (C) 2011, Broadcom Corporation. All Rights Reserved.
   6  *
   7  * Permission to use, copy, modify, and/or distribute this software for any
   8  * purpose with or without fee is hereby granted, provided that the above
   9  * copyright notice and this permission notice appear in all copies.
  10  *
  11  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  14  * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  16  * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  17  * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18  *
  19  * $Id: siutils.h 330112 2012-04-27 22:31:26Z $
  20  */
  21
  22 #ifndef _siutils_h_
  23 #define _siutils_h_
  24
  25 #if defined(WLC_HIGH) && !defined(WLC_LOW)
  26 #include "bcm_rpc.h"
  27 #endif
  28 /*
  29  * Data structure to export all chip specific common variables
  30  *   public (read-only) portion of siutils handle returned by si_attach()/si_kattach()
  31  */
  32 struct si_pub {
  33         uint    socitype;               /* SOCI_SB, SOCI_AI */
  34
  35         uint    bustype;                /* SI_BUS, PCI_BUS */
  36         uint    buscoretype;            /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
  37         uint    buscorerev;             /* buscore rev */
  38         uint    buscoreidx;             /* buscore index */
  39         int     ccrev;                  /* chip common core rev */
  40         uint32  cccaps;                 /* chip common capabilities */
  41         uint32  cccaps_ext;                     /* chip common capabilities extension */
  42         int     pmurev;                 /* pmu core rev */
  43         uint32  pmucaps;                /* pmu capabilities */
  44         uint    boardtype;              /* board type */
  45         uint    boardrev;               /* board rev */
  46         uint    boardvendor;            /* board vendor */
  47         uint    boardflags;             /* board flags */
  48         uint    boardflags2;            /* board flags2 */
  49         uint    chip;                   /* chip number */
  50         uint    chiprev;                /* chip revision */
  51         uint    chippkg;                /* chip package option */
  52         uint32  chipst;                 /* chip status */
  53         bool    issim;                  /* chip is in simulation or emulation */
  54         uint    socirev;                /* SOC interconnect rev */
  55         bool    pci_pr32414;
  56
  57 #if defined(WLC_HIGH) && !defined(WLC_LOW)
  58         rpc_info_t *rpc;
  59 #endif
  60 #ifdef SI_ENUM_BASE_VARIABLE
  61         uint32  si_enum_base;
  62 #endif /* SI_ENUM_BASE_VARIABLE */
  63 };
  64
  65 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
  66  * for monolithic driver, it is readonly to prevent accident change
  67  */
  68 #if defined(WLC_HIGH) && !defined(WLC_LOW)
  69 typedef struct si_pub si_t;
  70 #else
  71 typedef const struct si_pub si_t;
  72 #endif
  73
  74 #ifdef ATE_BUILD
  75 typedef struct _ate_params {
  76         void* wl;
  77         uint8 gpio_input;
  78         uint8 gpio_output;
  79         bool cmd_proceed;
  80         uint16 cmd_idx;
  81         bool ate_cmd_done;
  82 } ate_params_t;
  83 #endif /* ATE_BUILD */
  84
  85 /*
  86  * Many of the routines below take an 'sih' handle as their first arg.
  87  * Allocate this by calling si_attach().  Free it by calling si_detach().
  88  * At any one time, the sih is logically focused on one particular si core
  89  * (the "current core").
  90  * Use si_setcore() or si_setcoreidx() to change the association to another core.
  91  */
  92 #define SI_OSH          NULL    /* Use for si_kattach when no osh is available */
  93
  94 #define BADIDX          (SI_MAXCORES + 1)
  95
  96 /* clkctl xtal what flags */
  97 #define XTAL                    0x1     /* primary crystal oscillator (2050) */
  98 #define PLL                     0x2     /* main chip pll */
  99
 100 /* clkctl clk mode */
 101 #define CLK_FAST                0       /* force fast (pll) clock */
 102 #define CLK_DYNAMIC             2       /* enable dynamic clock control */
 103
 104 /* GPIO usage priorities */
 105 #define GPIO_DRV_PRIORITY       0       /* Driver */
 106 #define GPIO_APP_PRIORITY       1       /* Application */
 107 #define GPIO_HI_PRIORITY        2       /* Highest priority. Ignore GPIO reservation */
 108
 109 /* GPIO pull up/down */
 110 #define GPIO_PULLUP             0
 111 #define GPIO_PULLDN             1
 112
 113 /* GPIO event regtype */
 114 #define GPIO_REGEVT             0       /* GPIO register event */
 115 #define GPIO_REGEVT_INTMSK      1       /* GPIO register event int mask */
 116 #define GPIO_REGEVT_INTPOL      2       /* GPIO register event int polarity */
 117
 118 /* device path */
 119 #define SI_DEVPATH_BUFSZ        16      /* min buffer size in bytes */
 120
 121 /* SI routine enumeration: to be used by update function with multiple hooks */
 122 #define SI_DOATTACH     1
 123 #define SI_PCIDOWN      2
 124 #define SI_PCIUP        3
 125
 126 #if defined(BCMQT)
 127 #define ISSIM_ENAB(sih) ((sih)->issim)
 128 #else
 129 #define ISSIM_ENAB(sih) 0
 130 #endif
 131
 132 /* PMU clock/power control */
 133 #if defined(BCMPMUCTL)
 134 #define PMUCTL_ENAB(sih)        (BCMPMUCTL)
 135 #else
 136 #define PMUCTL_ENAB(sih)        ((sih)->cccaps & CC_CAP_PMU)
 137 #endif
 138
 139 /* chipcommon clock/power control (exclusive with PMU's) */
 140 #if defined(BCMPMUCTL) && BCMPMUCTL
 141 #define CCCTL_ENAB(sih)         (0)
 142 #define CCPLL_ENAB(sih)         (0)
 143 #else
 144 #define CCCTL_ENAB(sih)         ((sih)->cccaps & CC_CAP_PWR_CTL)
 145 #define CCPLL_ENAB(sih)         ((sih)->cccaps & CC_CAP_PLL_MASK)
 146 #endif
 147
 148 typedef void (*gpio_handler_t)(uint32 stat, void *arg);
 149 /* External BT Coex enable mask */
 150 #define CC_BTCOEX_EN_MASK  0x01
 151 /* External PA enable mask */
 152 #define GPIO_CTRL_EPA_EN_MASK 0x40
 153 /* WL/BT control enable mask */
 154 #define GPIO_CTRL_5_6_EN_MASK 0x60
 155 #define GPIO_CTRL_7_6_EN_MASK 0xC0
 156 #define GPIO_OUT_7_EN_MASK 0x80
 157
 158
 159
 160
 161 /* === exported functions === */
 162 extern si_t *si_attach(uint pcidev, osl_t *osh, void *regs, uint bustype,
 163                        void *sdh, char **vars, uint *varsz);
 164 extern si_t *si_kattach(osl_t *osh);
 165 extern void si_detach(si_t *sih);
 166 extern bool si_pci_war16165(si_t *sih);
 167
 168 extern uint si_corelist(si_t *sih, uint coreid[]);
 169 extern uint si_coreid(si_t *sih);
 170 extern uint si_flag(si_t *sih);
 171 extern uint si_intflag(si_t *sih);
 172 extern uint si_coreidx(si_t *sih);
 173 extern uint si_coreunit(si_t *sih);
 174 extern uint si_corevendor(si_t *sih);
 175 extern uint si_corerev(si_t *sih);
 176 extern void *si_osh(si_t *sih);
 177 extern void si_setosh(si_t *sih, osl_t *osh);
 178 extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val);
 179 extern void *si_coreregs(si_t *sih);
 180 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
 181 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
 182 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
 183 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
 184 #ifdef WLC_HIGH_ONLY
 185 extern bool wlc_bmac_iscoreup(si_t *sih);
 186 #define si_iscoreup(sih)        wlc_bmac_iscoreup(sih)
 187 #else
 188 extern bool si_iscoreup(si_t *sih);
 189 #endif /* __CONFIG_USBAP__ */
 190 extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
 191 extern void *si_setcoreidx(si_t *sih, uint coreidx);
 192 extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
 193 extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val);
 194 extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
 195 extern int si_numaddrspaces(si_t *sih);
 196 extern uint32 si_addrspace(si_t *sih, uint asidx);
 197 extern uint32 si_addrspacesize(si_t *sih, uint asidx);
 198 extern void si_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size);
 199 extern int si_corebist(si_t *sih);
 200 extern void si_core_reset(si_t *sih, uint32 bits, uint32 resetbits);
 201 extern void si_core_disable(si_t *sih, uint32 bits);
 202 extern uint32 si_clock_rate(uint32 pll_type, uint32 n, uint32 m);
 203 extern bool si_read_pmu_autopll(si_t *sih);
 204 extern uint32 si_clock(si_t *sih);
 205 extern uint32 si_alp_clock(si_t *sih);
 206 extern uint32 si_ilp_clock(si_t *sih);
 207 extern void si_pci_setup(si_t *sih, uint coremask);
 208 extern void si_pcmcia_init(si_t *sih);
 209 extern void si_setint(si_t *sih, int siflag);
 210 extern bool si_backplane64(si_t *sih);
 211 extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
 212         void *intrsenabled_fn, void *intr_arg);
 213 extern void si_deregister_intr_callback(si_t *sih);
 214 extern void si_clkctl_init(si_t *sih);
 215 extern uint16 si_clkctl_fast_pwrup_delay(si_t *sih);
 216 extern bool si_clkctl_cc(si_t *sih, uint mode);
 217 extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
 218 extern uint32 si_gpiotimerval(si_t *sih, uint32 mask, uint32 val);
 219 extern void si_btcgpiowar(si_t *sih);
 220 extern bool si_deviceremoved(si_t *sih);
 221 extern uint32 si_socram_size(si_t *sih);
 222 extern uint32 si_socdevram_size(si_t *sih);
 223 extern void si_socdevram(si_t *sih, bool set, uint8 *ennable, uint8 *protect, uint8 *remap);
 224 extern bool si_socdevram_pkg(si_t *sih);
 225 extern bool si_socdevram_remap_isenb(si_t *sih);
 226 extern uint32 si_socdevram_remap_size(si_t *sih);
 227
 228 extern void si_watchdog(si_t *sih, uint ticks);
 229 extern void si_watchdog_ms(si_t *sih, uint32 ms);
 230 extern uint32 si_watchdog_msticks(void);
 231 extern void *si_gpiosetcore(si_t *sih);
 232 extern uint32 si_gpiocontrol(si_t *sih, uint32 mask, uint32 val, uint8 priority);
 233 extern uint32 si_gpioouten(si_t *sih, uint32 mask, uint32 val, uint8 priority);
 234 extern uint32 si_gpioout(si_t *sih, uint32 mask, uint32 val, uint8 priority);
 235 extern uint32 si_gpioin(si_t *sih);
 236 extern uint32 si_gpiointpolarity(si_t *sih, uint32 mask, uint32 val, uint8 priority);
 237 extern uint32 si_gpiointmask(si_t *sih, uint32 mask, uint32 val, uint8 priority);
 238 extern uint32 si_gpioled(si_t *sih, uint32 mask, uint32 val);
 239 extern uint32 si_gpioreserve(si_t *sih, uint32 gpio_num, uint8 priority);
 240 extern uint32 si_gpiorelease(si_t *sih, uint32 gpio_num, uint8 priority);
 241 extern uint32 si_gpiopull(si_t *sih, bool updown, uint32 mask, uint32 val);
 242 extern uint32 si_gpioevent(si_t *sih, uint regtype, uint32 mask, uint32 val);
 243 extern uint32 si_gpio_int_enable(si_t *sih, bool enable);
 244
 245 /* GPIO event handlers */
 246 extern void *si_gpio_handler_register(si_t *sih, uint32 e, bool lev, gpio_handler_t cb, void *arg);
 247 extern void si_gpio_handler_unregister(si_t *sih, void* gpioh);
 248 extern void si_gpio_handler_process(si_t *sih);
 249
 250 /* Wake-on-wireless-LAN (WOWL) */
 251 extern bool si_pci_pmecap(si_t *sih);
 252 struct osl_info;
 253 extern bool si_pci_fastpmecap(struct osl_info *osh);
 254 extern bool si_pci_pmestat(si_t *sih);
 255 extern void si_pci_pmeclr(si_t *sih);
 256 extern void si_pci_pmeen(si_t *sih);
 257 extern void si_pci_pmestatclr(si_t *sih);
 258 extern uint si_pcie_readreg(void *sih, uint addrtype, uint offset);
 259
 260
 261 extern uint16 si_d11_devid(si_t *sih);
 262 extern int si_corepciid(si_t *sih, uint func, uint16 *pcivendor, uint16 *pcidevice,
 263         uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif, uint8 *pciheader);
 264
 265 #if defined(BCMECICOEX)
 266 extern bool si_eci(si_t *sih);
 267 extern int si_eci_init(si_t *sih);
 268 extern void si_eci_notify_bt(si_t *sih, uint32 mask, uint32 val, bool interrupt);
 269 extern bool si_seci(si_t *sih);
 270 extern void* si_seci_init(si_t *sih, uint8 seci_mode);
 271 extern void si_seci_down(si_t *sih);
 272 extern void si_seci_upd(si_t *sih, bool enable);
 273 #else
 274 #define si_eci(sih) 0
 275 static INLINE void * si_eci_init(si_t *sih) {return NULL;}
 276 #define si_eci_notify_bt(sih, type, val)  (0)
 277 #define si_seci(sih) 0
 278 #define si_seci_upd(sih, a)     do {} while (0)
 279 static INLINE void * si_seci_init(si_t *sih, uint8 use_seci) {return NULL;}
 280 #define si_seci_down(sih) do {} while (0)
 281 #endif /* BCMECICOEX */
 282
 283 /* OTP status */
 284 extern bool si_is_otp_disabled(si_t *sih);
 285 extern bool si_is_otp_powered(si_t *sih);
 286 extern void si_otp_power(si_t *sih, bool on);
 287
 288 /* SPROM availability */
 289 extern bool si_is_sprom_available(si_t *sih);
 290 extern bool si_is_sprom_enabled(si_t *sih);
 291 extern void si_sprom_enable(si_t *sih, bool enable);
 292 #ifdef SI_SPROM_PROBE
 293 extern void si_sprom_init(si_t *sih);
 294 #endif /* SI_SPROM_PROBE */
 295
 296 /* OTP/SROM CIS stuff */
 297 extern int si_cis_source(si_t *sih);
 298 #define CIS_DEFAULT     0
 299 #define CIS_SROM        1
 300 #define CIS_OTP         2
 301
 302 /* Fab-id information */
 303 #define DEFAULT_FAB     0x0     /* Original/first fab used for this chip */
 304 #define CSM_FAB7        0x1     /* CSM Fab7 chip */
 305 #define TSMC_FAB12      0x2     /* TSMC Fab12/Fab14 chip */
 306 #define SMIC_FAB4       0x3     /* SMIC Fab4 chip */
 307 extern int BCMINITFN(si_otp_fabid)(si_t *sih, uint16 *fabid, bool rw);
 308 extern uint16 BCMINITFN(si_fabid)(si_t *sih);
 309
 310 /*
 311  * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
 312  * The returned path is NULL terminated and has trailing '/'.
 313  * Return 0 on success, nonzero otherwise.
 314  */
 315 extern int si_devpath(si_t *sih, char *path, int size);
 316 /* Read variable with prepending the devpath to the name */
 317 extern char *si_getdevpathvar(si_t *sih, const char *name);
 318 extern int si_getdevpathintvar(si_t *sih, const char *name);
 319 extern char *si_coded_devpathvar(si_t *sih, char *varname, int var_len, const char *name);
 320
 321
 322 extern uint8 si_pcieclkreq(si_t *sih, uint32 mask, uint32 val);
 323 extern uint32 si_pcielcreg(si_t *sih, uint32 mask, uint32 val);
 324 extern void si_pcie_set_error_injection(si_t *sih, uint32 mode);
 325 extern void si_war42780_clkreq(si_t *sih, bool clkreq);
 326 extern void si_pci_down(si_t *sih);
 327 extern void si_pci_up(si_t *sih);
 328 #ifdef WLC_HIGH_ONLY
 329 #define si_pci_sleep(sih)       do { ASSERT(0); } while (0)
 330 #define si_pcie_war_ovr_update(sih, aspm)       do { ASSERT(0); } while (0)
 331 #define si_pcie_power_save_enable(sih, up)      do { ASSERT(0); } while (0)
 332 #else
 333 extern void si_pci_sleep(si_t *sih);
 334 extern void si_pcie_war_ovr_update(si_t *sih, uint8 aspm);
 335 extern void si_pcie_power_save_enable(si_t *sih, bool enable);
 336 #endif /* __CONFIG_USBAP__ */
 337 extern void si_pcie_extendL1timer(si_t *sih, bool extend);
 338 extern int si_pci_fixcfg(si_t *sih);
 339 extern bool si_ldo_war(si_t *sih, uint devid);
 340 extern void si_chippkg_set(si_t *sih, uint);
 341
 342 extern void si_chipcontrl_btshd0_4331(si_t *sih, bool on);
 343 extern void si_chipcontrl_restore(si_t *sih, uint32 val);
 344 extern uint32 si_chipcontrl_read(si_t *sih);
 345 extern void si_chipcontrl_epa4331(si_t *sih, bool on);
 346 extern void si_chipcontrl_epa4331_wowl(si_t *sih, bool enter_wowl);
 347 extern void si_chipcontrl_srom4360(si_t *sih, bool on);
 348 /* Enable BT-COEX & Ex-PA for 4313 */
 349 extern void si_epa_4313war(si_t *sih);
 350 extern void si_btc_enable_chipcontrol(si_t *sih);
 351 /* BT/WL selection for 4313 bt combo >= P250 boards */
 352 extern void si_btcombo_p250_4313_war(si_t *sih);
 353 extern void si_btcombo_43228_war(si_t *sih);
 354 extern void si_clk_pmu_htavail_set(si_t *sih, bool set_clear);
 355 extern uint si_pll_reset(si_t *sih);
 356 /* === debug routines === */
 357
 358 extern bool si_taclear(si_t *sih, bool details);
 359
 360 #ifdef BCMDBG
 361 extern void si_view(si_t *sih, bool verbose);
 362 extern void si_viewall(si_t *sih, bool verbose);
 363 #endif
 364
 365 #if defined(BCMDBG)
 366 struct bcmstrbuf;
 367 extern void si_dumpregs(si_t *sih, struct bcmstrbuf *b);
 368 #endif
 369
 370 extern uint32 si_pciereg(si_t *sih, uint32 offset, uint32 mask, uint32 val, uint type);
 371 extern uint32 si_pcieserdesreg(si_t *sih, uint32 mdioslave, uint32 offset, uint32 mask, uint32 val);
 372 extern void si_pcie_set_request_size(si_t *sih, uint16 size);
 373 extern uint16 si_pcie_get_request_size(si_t *sih);
 374 extern void si_pcie_set_maxpayload_size(si_t *sih, uint16 size);
 375 extern uint16 si_pcie_get_maxpayload_size(si_t *sih);
 376 extern uint16 si_pcie_get_ssid(si_t *sih);
 377 extern uint32 si_pcie_get_bar0(si_t *sih);
 378 extern int si_pcie_configspace_cache(si_t *sih);
 379 extern int si_pcie_configspace_restore(si_t *sih);
 380 extern int si_pcie_configspace_get(si_t *sih, uint8 *buf, uint size);
 381
 382 #ifndef DONGLEBUILD
 383 char *si_getnvramflvar(si_t *sih, const char *name);
 384 #endif /* DONGLEBUILD */
 385
 386 extern void BCMATTACHFN(si_muxenab)(si_t *sih, uint32 w);
 387
 388
 389 extern void si_gci_set_functionsel(si_t *sih, uint32 pin, uint8 fnsel);
 390 extern uint8 si_gci_get_chipctrlreg_idx(uint32 pin, uint32 *regidx, uint32 *pos);
 391 extern uint32 si_gci_chipcontrol(si_t *sih, uint reg, uint32 mask, uint32 val);
 392 extern int si_set_sromctl(si_t *sih, uint32 value);
 393 extern uint32 si_get_sromctl(si_t *sih);
 394
 395 #endif  /* _siutils_h_ */