tools/brcm/K24/hndtools-mipsel-uclibc-4.2.4/include/asm-mips/processor.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994 Waldorf GMBH
   7  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
   8  * Copyright (C) 1996 Paul M. Antoine
   9  * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
  10  */
  11 #ifndef _ASM_PROCESSOR_H
  12 #define _ASM_PROCESSOR_H
  13
  14 #include <linux/config.h>
  15 #include <linux/cache.h>
  16 #include <asm/isadep.h>
  17
  18 /*
  19  * Return current * instruction pointer ("program counter").
  20  */
  21 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
  22
  23 #ifndef __ASSEMBLY__
  24 #include <linux/smp.h>
  25 #include <linux/threads.h>
  26
  27 #include <asm/cachectl.h>
  28 #include <asm/cpu.h>
  29 #include <asm/mipsregs.h>
  30 #include <asm/reg.h>
  31 #include <asm/system.h>
  32
  33 /*
  34  * Descriptor for a cache
  35  */
  36 struct cache_desc {
  37         unsigned short linesz;  /* Size of line in bytes */
  38         unsigned short ways;    /* Number of ways */
  39         unsigned short sets;    /* Number of lines per set */
  40         unsigned int waysize;   /* Bytes per way */
  41         unsigned int waybit;    /* Bits to select in a cache set */
  42         unsigned int flags;     /* Flags describing cache properties */
  43 };
  44
  45 /*
  46  * Flag definitions
  47  */
  48 #define MIPS_CACHE_NOT_PRESENT  0x00000001
  49 #define MIPS_CACHE_VTAG         0x00000002      /* Virtually tagged cache */
  50 #define MIPS_CACHE_ALIASES      0x00000004      /* Cache could have aliases */
  51 #define MIPS_CACHE_IC_F_DC      0x00000008      /* Ic can refill from D-cache */
  52
  53 struct cpuinfo_mips {
  54         unsigned long udelay_val;
  55         unsigned long *pgd_quick;
  56         unsigned long *pte_quick;
  57         unsigned long pgtable_cache_sz;
  58         unsigned long asid_cache;
  59         /*
  60          * Capability and feature descriptor structure for MIPS CPU
  61          */
  62         unsigned long options;
  63         unsigned long ases;
  64         unsigned int processor_id;
  65         unsigned int fpu_id;
  66         unsigned int cputype;
  67         int isa_level;
  68         int tlbsize;
  69         struct cache_desc icache;       /* Primary I-cache */
  70         struct cache_desc dcache;       /* Primary D or combined I/D cache */
  71         struct cache_desc scache;       /* Secondary cache */
  72         struct cache_desc tcache;       /* Tertiary/split secondary cache */
  73 } __attribute__((aligned(SMP_CACHE_BYTES)));
  74
  75 /*
  76  * Assumption: Options of CPU 0 are a superset of all processors.
  77  * This is true for all known MIPS systems.
  78  */
  79 #define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
  80 #define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
  81 #define cpu_has_4ktlb           (cpu_data[0].options & MIPS_CPU_4KTLB)
  82 #define cpu_has_fpu             (cpu_data[0].options & MIPS_CPU_FPU)
  83 #define cpu_has_32fpr           (cpu_data[0].options & MIPS_CPU_32FPR)
  84 #define cpu_has_counter         (cpu_data[0].options & MIPS_CPU_COUNTER)
  85 #define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
  86 #define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
  87 #define cpu_has_vce             (cpu_data[0].options & MIPS_CPU_VCE)
  88 #define cpu_has_cache_cdex_p    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
  89 #define cpu_has_cache_cdex_s    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
  90 #define cpu_has_prefetch        (cpu_data[0].options & MIPS_CPU_PREFETCH)
  91 #define cpu_has_mcheck          (cpu_data[0].options & MIPS_CPU_MCHECK)
  92 #define cpu_has_ejtag           (cpu_data[0].options & MIPS_CPU_EJTAG)
  93 #define cpu_has_nofpuex         (cpu_data[0].options & MIPS_CPU_NOFPUEX)
  94 #define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
  95 #define cpu_has_mips16          (cpu_data[0].ases & MIPS_ASE_MIPS16)
  96 #define cpu_has_mdmx            (cpu_data[0].ases & MIPS_ASE_MDMX)
  97 #define cpu_has_mips3d          (cpu_data[0].ases & MIPS_ASE_MIPS3D)
  98 #define cpu_has_smartmips       (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
  99 #define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
 100 #define cpu_has_mipsmt          (cpu_data[0].ases & MIPS_ASE_MIPSMT)
 101 #define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
 102 #define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
 103 #define cpu_has_ic_fills_f_dc   (cpu_data[0].dcache.flags & MIPS_CACHE_IC_F_DC)
 104 #define cpu_has_64bits          (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 105 #define cpu_has_64bit_zero_reg  (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
 106 #define cpu_has_64bit_gp_regs   0
 107 #define cpu_has_64bit_addresses 0
 108 #define cpu_has_subset_pcaches  (cpu_data[0].options & MIPS_CPU_SUBSET_CACHES)
 109
 110 #define cpu_dcache_line_size()  current_cpu_data.dcache.linesz
 111 #define cpu_icache_line_size()  current_cpu_data.icache.linesz
 112 #define cpu_scache_line_size()  current_cpu_data.scache.linesz
 113
 114 extern struct cpuinfo_mips cpu_data[];
 115 #define current_cpu_data cpu_data[smp_processor_id()]
 116
 117 extern void cpu_probe(void);
 118 extern void cpu_report(void);
 119
 120 /*
 121  * System setup and hardware flags..
 122  */
 123 extern void (*cpu_wait)(void);
 124
 125 extern unsigned int vced_count, vcei_count;
 126
 127 /*
 128  * Bus types (default is ISA, but people can check others with these..)
 129  */
 130 #ifdef CONFIG_EISA
 131 extern int EISA_bus;
 132 #else
 133 #define EISA_bus (0)
 134 #endif
 135
 136 #define MCA_bus 0
 137 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
 138
 139 /*
 140  * User space process size: 2GB. This is hardcoded into a few places,
 141  * so don't change it unless you know what you are doing.  TASK_SIZE
 142  * for a 64 bit kernel expandable to 8192EB, of which the current MIPS
 143  * implementations will "only" be able to use 1TB ...
 144  */
 145 #define TASK_SIZE       0x7fff8000UL
 146
 147 /* This decides where the kernel will search for a free chunk of vm
 148  * space during mmap's.
 149  */
 150 #define TASK_UNMAPPED_BASE      (TASK_SIZE / 3)
 151
 152 /*
 153  * Size of io_bitmap in longwords: 32 is ports 0-0x3ff.
 154  */
 155 #define IO_BITMAP_SIZE  32
 156
 157 #define NUM_FPU_REGS    32
 158
 159 struct mips_fpu_hard_struct {
 160         double fp_regs[NUM_FPU_REGS];
 161         unsigned int control;
 162 };
 163
 164 /*
 165  * It would be nice to add some more fields for emulator statistics, but there
 166  * are a number of fixed offsets in offset.h and elsewhere that would have to
 167  * be recalculated by hand.  So the additional information will be private to
 168  * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
 169  */
 170 typedef u64 fpureg_t;
 171 struct mips_fpu_soft_struct {
 172         fpureg_t        regs[NUM_FPU_REGS];
 173         unsigned int    sr;
 174 };
 175
 176 union mips_fpu_union {
 177         struct mips_fpu_hard_struct hard;
 178         struct mips_fpu_soft_struct soft;
 179 };
 180
 181 #define INIT_FPU { \
 182         {{0,},} \
 183 }
 184
 185 typedef struct {
 186         unsigned long seg;
 187 } mm_segment_t;
 188
 189 /*
 190  * If you change thread_struct remember to change the #defines below too!
 191  */
 192 struct thread_struct {
 193         /* Saved main processor registers. */
 194         unsigned long reg16;
 195         unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
 196         unsigned long reg29, reg30, reg31;
 197
 198         /* Saved cp0 stuff. */
 199         unsigned long cp0_status;
 200
 201         /* Saved fpu/fpu emulator stuff. */
 202         union mips_fpu_union fpu;
 203
 204         /* Other stuff associated with the thread. */
 205         unsigned long cp0_badvaddr;     /* Last user fault */
 206         unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
 207         unsigned long error_code;
 208         unsigned long trap_no;
 209 #define MF_FIXADE       1               /* Fix address errors in software */
 210 #define MF_LOGADE       2               /* Log address errors to syslog */
 211         unsigned long mflags;
 212         mm_segment_t current_ds;
 213         unsigned long irix_trampoline;  /* Wheee... */
 214         unsigned long irix_oldctx;
 215 };
 216
 217 #endif /* !__ASSEMBLY__ */
 218
 219 #define INIT_THREAD  { \
 220         /* \
 221          * saved main processor registers \
 222          */ \
 223         0, 0, 0, 0, 0, 0, 0, 0, \
 224                        0, 0, 0, \
 225         /* \
 226          * saved cp0 stuff \
 227          */ \
 228         0, \
 229         /* \
 230          * saved fpu/fpu emulator stuff \
 231          */ \
 232         INIT_FPU, \
 233         /* \
 234          * Other stuff associated with the process \
 235          */ \
 236         0, 0, 0, 0, \
 237         /* \
 238          * For now the default is to fix address errors \
 239          */ \
 240         MF_FIXADE, { 0 }, 0, 0 \
 241 }
 242
 243 #ifdef __KERNEL__
 244
 245 #define KERNEL_STACK_SIZE       0x2000
 246
 247 #ifndef __ASSEMBLY__
 248
 249 /* Free all resources held by a thread. */
 250 #define release_thread(thread) do { } while(0)
 251
 252 extern int arch_kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
 253
 254 /* Copy and release all segment info associated with a VM */
 255 #define copy_segments(p, mm) do { } while(0)
 256 #define release_segments(mm) do { } while(0)
 257
 258 struct mips_frame_info {
 259         int frame_offset;
 260         int pc_offset;
 261 };
 262 extern struct mips_frame_info schedule_frame;
 263 /*
 264  * Return saved PC of a blocked thread.
 265  */
 266 static inline unsigned long thread_saved_pc(struct thread_struct *t)
 267 {
 268         extern void ret_from_fork(void);
 269
 270         /* New born processes are a special case */
 271         if (t->reg31 == (unsigned long) ret_from_fork)
 272                 return t->reg31;
 273
 274         if (schedule_frame.pc_offset < 0)
 275                 return 0;
 276         return ((unsigned long *)t->reg29)[schedule_frame.pc_offset];
 277 }
 278
 279 /*
 280  * Do necessary setup to start up a newly executed thread.
 281  */
 282 extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
 283
 284 struct task_struct;
 285 unsigned long get_wchan(struct task_struct *p);
 286
 287 #define __PT_REG(reg) ((long)&((struct pt_regs *)0)->reg - sizeof(struct pt_regs))
 288 #define __KSTK_TOS(tsk) ((unsigned long)(tsk) + KERNEL_STACK_SIZE - \
 289                         32 - sizeof(struct pt_regs))
 290 #define KSTK_EIP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_epc)))
 291 #define KSTK_ESP(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(regs[29])))
 292 #define KSTK_STATUS(tsk) (*(unsigned long *)(__KSTK_TOS(tsk) + __PT_REG(cp0_status)))
 293
 294 /* Allocation and freeing of basic task resources. */
 295 /*
 296  * NOTE! The task struct and the stack go together
 297  */
 298 #define THREAD_ORDER            (PAGE_SHIFT >= 14 ? 0 : 1)
 299 #define THREAD_SIZE             (PAGE_SIZE << THREAD_ORDER)
 300 #define THREAD_MASK             (THREAD_SIZE - 1UL)
 301 #define alloc_task_struct() \
 302         ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
 303 #define free_task_struct(p)     free_pages((unsigned long)(p),1)
 304 #define get_task_struct(tsk)      atomic_inc(&virt_to_page(tsk)->count)
 305
 306 #define init_task       (init_task_union.task)
 307 #define init_stack      (init_task_union.stack)
 308
 309 #define cpu_relax()     barrier()
 310
 311 #endif /* !__ASSEMBLY__ */
 312 #endif /* __KERNEL__ */
 313
 314 /*
 315  * Return_address is a replacement for __builtin_return_address(count)
 316  * which on certain architectures cannot reasonably be implemented in GCC
 317  * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
 318  * Note that __builtin_return_address(x>=1) is forbidden because GCC
 319  * aborts compilation on some CPUs.  It's simply not possible to unwind
 320  * some CPU's stackframes.
 321  *
 322  * __builtin_return_address works only for non-leaf functions.  We avoid the
 323  * overhead of a function call by forcing the compiler to save the return
 324  * address register on the stack.
 325  */
 326 #define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
 327
 328 #endif /* _ASM_PROCESSOR_H */