release/src-rt/linux/linux-2.6/drivers/usb/host/ehci.h

   1 /*
   2  * Copyright (c) 2001-2002 by David Brownell
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms of the GNU General Public License as published by the
   6  * Free Software Foundation; either version 2 of the License, or (at your
   7  * option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  11  * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software Foundation,
  16  * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  17  */
  18
  19 #ifndef __LINUX_EHCI_HCD_H
  20 #define __LINUX_EHCI_HCD_H
  21
  22 #ifdef  __KERNEL__
  23 #ifndef BIT
  24 #define BIT(nr) (1UL << (nr))
  25 #endif
  26 #endif
  27
  28 /* definitions used for the EHCI driver */
  29
  30 /*
  31  * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
  32  * __leXX (normally) or __beXX (given EHCI_BIG_ENDIAN_DESC), depending on
  33  * the host controller implementation.
  34  *
  35  * To facilitate the strongest possible byte-order checking from "sparse"
  36  * and so on, we use __leXX unless that's not practical.
  37  */
  38 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
  39 typedef __u32 __bitwise __hc32;
  40 typedef __u16 __bitwise __hc16;
  41 #else
  42 #define __hc32  __le32
  43 #define __hc16  __le16
  44 #endif
  45
  46 /* statistics can be kept for for tuning/monitoring */
  47 struct ehci_stats {
  48         /* irq usage */
  49         unsigned long           normal;
  50         unsigned long           error;
  51         unsigned long           reclaim;
  52         unsigned long           lost_iaa;
  53
  54         /* termination of urbs from core */
  55         unsigned long           complete;
  56         unsigned long           unlink;
  57 };
  58
  59 /* ehci_hcd->lock guards shared data against other CPUs:
  60  *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
  61  *   usb_host_endpoint: hcpriv
  62  *   ehci_qh:   qh_next, qtd_list
  63  *   ehci_qtd:  qtd_list
  64  *
  65  * Also, hold this lock when talking to HC registers or
  66  * when updating hw_* fields in shared qh/qtd/... structures.
  67  */
  68
  69 #define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
  70
  71 struct ehci_hcd {                       /* one per controller */
  72         /* glue to PCI and HCD framework */
  73         struct ehci_caps __iomem *caps;
  74         struct ehci_regs __iomem *regs;
  75         struct ehci_dbg_port __iomem *debug;
  76
  77         __u32                   hcs_params;     /* cached register copy */
  78         spinlock_t              lock;
  79
  80         /* async schedule support */
  81         struct ehci_qh          *async;
  82         struct ehci_qh          *reclaim;
  83         unsigned                scanning : 1;
  84
  85         /* periodic schedule support */
  86 #define DEFAULT_I_TDPS          1024            /* some HCs can do less */
  87         unsigned                periodic_size;
  88         __hc32                  *periodic;      /* hw periodic table */
  89         dma_addr_t              periodic_dma;
  90         unsigned                i_thresh;       /* uframes HC might cache */
  91
  92         union ehci_shadow       *pshadow;       /* mirror hw periodic table */
  93         int                     next_uframe;    /* scan periodic, start here */
  94         unsigned                periodic_sched; /* periodic activity count */
  95
  96         /* list of itds & sitds completed while clock_frame was still active */
  97         struct list_head        cached_itd_list;
  98         struct list_head        cached_sitd_list;
  99         unsigned                clock_frame;
 100
 101         /* per root hub port */
 102         unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
 103
 104         /* bit vectors (one bit per port) */
 105         unsigned long           bus_suspended;          /* which ports were
 106                         already suspended at the start of a bus suspend */
 107         unsigned long           companion_ports;        /* which ports are
 108                         dedicated to the companion controller */
 109         unsigned long           owned_ports;            /* which ports are
 110                         owned by the companion during a bus suspend */
 111         unsigned long           port_c_suspend;         /* which ports have
 112                         the change-suspend feature turned on */
 113         unsigned long           suspended_ports;        /* which ports are
 114                         suspended */
 115
 116         /* per-HC memory pools (could be per-bus, but ...) */
 117         struct dma_pool         *qh_pool;       /* qh per active urb */
 118         struct dma_pool         *qtd_pool;      /* one or more per qh */
 119         struct dma_pool         *itd_pool;      /* itd per iso urb */
 120         struct dma_pool         *sitd_pool;     /* sitd per split iso urb */
 121
 122         struct timer_list       iaa_watchdog;
 123         struct timer_list       watchdog;
 124         unsigned long           actions;
 125         unsigned                stamp;
 126         unsigned                random_frame;
 127         unsigned long           next_statechange;
 128         ktime_t                 last_periodic_enable;
 129         u32                     command;
 130
 131         /* SILICON QUIRKS */
 132         unsigned                no_selective_suspend:1;
 133         unsigned                has_fsl_port_bug:1; /* FreeScale */
 134         unsigned                big_endian_mmio:1;
 135         unsigned                big_endian_desc:1;
 136         unsigned                need_io_watchdog:1;
 137         unsigned                broken_periodic:1;
 138         unsigned                fs_i_thresh:1;  /* Intel iso scheduling */
 139
 140         u8                      sbrn;           /* packed release number */
 141
 142         /* irq statistics */
 143 #ifdef EHCI_STATS
 144         struct ehci_stats       stats;
 145 #       define COUNT(x) do { (x)++; } while (0)
 146 #else
 147 #       define COUNT(x) do {} while (0)
 148 #endif
 149
 150         /* debug files */
 151 #ifdef DEBUG
 152         struct dentry           *debug_dir;
 153 #endif
 154 };
 155
 156 /* convert between an HCD pointer and the corresponding EHCI_HCD */
 157 static inline struct ehci_hcd *hcd_to_ehci (struct usb_hcd *hcd)
 158 {
 159         return (struct ehci_hcd *) (hcd->hcd_priv);
 160 }
 161 static inline struct usb_hcd *ehci_to_hcd (struct ehci_hcd *ehci)
 162 {
 163         return container_of ((void *) ehci, struct usb_hcd, hcd_priv);
 164 }
 165
 166
 167 static inline void
 168 iaa_watchdog_start(struct ehci_hcd *ehci)
 169 {
 170         WARN_ON(timer_pending(&ehci->iaa_watchdog));
 171         mod_timer(&ehci->iaa_watchdog,
 172                         jiffies + msecs_to_jiffies(EHCI_IAA_MSECS));
 173 }
 174
 175 static inline void iaa_watchdog_done(struct ehci_hcd *ehci)
 176 {
 177         del_timer(&ehci->iaa_watchdog);
 178 }
 179
 180 enum ehci_timer_action {
 181         TIMER_IO_WATCHDOG,
 182         TIMER_ASYNC_SHRINK,
 183         TIMER_ASYNC_OFF,
 184 };
 185
 186 static inline void
 187 timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
 188 {
 189         clear_bit (action, &ehci->actions);
 190 }
 191
 192 static void free_cached_lists(struct ehci_hcd *ehci);
 193
 194 /*-------------------------------------------------------------------------*/
 195
 196 /* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
 197
 198 /* Section 2.2 Host Controller Capability Registers */
 199 struct ehci_caps {
 200         /* these fields are specified as 8 and 16 bit registers,
 201          * but some hosts can't perform 8 or 16 bit PCI accesses.
 202          */
 203         u32             hc_capbase;
 204 #define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
 205 #define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
 206         u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
 207 #define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
 208 #define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
 209 #define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
 210 #define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
 211 #define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
 212 #define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
 213 #define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
 214
 215         u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
 216 #define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
 217 #define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
 218 #define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
 219 #define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
 220 #define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
 221 #define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
 222         u8              portroute [8];   /* nibbles for routing - offset 0xC */
 223 } __attribute__ ((packed));
 224
 225
 226 /* Section 2.3 Host Controller Operational Registers */
 227 struct ehci_regs {
 228
 229         /* USBCMD: offset 0x00 */
 230         u32             command;
 231 /* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
 232 #define CMD_PARK        (1<<11)         /* enable "park" on async qh */
 233 #define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
 234 #define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
 235 #define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
 236 #define CMD_ASE         (1<<5)          /* async schedule enable */
 237 #define CMD_PSE         (1<<4)          /* periodic schedule enable */
 238 /* 3:2 is periodic frame list size */
 239 #define CMD_RESET       (1<<1)          /* reset HC not bus */
 240 #define CMD_RUN         (1<<0)          /* start/stop HC */
 241
 242         /* USBSTS: offset 0x04 */
 243         u32             status;
 244 #define STS_ASS         (1<<15)         /* Async Schedule Status */
 245 #define STS_PSS         (1<<14)         /* Periodic Schedule Status */
 246 #define STS_RECL        (1<<13)         /* Reclamation */
 247 #define STS_HALT        (1<<12)         /* Not running (any reason) */
 248 /* some bits reserved */
 249         /* these STS_* flags are also intr_enable bits (USBINTR) */
 250 #define STS_IAA         (1<<5)          /* Interrupted on async advance */
 251 #define STS_FATAL       (1<<4)          /* such as some PCI access errors */
 252 #define STS_FLR         (1<<3)          /* frame list rolled over */
 253 #define STS_PCD         (1<<2)          /* port change detect */
 254 #define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
 255 #define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
 256
 257         /* USBINTR: offset 0x08 */
 258         u32             intr_enable;
 259
 260         /* FRINDEX: offset 0x0C */
 261         u32             frame_index;    /* current microframe number */
 262         /* CTRLDSSEGMENT: offset 0x10 */
 263         u32             segment;        /* address bits 63:32 if needed */
 264         /* PERIODICLISTBASE: offset 0x14 */
 265         u32             frame_list;     /* points to periodic list */
 266         /* ASYNCLISTADDR: offset 0x18 */
 267         u32             async_next;     /* address of next async queue head */
 268
 269         u32             reserved [9];
 270
 271         /* CONFIGFLAG: offset 0x40 */
 272         u32             configured_flag;
 273 #define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
 274
 275         /* PORTSC: offset 0x44 */
 276         u32             port_status [0];        /* up to N_PORTS */
 277 /* 31:23 reserved */
 278 #define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
 279 #define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
 280 #define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
 281 /* 19:16 for port testing */
 282 #define PORT_LED_OFF    (0<<14)
 283 #define PORT_LED_AMBER  (1<<14)
 284 #define PORT_LED_GREEN  (2<<14)
 285 #define PORT_LED_MASK   (3<<14)
 286 #define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
 287 #define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
 288 #define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
 289 /* 11:10 for detecting lowspeed devices (reset vs release ownership) */
 290 /* 9 reserved */
 291 #define PORT_RESET      (1<<8)          /* reset port */
 292 #define PORT_SUSPEND    (1<<7)          /* suspend port */
 293 #define PORT_RESUME     (1<<6)          /* resume it */
 294 #define PORT_OCC        (1<<5)          /* over current change */
 295 #define PORT_OC         (1<<4)          /* over current active */
 296 #define PORT_PEC        (1<<3)          /* port enable change */
 297 #define PORT_PE         (1<<2)          /* port enable */
 298 #define PORT_CSC        (1<<1)          /* connect status change */
 299 #define PORT_CONNECT    (1<<0)          /* device connected */
 300 #define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
 301 } __attribute__ ((packed));
 302
 303 #define USBMODE         0x68            /* USB Device mode */
 304 #define USBMODE_SDIS    (1<<3)          /* Stream disable */
 305 #define USBMODE_BE      (1<<2)          /* BE/LE endianness select */
 306 #define USBMODE_CM_HC   (3<<0)          /* host controller mode */
 307 #define USBMODE_CM_IDLE (0<<0)          /* idle state */
 308
 309 /* Appendix C, Debug port ... intended for use with special "debug devices"
 310  * that can help if there's no serial console.  (nonstandard enumeration.)
 311  */
 312 struct ehci_dbg_port {
 313         u32     control;
 314 #define DBGP_OWNER      (1<<30)
 315 #define DBGP_ENABLED    (1<<28)
 316 #define DBGP_DONE       (1<<16)
 317 #define DBGP_INUSE      (1<<10)
 318 #define DBGP_ERRCODE(x) (((x)>>7)&0x07)
 319 #       define DBGP_ERR_BAD     1
 320 #       define DBGP_ERR_SIGNAL  2
 321 #define DBGP_ERROR      (1<<6)
 322 #define DBGP_GO         (1<<5)
 323 #define DBGP_OUT        (1<<4)
 324 #define DBGP_LEN(x)     (((x)>>0)&0x0f)
 325         u32     pids;
 326 #define DBGP_PID_GET(x)         (((x)>>16)&0xff)
 327 #define DBGP_PID_SET(data,tok)  (((data)<<8)|(tok))
 328         u32     data03;
 329         u32     data47;
 330         u32     address;
 331 #define DBGP_EPADDR(dev,ep)     (((dev)<<8)|(ep))
 332 } __attribute__ ((packed));
 333
 334 /*-------------------------------------------------------------------------*/
 335
 336 #define QTD_NEXT(ehci, dma)     cpu_to_hc32(ehci, (u32)dma)
 337
 338 /*
 339  * EHCI Specification 0.95 Section 3.5
 340  * QTD: describe data transfer components (buffer, direction, ...)
 341  * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
 342  *
 343  * These are associated only with "QH" (Queue Head) structures,
 344  * used with control, bulk, and interrupt transfers.
 345  */
 346 struct ehci_qtd {
 347         /* first part defined by EHCI spec */
 348         __hc32                  hw_next;        /* see EHCI 3.5.1 */
 349         __hc32                  hw_alt_next;    /* see EHCI 3.5.2 */
 350         __hc32                  hw_token;       /* see EHCI 3.5.3 */
 351 #define QTD_TOGGLE      (1 << 31)       /* data toggle */
 352 #define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
 353 #define QTD_IOC         (1 << 15)       /* interrupt on complete */
 354 #define QTD_CERR(tok)   (((tok)>>10) & 0x3)
 355 #define QTD_PID(tok)    (((tok)>>8) & 0x3)
 356 #define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
 357 #define QTD_STS_HALT    (1 << 6)        /* halted on error */
 358 #define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
 359 #define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
 360 #define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
 361 #define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
 362 #define QTD_STS_STS     (1 << 1)        /* split transaction state */
 363 #define QTD_STS_PING    (1 << 0)        /* issue PING? */
 364
 365 #define ACTIVE_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_ACTIVE)
 366 #define HALT_BIT(ehci)          cpu_to_hc32(ehci, QTD_STS_HALT)
 367 #define STATUS_BIT(ehci)        cpu_to_hc32(ehci, QTD_STS_STS)
 368
 369         __hc32                  hw_buf [5];        /* see EHCI 3.5.4 */
 370         __hc32                  hw_buf_hi [5];        /* Appendix B */
 371
 372         /* the rest is HCD-private */
 373         dma_addr_t              qtd_dma;                /* qtd address */
 374         struct list_head        qtd_list;               /* sw qtd list */
 375         struct urb              *urb;                   /* qtd's urb */
 376         size_t                  length;                 /* length of buffer */
 377 } __attribute__ ((aligned (32)));
 378
 379 /* mask NakCnt+T in qh->hw_alt_next */
 380 #define QTD_MASK(ehci)  cpu_to_hc32 (ehci, ~0x1f)
 381
 382 #define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
 383
 384 /*-------------------------------------------------------------------------*/
 385
 386 /* type tag from {qh,itd,sitd,fstn}->hw_next */
 387 #define Q_NEXT_TYPE(ehci,dma)   ((dma) & cpu_to_hc32(ehci, 3 << 1))
 388
 389 /*
 390  * Now the following defines are not converted using the
 391  * __constant_cpu_to_le32() macro anymore, since we have to support
 392  * "dynamic" switching between be and le support, so that the driver
 393  * can be used on one system with SoC EHCI controller using big-endian
 394  * descriptors as well as a normal little-endian PCI EHCI controller.
 395  */
 396 /* values for that type tag */
 397 #define Q_TYPE_ITD      (0 << 1)
 398 #define Q_TYPE_QH       (1 << 1)
 399 #define Q_TYPE_SITD     (2 << 1)
 400 #define Q_TYPE_FSTN     (3 << 1)
 401
 402 /* next async queue entry, or pointer to interrupt/periodic QH */
 403 #define QH_NEXT(ehci,dma)       (cpu_to_hc32(ehci, (((u32)dma)&~0x01f)|Q_TYPE_QH))
 404
 405 /* for periodic/async schedules and qtd lists, mark end of list */
 406 #define EHCI_LIST_END(ehci)     cpu_to_hc32(ehci, 1) /* "null pointer" to hw */
 407
 408 /*
 409  * Entries in periodic shadow table are pointers to one of four kinds
 410  * of data structure.  That's dictated by the hardware; a type tag is
 411  * encoded in the low bits of the hardware's periodic schedule.  Use
 412  * Q_NEXT_TYPE to get the tag.
 413  *
 414  * For entries in the async schedule, the type tag always says "qh".
 415  */
 416 union ehci_shadow {
 417         struct ehci_qh          *qh;            /* Q_TYPE_QH */
 418         struct ehci_itd         *itd;           /* Q_TYPE_ITD */
 419         struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
 420         struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
 421         __hc32                  *hw_next;       /* (all types) */
 422         void                    *ptr;
 423 };
 424
 425 /*-------------------------------------------------------------------------*/
 426
 427 /*
 428  * EHCI Specification 0.95 Section 3.6
 429  * QH: describes control/bulk/interrupt endpoints
 430  * See Fig 3-7 "Queue Head Structure Layout".
 431  *
 432  * These appear in both the async and (for interrupt) periodic schedules.
 433  */
 434
 435 /* first part defined by EHCI spec */
 436 struct ehci_qh_hw {
 437         __hc32                  hw_next;        /* see EHCI 3.6.1 */
 438         __hc32                  hw_info1;       /* see EHCI 3.6.2 */
 439 #define QH_HEAD         0x00008000
 440         __hc32                  hw_info2;        /* see EHCI 3.6.2 */
 441 #define QH_SMASK        0x000000ff
 442 #define QH_CMASK        0x0000ff00
 443 #define QH_HUBADDR      0x007f0000
 444 #define QH_HUBPORT      0x3f800000
 445 #define QH_MULT         0xc0000000
 446         __hc32                  hw_current;     /* qtd list - see EHCI 3.6.4 */
 447
 448         /* qtd overlay (hardware parts of a struct ehci_qtd) */
 449         __hc32                  hw_qtd_next;
 450         __hc32                  hw_alt_next;
 451         __hc32                  hw_token;
 452         __hc32                  hw_buf [5];
 453         __hc32                  hw_buf_hi [5];
 454 } __attribute__ ((aligned(32)));
 455
 456 struct ehci_qh {
 457         struct ehci_qh_hw       *hw;
 458         /* the rest is HCD-private */
 459         dma_addr_t              qh_dma;         /* address of qh */
 460         union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
 461         struct list_head        qtd_list;       /* sw qtd list */
 462         struct ehci_qtd         *dummy;
 463         struct ehci_qh          *reclaim;       /* next to reclaim */
 464
 465         struct ehci_hcd         *ehci;
 466
 467         /*
 468          * Do NOT use atomic operations for QH refcounting. On some CPUs
 469          * (PPC7448 for example), atomic operations cannot be performed on
 470          * memory that is cache-inhibited (i.e. being used for DMA).
 471          * Spinlocks are used to protect all QH fields.
 472          */
 473         u32                     refcount;
 474         unsigned                stamp;
 475
 476         u8                      needs_rescan;   /* Dequeue during giveback */
 477         u8                      qh_state;
 478 #define QH_STATE_LINKED         1               /* HC sees this */
 479 #define QH_STATE_UNLINK         2               /* HC may still see this */
 480 #define QH_STATE_IDLE           3               /* HC doesn't see this */
 481 #define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
 482 #define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
 483
 484         u8                      xacterrs;       /* XactErr retry counter */
 485 #define QH_XACTERR_MAX          32              /* XactErr retry limit */
 486
 487         /* periodic schedule info */
 488         u8                      usecs;          /* intr bandwidth */
 489         u8                      gap_uf;         /* uframes split/csplit gap */
 490         u8                      c_usecs;        /* ... split completion bw */
 491         u16                     tt_usecs;       /* tt downstream bandwidth */
 492         unsigned short          period;         /* polling interval */
 493         unsigned short          start;          /* where polling starts */
 494 #define NO_FRAME ((unsigned short)~0)                   /* pick new start */
 495         struct usb_device       *dev;           /* access to TT */
 496         unsigned                clearing_tt:1;  /* Clear-TT-Buf in progress */
 497 };
 498
 499 /*-------------------------------------------------------------------------*/
 500
 501 /* description of one iso transaction (up to 3 KB data if highspeed) */
 502 struct ehci_iso_packet {
 503         /* These will be copied to iTD when scheduling */
 504         u64                     bufp;           /* itd->hw_bufp{,_hi}[pg] |= */
 505         __hc32                  transaction;    /* itd->hw_transaction[i] |= */
 506         u8                      cross;          /* buf crosses pages */
 507         /* for full speed OUT splits */
 508         u32                     buf1;
 509 };
 510
 511 /* temporary schedule data for packets from iso urbs (both speeds)
 512  * each packet is one logical usb transaction to the device (not TT),
 513  * beginning at stream->next_uframe
 514  */
 515 struct ehci_iso_sched {
 516         struct list_head        td_list;
 517         unsigned                span;
 518         struct ehci_iso_packet  packet [0];
 519 };
 520
 521 /*
 522  * ehci_iso_stream - groups all (s)itds for this endpoint.
 523  * acts like a qh would, if EHCI had them for ISO.
 524  */
 525 struct ehci_iso_stream {
 526         /* first field matches ehci_hq, but is NULL */
 527         struct ehci_qh_hw       *hw;
 528
 529         u32                     refcount;
 530         u8                      bEndpointAddress;
 531         u8                      highspeed;
 532         struct list_head        td_list;        /* queued itds/sitds */
 533         struct list_head        free_list;      /* list of unused itds/sitds */
 534         struct usb_device       *udev;
 535         struct usb_host_endpoint *ep;
 536
 537         /* output of (re)scheduling */
 538         int                     next_uframe;
 539         __hc32                  splits;
 540
 541         /* the rest is derived from the endpoint descriptor,
 542          * trusting urb->interval == f(epdesc->bInterval) and
 543          * including the extra info for hw_bufp[0..2]
 544          */
 545         u8                      usecs, c_usecs;
 546         u16                     interval;
 547         u16                     tt_usecs;
 548         u16                     maxp;
 549         u16                     raw_mask;
 550         unsigned                bandwidth;
 551
 552         /* This is used to initialize iTD's hw_bufp fields */
 553         __hc32                  buf0;
 554         __hc32                  buf1;
 555         __hc32                  buf2;
 556
 557         /* this is used to initialize sITD's tt info */
 558         __hc32                  address;
 559 };
 560
 561 /*-------------------------------------------------------------------------*/
 562
 563 /*
 564  * EHCI Specification 0.95 Section 3.3
 565  * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
 566  *
 567  * Schedule records for high speed iso xfers
 568  */
 569 struct ehci_itd {
 570         /* first part defined by EHCI spec */
 571         __hc32                  hw_next;           /* see EHCI 3.3.1 */
 572         __hc32                  hw_transaction [8]; /* see EHCI 3.3.2 */
 573 #define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
 574 #define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
 575 #define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
 576 #define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
 577 #define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x0fff)
 578 #define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
 579
 580 #define ITD_ACTIVE(ehci)        cpu_to_hc32(ehci, EHCI_ISOC_ACTIVE)
 581
 582         __hc32                  hw_bufp [7];    /* see EHCI 3.3.3 */
 583         __hc32                  hw_bufp_hi [7]; /* Appendix B */
 584
 585         /* the rest is HCD-private */
 586         dma_addr_t              itd_dma;        /* for this itd */
 587         union ehci_shadow       itd_next;       /* ptr to periodic q entry */
 588
 589         struct urb              *urb;
 590         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 591         struct list_head        itd_list;       /* list of stream's itds */
 592
 593         /* any/all hw_transactions here may be used by that urb */
 594         unsigned                frame;          /* where scheduled */
 595         unsigned                pg;
 596         unsigned                index[8];       /* in urb->iso_frame_desc */
 597 } __attribute__ ((aligned (32)));
 598
 599 /*-------------------------------------------------------------------------*/
 600
 601 /*
 602  * EHCI Specification 0.95 Section 3.4
 603  * siTD, aka split-transaction isochronous Transfer Descriptor
 604  *       ... describe full speed iso xfers through TT in hubs
 605  * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
 606  */
 607 struct ehci_sitd {
 608         /* first part defined by EHCI spec */
 609         __hc32                  hw_next;
 610 /* uses bit field macros above - see EHCI 0.95 Table 3-8 */
 611         __hc32                  hw_fullspeed_ep;        /* EHCI table 3-9 */
 612         __hc32                  hw_uframe;              /* EHCI table 3-10 */
 613         __hc32                  hw_results;             /* EHCI table 3-11 */
 614 #define SITD_IOC        (1 << 31)       /* interrupt on completion */
 615 #define SITD_PAGE       (1 << 30)       /* buffer 0/1 */
 616 #define SITD_LENGTH(x)  (0x3ff & ((x)>>16))
 617 #define SITD_STS_ACTIVE (1 << 7)        /* HC may execute this */
 618 #define SITD_STS_ERR    (1 << 6)        /* error from TT */
 619 #define SITD_STS_DBE    (1 << 5)        /* data buffer error (in HC) */
 620 #define SITD_STS_BABBLE (1 << 4)        /* device was babbling */
 621 #define SITD_STS_XACT   (1 << 3)        /* illegal IN response */
 622 #define SITD_STS_MMF    (1 << 2)        /* incomplete split transaction */
 623 #define SITD_STS_STS    (1 << 1)        /* split transaction state */
 624
 625 #define SITD_ACTIVE(ehci)       cpu_to_hc32(ehci, SITD_STS_ACTIVE)
 626
 627         __hc32                  hw_buf [2];             /* EHCI table 3-12 */
 628         __hc32                  hw_backpointer;         /* EHCI table 3-13 */
 629         __hc32                  hw_buf_hi [2];          /* Appendix B */
 630
 631         /* the rest is HCD-private */
 632         dma_addr_t              sitd_dma;
 633         union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
 634
 635         struct urb              *urb;
 636         struct ehci_iso_stream  *stream;        /* endpoint's queue */
 637         struct list_head        sitd_list;      /* list of stream's sitds */
 638         unsigned                frame;
 639         unsigned                index;
 640 } __attribute__ ((aligned (32)));
 641
 642 /*-------------------------------------------------------------------------*/
 643
 644 /*
 645  * EHCI Specification 0.96 Section 3.7
 646  * Periodic Frame Span Traversal Node (FSTN)
 647  *
 648  * Manages split interrupt transactions (using TT) that span frame boundaries
 649  * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
 650  * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
 651  * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
 652  */
 653 struct ehci_fstn {
 654         __hc32                  hw_next;        /* any periodic q entry */
 655         __hc32                  hw_prev;        /* qh or EHCI_LIST_END */
 656
 657         /* the rest is HCD-private */
 658         dma_addr_t              fstn_dma;
 659         union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
 660 } __attribute__ ((aligned (32)));
 661
 662 /*-------------------------------------------------------------------------*/
 663
 664 #ifdef CONFIG_USB_EHCI_ROOT_HUB_TT
 665
 666 /*
 667  * Some EHCI controllers have a Transaction Translator built into the
 668  * root hub. This is a non-standard feature.  Each controller will need
 669  * to add code to the following inline functions, and call them as
 670  * needed (mostly in root hub code).
 671  */
 672
 673 #define ehci_is_TDI(e)                  (ehci_to_hcd(e)->has_tt)
 674
 675 /* Returns the speed of a device attached to a port on the root hub. */
 676 static inline unsigned int
 677 ehci_port_speed(struct ehci_hcd *ehci, unsigned int portsc)
 678 {
 679         if (ehci_is_TDI(ehci)) {
 680                 switch ((portsc>>26)&3) {
 681                 case 0:
 682                         return 0;
 683                 case 1:
 684                         return (1<<USB_PORT_FEAT_LOWSPEED);
 685                 case 2:
 686                 default:
 687                         return (1<<USB_PORT_FEAT_HIGHSPEED);
 688                 }
 689         }
 690         return (1<<USB_PORT_FEAT_HIGHSPEED);
 691 }
 692
 693 #else
 694
 695 #define ehci_is_TDI(e)                  (0)
 696
 697 #define ehci_port_speed(ehci, portsc)   (1<<USB_PORT_FEAT_HIGHSPEED)
 698 #endif
 699
 700 /*-------------------------------------------------------------------------*/
 701
 702 #ifdef CONFIG_PPC_83xx
 703 /* Some Freescale processors have an erratum in which the TT
 704  * port number in the queue head was 0..N-1 instead of 1..N.
 705  */
 706 #define ehci_has_fsl_portno_bug(e)              ((e)->has_fsl_port_bug)
 707 #else
 708 #define ehci_has_fsl_portno_bug(e)              (0)
 709 #endif
 710
 711 /*
 712  * While most USB host controllers implement their registers in
 713  * little-endian format, a minority (celleb companion chip) implement
 714  * them in big endian format.
 715  *
 716  * This attempts to support either format at compile time without a
 717  * runtime penalty, or both formats with the additional overhead
 718  * of checking a flag bit.
 719  */
 720
 721 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 722 #define ehci_big_endian_mmio(e)         ((e)->big_endian_mmio)
 723 #else
 724 #define ehci_big_endian_mmio(e)         0
 725 #endif
 726
 727 /*
 728  * Big-endian read/write functions are arch-specific.
 729  * Other arches can be added if/when they're needed.
 730  *
 731  * REVISIT: arch/powerpc now has readl/writel_be, so the
 732  * definition below can die once the 4xx support is
 733  * finally ported over.
 734  */
 735 #if defined(CONFIG_PPC)
 736 #define readl_be(addr)          in_be32((__force unsigned *)addr)
 737 #define writel_be(val, addr)    out_be32((__force unsigned *)addr, val)
 738 #endif
 739
 740 static inline unsigned int ehci_readl(const struct ehci_hcd *ehci,
 741                 __u32 __iomem * regs)
 742 {
 743 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 744         return ehci_big_endian_mmio(ehci) ?
 745                 readl_be(regs) :
 746                 readl(regs);
 747 #else
 748         return readl(regs);
 749 #endif
 750 }
 751
 752 static inline void ehci_writel(const struct ehci_hcd *ehci,
 753                 const unsigned int val, __u32 __iomem *regs)
 754 {
 755 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
 756         ehci_big_endian_mmio(ehci) ?
 757                 writel_be(val, regs) :
 758                 writel(val, regs);
 759 #else
 760         writel(val, regs);
 761 #endif
 762 }
 763
 764 /*-------------------------------------------------------------------------*/
 765
 766 /*
 767  * The AMCC 440EPx not only implements its EHCI registers in big-endian
 768  * format, but also its DMA data structures (descriptors).
 769  *
 770  * EHCI controllers accessed through PCI work normally (little-endian
 771  * everywhere), so we won't bother supporting a BE-only mode for now.
 772  */
 773 #ifdef CONFIG_USB_EHCI_BIG_ENDIAN_DESC
 774 #define ehci_big_endian_desc(e)         ((e)->big_endian_desc)
 775
 776 /* cpu to ehci */
 777 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 778 {
 779         return ehci_big_endian_desc(ehci)
 780                 ? (__force __hc32)cpu_to_be32(x)
 781                 : (__force __hc32)cpu_to_le32(x);
 782 }
 783
 784 /* ehci to cpu */
 785 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 786 {
 787         return ehci_big_endian_desc(ehci)
 788                 ? be32_to_cpu((__force __be32)x)
 789                 : le32_to_cpu((__force __le32)x);
 790 }
 791
 792 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 793 {
 794         return ehci_big_endian_desc(ehci)
 795                 ? be32_to_cpup((__force __be32 *)x)
 796                 : le32_to_cpup((__force __le32 *)x);
 797 }
 798
 799 #else
 800
 801 /* cpu to ehci */
 802 static inline __hc32 cpu_to_hc32 (const struct ehci_hcd *ehci, const u32 x)
 803 {
 804         return cpu_to_le32(x);
 805 }
 806
 807 /* ehci to cpu */
 808 static inline u32 hc32_to_cpu (const struct ehci_hcd *ehci, const __hc32 x)
 809 {
 810         return le32_to_cpu(x);
 811 }
 812
 813 static inline u32 hc32_to_cpup (const struct ehci_hcd *ehci, const __hc32 *x)
 814 {
 815         return le32_to_cpup(x);
 816 }
 817
 818 #endif
 819
 820 /*-------------------------------------------------------------------------*/
 821
 822 #ifndef DEBUG
 823 #define STUB_DEBUG_FILES
 824 #endif  /* DEBUG */
 825
 826 /*-------------------------------------------------------------------------*/
 827
 828 #endif /* __LINUX_EHCI_HCD_H */