2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2000, 2001, 2003 Ralf Baechle
7 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
8 * Copyright (C) 2001 MIPS Technologies, Inc.
9 * Copyright (C) 2002 Maciej W. Rozycki
11 #include <linux/init.h>
14 #include <asm/asmmacro.h>
15 #include <asm/cacheops.h>
16 #include <asm/irqflags.h>
17 #include <asm/regdef.h>
18 #include <asm/fpregdef.h>
19 #include <asm/mipsregs.h>
20 #include <asm/stackframe.h>
23 #include <asm/thread_info.h>
25 #define PANIC_PIC(msg) \
38 NESTED(except_vec0_generic, 0, sp)
39 PANIC_PIC("Exception vector 0 called")
40 END(except_vec0_generic)
42 NESTED(except_vec1_generic, 0, sp)
43 PANIC_PIC("Exception vector 1 called")
44 END(except_vec1_generic)
47 * General exception vector for all other CPUs.
49 * Be careful when changing this, it has to be at most 128 bytes
50 * to fit into space reserved for the exception handler.
52 NESTED(except_vec3_generic, 0, sp)
59 #if R5432_CP0_INTERRUPT_WAR
71 PTR_L k0, exception_handlers(k1)
74 END(except_vec3_generic)
77 * General exception handler for CPUs with virtual coherency exception.
79 * Be careful when changing this, it has to be at most 256 (as a special
80 * exception) bytes to fit into space reserved for the exception handler.
82 NESTED(except_vec3_r4000, 0, sp)
92 beq k1, k0, handle_vced
94 beq k1, k0, handle_vcei
99 PTR_L k0, exception_handlers(k1)
103 * Big shit, we now may have two dirty primary cache lines for the same
104 * physical address. We can safely invalidate the line pointed to by
105 * c0_badvaddr because after return from this exception handler the
106 * load / store will be re-executed.
109 MFC0 k0, CP0_BADVADDR
110 li k1, -4 # Is this ...
111 and k0, k1 # ... really needed?
113 cache Index_Store_Tag_D, (k0)
114 cache Hit_Writeback_Inv_SD, (k0)
115 #ifdef CONFIG_PROC_FS
116 PTR_LA k0, vced_count
124 MFC0 k0, CP0_BADVADDR
125 cache Hit_Writeback_Inv_SD, (k0) # also cleans pi
126 #ifdef CONFIG_PROC_FS
127 PTR_LA k0, vcei_count
134 END(except_vec3_r4000)
138 .align 5 /* 32 byte rollback region */
142 /* start of rollback region */
143 LONG_L t0, TI_FLAGS($28)
145 andi t0, _TIF_NEED_RESCHED
152 /* end of rollback region (the region size must be power of two) */
158 .macro BUILD_ROLLBACK_PROLOGUE handler
159 FEXPORT(rollback_\handler)
164 ori k0, 0x1f /* 32 byte rollback region */
173 BUILD_ROLLBACK_PROLOGUE handle_int
174 NESTED(handle_int, PT_SIZE, sp)
175 #ifdef CONFIG_TRACE_IRQFLAGS
177 * Check to see if the interrupted code has just disabled
178 * interrupts and ignore this interrupt for now if so.
180 * local_irq_disable() disables interrupts and then calls
181 * trace_hardirqs_off() to track the state. If an interrupt is taken
182 * after interrupts are disabled but before the state is updated
183 * it will appear to restore_all that it is incorrectly returning with
184 * interrupts disabled
189 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
210 LONG_L s0, TI_REGS($28)
211 LONG_S sp, TI_REGS($28)
212 PTR_LA ra, ret_from_irq
219 * Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
220 * This is a dedicated interrupt exception vector which reduces the
221 * interrupt processing overhead. The jump instruction will be replaced
222 * at the initialization time.
224 * Be careful when changing this, it has to be at most 128 bytes
225 * to fit into space reserved for the exception handler.
227 NESTED(except_vec4, 0, sp)
228 1: j 1b /* Dummy, will be replaced */
232 * EJTAG debug exception handler.
233 * The EJTAG debug exception entry point is 0xbfc00480, which
234 * normally is in the boot PROM, so the boot PROM must do a
235 * unconditional jump to this vector.
237 NESTED(except_vec_ejtag_debug, 0, sp)
238 j ejtag_debug_handler
239 END(except_vec_ejtag_debug)
244 * Vectored interrupt handler.
245 * This prototype is copied to ebase + n*IntCtl.VS and patched
246 * to invoke the handler
248 BUILD_ROLLBACK_PROLOGUE except_vec_vi
249 NESTED(except_vec_vi, 0, sp)
254 #ifdef CONFIG_MIPS_MT_SMTC
256 * To keep from blindly blocking *all* interrupts
257 * during service by SMTC kernel, we also want to
258 * pass the IM value to be cleared.
260 FEXPORT(except_vec_vi_mori)
262 #endif /* CONFIG_MIPS_MT_SMTC */
263 FEXPORT(except_vec_vi_lui)
264 lui v0, 0 /* Patched */
265 j except_vec_vi_handler
266 FEXPORT(except_vec_vi_ori)
267 ori v0, 0 /* Patched */
270 EXPORT(except_vec_vi_end)
273 * Common Vectored Interrupt code
274 * Complete the register saves and invoke the handler which is passed in $v0
276 NESTED(except_vec_vi_handler, 0, sp)
279 #ifdef CONFIG_MIPS_MT_SMTC
281 * SMTC has an interesting problem that interrupts are level-triggered,
282 * and the CLI macro will clear EXL, potentially causing a duplicate
283 * interrupt service invocation. So we need to clear the associated
284 * IM bit of Status prior to doing CLI, and restore it after the
285 * service routine has been invoked - we must assume that the
286 * service routine will have cleared the state, and any active
287 * level represents a new or otherwised unserviced event...
291 #ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
292 mfc0 t2, CP0_TCCONTEXT
294 mtc0 t0, CP0_TCCONTEXT
295 #endif /* CONFIG_MIPS_MT_SMTC_IM_BACKSTOP */
299 #endif /* CONFIG_MIPS_MT_SMTC */
301 #ifdef CONFIG_TRACE_IRQFLAGS
303 #ifdef CONFIG_MIPS_MT_SMTC
307 #ifdef CONFIG_MIPS_MT_SMTC
313 LONG_L s0, TI_REGS($28)
314 LONG_S sp, TI_REGS($28)
315 PTR_LA ra, ret_from_irq
317 END(except_vec_vi_handler)
320 * EJTAG debug exception handler.
322 NESTED(ejtag_debug_handler, PT_SIZE, sp)
328 sll k0, k0, 30 # Check for SDBBP.
329 bgez k0, ejtag_return
331 PTR_LA k0, ejtag_debug_buffer
335 jal ejtag_exception_handler
337 PTR_LA k0, ejtag_debug_buffer
345 END(ejtag_debug_handler)
348 * This buffer is reserved for the use of the EJTAG debug
352 EXPORT(ejtag_debug_buffer)
359 * NMI debug exception handler for MIPS reference boards.
360 * The NMI debug exception entry point is 0xbfc00000, which
361 * normally is in the boot PROM, so the boot PROM must do a
362 * unconditional jump to this vector.
364 NESTED(except_vec_nmi, 0, sp)
370 NESTED(nmi_handler, PT_SIZE, sp)
375 jal nmi_exception_handler
382 .macro __build_clear_none
385 .macro __build_clear_sti
390 .macro __build_clear_cli
395 .macro __build_clear_fpe
404 .macro __build_clear_ade
405 MFC0 t0, CP0_BADVADDR
406 PTR_S t0, PT_BVADDR(sp)
410 .macro __BUILD_silent exception
413 /* Gas tries to parse the PRINT argument as a string containing
414 string escapes and emits bogus warnings if it believes to
415 recognize an unknown escape code. So make the arguments
416 start with an n and gas will believe \n is ok ... */
417 .macro __BUILD_verbose nexception
418 LONG_L a1, PT_EPC(sp)
420 PRINT("Got \nexception at %08lx\012")
423 PRINT("Got \nexception at %016lx\012")
427 .macro __BUILD_count exception
428 LONG_L t0,exception_count_\exception
430 LONG_S t0,exception_count_\exception
431 .comm exception_count\exception, 8, 8
434 .macro __BUILD_HANDLER exception handler clear verbose ext
436 NESTED(handle_\exception, PT_SIZE, sp)
439 FEXPORT(handle_\exception\ext)
442 __BUILD_\verbose \exception
444 PTR_LA ra, ret_from_exception
446 END(handle_\exception)
449 .macro BUILD_HANDLER exception handler clear verbose
450 __BUILD_HANDLER \exception \handler \clear \verbose _int
453 BUILD_HANDLER adel ade ade silent /* #4 */
454 BUILD_HANDLER ades ade ade silent /* #5 */
455 BUILD_HANDLER ibe be cli silent /* #6 */
456 BUILD_HANDLER dbe be cli silent /* #7 */
457 BUILD_HANDLER bp bp sti silent /* #9 */
458 BUILD_HANDLER ri ri sti silent /* #10 */
459 BUILD_HANDLER cpu cpu sti silent /* #11 */
460 BUILD_HANDLER ov ov sti silent /* #12 */
461 BUILD_HANDLER tr tr sti silent /* #13 */
462 BUILD_HANDLER fpe fpe fpe silent /* #15 */
463 BUILD_HANDLER mdmx mdmx sti silent /* #22 */
464 BUILD_HANDLER watch watch sti verbose /* #23 */
465 BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
466 BUILD_HANDLER mt mt sti silent /* #25 */
467 BUILD_HANDLER dsp dsp sti silent /* #26 */
468 BUILD_HANDLER reserved reserved sti verbose /* others */
471 LEAF(handle_ri_rdhwr_vivt)
472 #ifdef CONFIG_MIPS_MT_SMTC
473 PANIC_PIC("handle_ri_rdhwr_vivt called")
478 /* check if TLB contains a entry for EPC */
480 andi k1, 0xff /* ASID_MASK */
482 PTR_SRL k0, PAGE_SHIFT + 1
483 PTR_SLL k0, PAGE_SHIFT + 1
491 bltz k1, handle_ri /* slow path */
494 END(handle_ri_rdhwr_vivt)
496 LEAF(handle_ri_rdhwr)
500 /* 0x7c03e83b: rdhwr v1,$29 */
506 bne k0, k1, handle_ri /* if not ours */
507 /* The insn is rdhwr. No need to check CAUSE.BD here. */
508 get_saved_sp /* k1 := current_thread_info */
511 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
513 xori k1, _THREAD_MASK
514 LONG_L v1, TI_TP_VALUE(k1)
519 LONG_ADDIU k0, 4 /* stall on $k0 */
521 /* I hope three instructions between MTC0 and ERET are enough... */
523 xori k1, _THREAD_MASK
524 LONG_L v1, TI_TP_VALUE(k1)
533 /* A temporary overflow handler used by check_daddi(). */
537 BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */