2 * Misc utility routines for accessing the SOC Interconnects
3 * of Broadcom HNBU chips.
5 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
7 * Permission to use, copy, modify, and/or distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
14 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
16 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
17 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 * $Id: siutils.h,v 13.254.4.14 2011-01-27 19:03:20 Exp $
25 #if defined(WLC_HIGH) && !defined(WLC_LOW)
29 * Data structure to export all chip specific common variables
30 * public (read-only) portion of siutils handle returned by si_attach()/si_kattach()
33 uint socitype
; /* SOCI_SB, SOCI_AI */
35 uint bustype
; /* SI_BUS, PCI_BUS */
36 uint buscoretype
; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
37 uint buscorerev
; /* buscore rev */
38 uint buscoreidx
; /* buscore index */
39 int ccrev
; /* chip common core rev */
40 uint32 cccaps
; /* chip common capabilities */
41 uint32 cccaps_ext
; /* chip common capabilities extension */
42 int pmurev
; /* pmu core rev */
43 uint32 pmucaps
; /* pmu capabilities */
44 uint boardtype
; /* board type */
45 uint boardrev
; /* board rev */
46 uint boardvendor
; /* board vendor */
47 uint boardflags
; /* board flags */
48 uint boardflags2
; /* board flags2 */
49 uint chip
; /* chip number */
50 uint chiprev
; /* chip revision */
51 uint chippkg
; /* chip package option */
52 uint32 chipst
; /* chip status */
53 bool issim
; /* chip is in simulation or emulation */
54 uint socirev
; /* SOC interconnect rev */
57 #if defined(WLC_HIGH) && !defined(WLC_LOW)
60 #ifdef SI_ENUM_BASE_VARIABLE
62 #endif /* SI_ENUM_BASE_VARIABLE */
65 /* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
66 * for monolithic driver, it is readonly to prevent accident change
68 #if defined(WLC_HIGH) && !defined(WLC_LOW)
69 typedef struct si_pub si_t
;
71 typedef const struct si_pub si_t
;
75 * Many of the routines below take an 'sih' handle as their first arg.
76 * Allocate this by calling si_attach(). Free it by calling si_detach().
77 * At any one time, the sih is logically focused on one particular si core
78 * (the "current core").
79 * Use si_setcore() or si_setcoreidx() to change the association to another core.
81 #define SI_OSH NULL /* Use for si_kattach when no osh is available */
83 #define BADIDX (SI_MAXCORES + 1)
85 /* clkctl xtal what flags */
86 #define XTAL 0x1 /* primary crystal oscillator (2050) */
87 #define PLL 0x2 /* main chip pll */
90 #define CLK_FAST 0 /* force fast (pll) clock */
91 #define CLK_DYNAMIC 2 /* enable dynamic clock control */
93 /* GPIO usage priorities */
94 #define GPIO_DRV_PRIORITY 0 /* Driver */
95 #define GPIO_APP_PRIORITY 1 /* Application */
96 #define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
98 /* GPIO pull up/down */
100 #define GPIO_PULLDN 1
102 /* GPIO event regtype */
103 #define GPIO_REGEVT 0 /* GPIO register event */
104 #define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
105 #define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
108 #define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
110 /* SI routine enumeration: to be used by update function with multiple hooks */
111 #define SI_DOATTACH 1
116 #define ISSIM_ENAB(sih) ((sih)->issim)
118 #define ISSIM_ENAB(sih) 0
121 /* PMU clock/power control */
122 #if defined(BCMPMUCTL)
123 #define PMUCTL_ENAB(sih) (BCMPMUCTL)
125 #define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
128 /* chipcommon clock/power control (exclusive with PMU's) */
129 #if defined(BCMPMUCTL) && BCMPMUCTL
130 #define CCCTL_ENAB(sih) (0)
131 #define CCPLL_ENAB(sih) (0)
133 #define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
134 #define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
137 typedef void (*gpio_handler_t
)(uint32 stat
, void *arg
);
138 /* External BT Coex enable mask */
139 #define CC_BTCOEX_EN_MASK 0x01
140 /* External PA enable mask */
141 #define GPIO_CTRL_EPA_EN_MASK 0x40
142 /* WL/BT control enable mask */
143 #define GPIO_CTRL_5_6_EN_MASK 0x60
145 /* === exported functions === */
146 extern si_t
*si_attach(uint pcidev
, osl_t
*osh
, void *regs
, uint bustype
,
147 void *sdh
, char **vars
, uint
*varsz
);
148 extern si_t
*si_kattach(osl_t
*osh
);
149 extern void si_detach(si_t
*sih
);
150 extern bool si_pci_war16165(si_t
*sih
);
152 extern uint
si_corelist(si_t
*sih
, uint coreid
[]);
153 extern uint
si_coreid(si_t
*sih
);
154 extern uint
si_flag(si_t
*sih
);
155 extern uint
si_intflag(si_t
*sih
);
156 extern uint
si_coreidx(si_t
*sih
);
157 extern uint
si_coreunit(si_t
*sih
);
158 extern uint
si_corevendor(si_t
*sih
);
159 extern uint
si_corerev(si_t
*sih
);
160 extern void *si_osh(si_t
*sih
);
161 extern void si_setosh(si_t
*sih
, osl_t
*osh
);
162 extern uint
si_corereg(si_t
*sih
, uint coreidx
, uint regoff
, uint mask
, uint val
);
163 extern void *si_coreregs(si_t
*sih
);
164 extern void si_write_wrapperreg(si_t
*sih
, uint32 offset
, uint32 val
);
165 extern uint32
si_core_cflags(si_t
*sih
, uint32 mask
, uint32 val
);
166 extern void si_core_cflags_wo(si_t
*sih
, uint32 mask
, uint32 val
);
167 extern uint32
si_core_sflags(si_t
*sih
, uint32 mask
, uint32 val
);
168 extern bool si_iscoreup(si_t
*sih
);
169 extern uint
si_findcoreidx(si_t
*sih
, uint coreid
, uint coreunit
);
170 extern void *si_setcoreidx(si_t
*sih
, uint coreidx
);
171 extern void *si_setcore(si_t
*sih
, uint coreid
, uint coreunit
);
172 extern void *si_switch_core(si_t
*sih
, uint coreid
, uint
*origidx
, uint
*intr_val
);
173 extern void si_restore_core(si_t
*sih
, uint coreid
, uint intr_val
);
174 extern int si_numaddrspaces(si_t
*sih
);
175 extern uint32
si_addrspace(si_t
*sih
, uint asidx
);
176 extern uint32
si_addrspacesize(si_t
*sih
, uint asidx
);
177 extern void si_coreaddrspaceX(si_t
*sih
, uint asidx
, uint32
*addr
, uint32
*size
);
178 extern int si_corebist(si_t
*sih
);
179 extern void si_core_reset(si_t
*sih
, uint32 bits
, uint32 resetbits
);
180 extern void si_core_disable(si_t
*sih
, uint32 bits
);
181 extern uint32
si_clock_rate(uint32 pll_type
, uint32 n
, uint32 m
);
182 extern uint32
si_clock(si_t
*sih
);
183 extern uint32
si_alp_clock(si_t
*sih
);
184 extern uint32
si_ilp_clock(si_t
*sih
);
185 extern void si_pci_setup(si_t
*sih
, uint coremask
);
186 extern void si_pcmcia_init(si_t
*sih
);
187 extern void si_setint(si_t
*sih
, int siflag
);
188 extern bool si_backplane64(si_t
*sih
);
189 extern void si_register_intr_callback(si_t
*sih
, void *intrsoff_fn
, void *intrsrestore_fn
,
190 void *intrsenabled_fn
, void *intr_arg
);
191 extern void si_deregister_intr_callback(si_t
*sih
);
192 extern void si_clkctl_init(si_t
*sih
);
193 extern uint16
si_clkctl_fast_pwrup_delay(si_t
*sih
);
194 extern bool si_clkctl_cc(si_t
*sih
, uint mode
);
195 extern int si_clkctl_xtal(si_t
*sih
, uint what
, bool on
);
196 extern uint32
si_gpiotimerval(si_t
*sih
, uint32 mask
, uint32 val
);
197 extern void si_btcgpiowar(si_t
*sih
);
198 extern bool si_deviceremoved(si_t
*sih
);
199 extern uint32
si_socram_size(si_t
*sih
);
200 extern uint32
si_socdevram_size(si_t
*sih
);
201 extern void si_socdevram(si_t
*sih
, bool set
, uint8
*ennable
, uint8
*protect
);
202 extern bool si_socdevram_pkg(si_t
*sih
);
204 extern void si_watchdog(si_t
*sih
, uint ticks
);
205 extern void si_watchdog_ms(si_t
*sih
, uint32 ms
);
206 extern void *si_gpiosetcore(si_t
*sih
);
207 extern uint32
si_gpiocontrol(si_t
*sih
, uint32 mask
, uint32 val
, uint8 priority
);
208 extern uint32
si_gpioouten(si_t
*sih
, uint32 mask
, uint32 val
, uint8 priority
);
209 extern uint32
si_gpioout(si_t
*sih
, uint32 mask
, uint32 val
, uint8 priority
);
210 extern uint32
si_gpioin(si_t
*sih
);
211 extern uint32
si_gpiointpolarity(si_t
*sih
, uint32 mask
, uint32 val
, uint8 priority
);
212 extern uint32
si_gpiointmask(si_t
*sih
, uint32 mask
, uint32 val
, uint8 priority
);
213 extern uint32
si_gpioled(si_t
*sih
, uint32 mask
, uint32 val
);
214 extern uint32
si_gpioreserve(si_t
*sih
, uint32 gpio_num
, uint8 priority
);
215 extern uint32
si_gpiorelease(si_t
*sih
, uint32 gpio_num
, uint8 priority
);
216 extern uint32
si_gpiopull(si_t
*sih
, bool updown
, uint32 mask
, uint32 val
);
217 extern uint32
si_gpioevent(si_t
*sih
, uint regtype
, uint32 mask
, uint32 val
);
218 extern uint32
si_gpio_int_enable(si_t
*sih
, bool enable
);
220 /* GPIO event handlers */
221 extern void *si_gpio_handler_register(si_t
*sih
, uint32 e
, bool lev
, gpio_handler_t cb
, void *arg
);
222 extern void si_gpio_handler_unregister(si_t
*sih
, void* gpioh
);
223 extern void si_gpio_handler_process(si_t
*sih
);
225 /* Wake-on-wireless-LAN (WOWL) */
226 extern bool si_pci_pmecap(si_t
*sih
);
228 extern bool si_pci_fastpmecap(struct osl_info
*osh
);
229 extern bool si_pci_pmestat(si_t
*sih
);
230 extern void si_pci_pmeclr(si_t
*sih
);
231 extern void si_pci_pmeen(si_t
*sih
);
232 extern uint
si_pcie_readreg(void *sih
, uint addrtype
, uint offset
);
235 extern uint16
si_d11_devid(si_t
*sih
);
236 extern int si_corepciid(si_t
*sih
, uint func
, uint16
*pcivendor
, uint16
*pcidevice
,
237 uint8
*pciclass
, uint8
*pcisubclass
, uint8
*pciprogif
, uint8
*pciheader
);
239 #if defined(BCMECICOEX)
240 extern bool si_eci(si_t
*sih
);
241 extern int si_eci_init(si_t
*sih
);
242 extern void si_eci_notify_bt(si_t
*sih
, uint32 mask
, uint32 val
, bool interrupt
);
243 extern bool si_seci(si_t
*sih
);
244 extern void* si_seci_init(si_t
*sih
, uint8 seci_mode
);
245 extern void si_seci_down(si_t
*sih
);
247 #define si_eci(sih) 0
248 #define si_eci_init(sih) (0)
249 #define si_eci_notify_bt(sih, type, val) (0)
250 #define si_seci(sih) 0
251 static INLINE
void * si_seci_init(si_t
*sih
, uint8 use_seci
) {return NULL
;}
252 #define si_seci_down(sih) do { } while (0)
253 #endif /* BCMECICOEX */
256 extern bool si_is_otp_disabled(si_t
*sih
);
257 extern bool si_is_otp_powered(si_t
*sih
);
258 extern void si_otp_power(si_t
*sih
, bool on
);
260 /* SPROM availability */
261 extern bool si_is_sprom_available(si_t
*sih
);
262 extern bool si_is_sprom_enabled(si_t
*sih
);
263 extern void si_sprom_enable(si_t
*sih
, bool enable
);
264 #ifdef SI_SPROM_PROBE
265 extern void si_sprom_init(si_t
*sih
);
266 #endif /* SI_SPROM_PROBE */
268 /* OTP/SROM CIS stuff */
269 extern int si_cis_source(si_t
*sih
);
270 #define CIS_DEFAULT 0
274 /* Fab-id information */
275 #define DEFAULT_FAB 0x0 /* Original/first fab used for this chip */
276 #define CSM_FAB7 0x1 /* CSM Fab7 chip */
277 #define TSMC_FAB12 0x2 /* TSMC Fab12/Fab14 chip */
278 #define SMIC_FAB4 0x3 /* SMIC Fab4 chip */
279 extern int BCMINITFN(si_otp_fabid
)(si_t
*sih
, uint16
*fabid
, bool rw
);
280 extern uint16
BCMINITFN(si_fabid
)(si_t
*sih
);
283 * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
284 * The returned path is NULL terminated and has trailing '/'.
285 * Return 0 on success, nonzero otherwise.
287 extern int si_devpath(si_t
*sih
, char *path
, int size
);
288 /* Read variable with prepending the devpath to the name */
289 extern char *si_getdevpathvar(si_t
*sih
, const char *name
);
290 extern int si_getdevpathintvar(si_t
*sih
, const char *name
);
291 extern char *si_coded_devpathvar(si_t
*sih
, char *varname
, int var_len
, const char *name
);
294 extern uint8
si_pcieclkreq(si_t
*sih
, uint32 mask
, uint32 val
);
295 extern uint32
si_pcielcreg(si_t
*sih
, uint32 mask
, uint32 val
);
296 extern void si_war42780_clkreq(si_t
*sih
, bool clkreq
);
297 extern void si_pci_sleep(si_t
*sih
);
298 extern void si_pci_down(si_t
*sih
);
299 extern void si_pci_up(si_t
*sih
);
300 extern void si_pcie_war_ovr_update(si_t
*sih
, uint8 aspm
);
301 extern void si_pcie_power_save_enable(si_t
*sih
, bool enable
);
303 extern void si_pcie_extendL1timer(si_t
*sih
, bool extend
);
304 extern int si_pci_fixcfg(si_t
*sih
);
305 extern bool si_ldo_war(si_t
*sih
, uint devid
);
306 extern void si_chippkg_set(si_t
*sih
, uint
);
309 extern void si_chipcontrl_epa4331_restore(si_t
*sih
, uint32 val
);
310 extern uint32
si_chipcontrl_epa4331_read(si_t
*sih
);
311 extern void si_chipcontrl_epa4331(si_t
*sih
, bool on
);
312 extern void si_chipcontrl_epa4331_wowl(si_t
*sih
, bool enter_wowl
);
313 /* Enable BT-COEX & Ex-PA for 4313 */
314 extern void si_epa_4313war(si_t
*sih
);
315 extern void si_btc_enable_chipcontrol(si_t
*sih
);
316 /* BT/WL selection for 4313 bt combo >= P250 boards */
317 extern void si_btcombo_p250_4313_war(si_t
*sih
);
318 extern void si_clk_pmu_htavail_set(si_t
*sih
, bool set_clear
);
319 extern uint
si_pll_reset(si_t
*sih
);
322 /* === debug routines === */
324 extern bool si_taclear(si_t
*sih
, bool details
);
327 extern void si_view(si_t
*sih
, bool verbose
);
328 extern void si_viewall(si_t
*sih
, bool verbose
);
331 #if defined(BCMDBG_DUMP)
332 extern void si_dump(si_t
*sih
, struct bcmstrbuf
*b
);
333 extern void si_ccreg_dump(si_t
*sih
, struct bcmstrbuf
*b
);
334 extern void si_clkctl_dump(si_t
*sih
, struct bcmstrbuf
*b
);
335 extern int si_gpiodump(si_t
*sih
, struct bcmstrbuf
*b
);
336 extern int si_dump_pcieregs(si_t
*sih
, struct bcmstrbuf
*b
);
338 #if defined(BCMDBG) || defined(BCMDBG_DUMP)
339 extern void si_dumpregs(si_t
*sih
, struct bcmstrbuf
*b
);
342 extern uint32
si_pciereg(si_t
*sih
, uint32 offset
, uint32 mask
, uint32 val
, uint type
);
343 extern uint32
si_pcieserdesreg(si_t
*sih
, uint32 mdioslave
, uint32 offset
, uint32 mask
, uint32 val
);
344 extern void si_pcie_set_request_size(si_t
*sih
, uint16 size
);
345 extern uint16
si_pcie_get_request_size(si_t
*sih
);
348 char *si_getnvramflvar(si_t
*sih
, const char *name
);
349 #endif /* DONGLEBUILD */
351 #endif /* _siutils_h_ */