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K2.6 patches and update.
[tomato.git] / release / src-rt / include / bcmsrom_tbl.h
blob9af58b28a89ca1c4791637f01f20e3adf367aa61
1 /*
2 * Table that encodes the srom formats for PCI/PCIe NICs.
3 *
4 * Copyright (C) 2010, Broadcom Corporation. All Rights Reserved.
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 *
18 * $Id: bcmsrom_tbl.h,v 13.40.10.12 2011-02-05 01:08:27 Exp $
19 */
20
21 #ifndef _bcmsrom_tbl_h_
22 #define _bcmsrom_tbl_h_
23
24 #include "sbpcmcia.h"
25 #include "wlioctl.h"
26
27 typedef struct {
28 const char *name;
29 uint32 revmask;
30 uint32 flags;
31 uint16 off;
32 uint16 mask;
33 } sromvar_t;
34
35 #define SRFL_MORE 1 /* value continues as described by the next entry */
36 #define SRFL_NOFFS 2 /* value bits can't be all one's */
37 #define SRFL_PRHEX 4 /* value is in hexdecimal format */
38 #define SRFL_PRSIGN 8 /* value is in signed decimal format */
39 #define SRFL_CCODE 0x10 /* value is in country code format */
40 #define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
41 #define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
42 #define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */
43
44
45 /* Assumptions:
46 * - Ethernet address spans across 3 consective words
47 *
48 * Table rules:
49 * - Add multiple entries next to each other if a value spans across multiple words
50 * (even multiple fields in the same word) with each entry except the last having
51 * it's SRFL_MORE bit set.
52 * - Ethernet address entry does not follow above rule and must not have SRFL_MORE
53 * bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
54 * - The last entry's name field must be NULL to indicate the end of the table. Other
55 * entries must have non-NULL name.
56 */
57
58 static const sromvar_t pci_sromvars[] = {
59 {"devid", 0xffffff00, SRFL_PRHEX|SRFL_NOVAR, PCI_F0DEVID, 0xffff},
60 {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
61 {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
62 {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
63 {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
64 {"boardflags", 0x00000004, SRFL_PRHEX|SRFL_MORE, SROM_BFL, 0xffff},
65 {"", 0, 0, SROM_BFL2, 0xffff},
66 {"boardflags", 0x00000008, SRFL_PRHEX|SRFL_MORE, SROM_BFL, 0xffff},
67 {"", 0, 0, SROM3_BFL2, 0xffff},
68 {"boardflags", 0x00000010, SRFL_PRHEX|SRFL_MORE, SROM4_BFL0, 0xffff},
69 {"", 0, 0, SROM4_BFL1, 0xffff},
70 {"boardflags", 0x000000e0, SRFL_PRHEX|SRFL_MORE, SROM5_BFL0, 0xffff},
71 {"", 0, 0, SROM5_BFL1, 0xffff},
72 {"boardflags", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL0, 0xffff},
73 {"", 0, 0, SROM8_BFL1, 0xffff},
74 {"boardflags2", 0x00000010, SRFL_PRHEX|SRFL_MORE, SROM4_BFL2, 0xffff},
75 {"", 0, 0, SROM4_BFL3, 0xffff},
76 {"boardflags2", 0x000000e0, SRFL_PRHEX|SRFL_MORE, SROM5_BFL2, 0xffff},
77 {"", 0, 0, SROM5_BFL3, 0xffff},
78 {"boardflags2", 0xffffff00, SRFL_PRHEX|SRFL_MORE, SROM8_BFL2, 0xffff},
79 {"", 0, 0, SROM8_BFL3, 0xffff},
80 {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
81 {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
82 {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
83 {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
84 {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
85 {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff},
86 {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
87 {"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
88 {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
89 {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
90 {"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff},
91 {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
92 {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
93 {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
94 {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
95 {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
96 {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
97 {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
98 {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
99 {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
100 {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
101 {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
102 {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
103 {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
104 {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
105 {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
106 {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
107 {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
108 {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
109 {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
110 {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
111 {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
112 {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
113 {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
114 {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
115 {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
116 {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
117 {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
118 {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
119 {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
120 {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
121 {"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff},
122 {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
123 {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
124 {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00},
125 {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
126 {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
127 {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
128 {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
129 {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
130 {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
131 {"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff},
132 {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00},
133 {"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff},
134 {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00},
135 {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
136 {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
137 {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
138 {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
139 {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
140 {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
141 {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
142 {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
143 {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
144 {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
145 {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
146 {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
147 {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
148 {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
149 {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
150 {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
151 {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
152 {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
153 {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
154 {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
155 {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
156 {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
157 {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
158 {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
159 {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
160 {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
161 {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
162 {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
163 {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
164 {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
165 {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
166 {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
167 {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
168 {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
169 {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
170 {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
171 {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
172 {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
173 {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
174 {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
175 {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
176 {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
177 {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
178 {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
179 {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
180 {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
181 {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
182 {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00},
183 {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
184 {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
185 {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
186 {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
187 {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
188 {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
189 {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
190 {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
191 {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
192 {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
193 {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
194 {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
195 {"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
196 {"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
197 {"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
198 {"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
199 {"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
200 {"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
201 {"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
202 {"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
203 {"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
204 {"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
205 {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
206 {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
207 {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
208 {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
209 {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
210 {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
211 {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
212 {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
213 {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
214 {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
215 {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
216 {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
217 {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
218 {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
219 {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
220 {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
221
222 {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
223 {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
224 {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
225 {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
226 {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
227 {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
228 {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
229 {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
230 {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
231 {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
232 {"leddc", 0xffffff00, SRFL_NOFFS|SRFL_LEDDC, SROM8_LEDDC, 0xffff},
233 {"leddc", 0x000000e0, SRFL_NOFFS|SRFL_LEDDC, SROM5_LEDDC, 0xffff},
234 {"leddc", 0x00000010, SRFL_NOFFS|SRFL_LEDDC, SROM4_LEDDC, 0xffff},
235 {"leddc", 0x00000008, SRFL_NOFFS|SRFL_LEDDC, SROM3_LEDDC, 0xffff},
236
237 {"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00},
238 {"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
239 {"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
240 {"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
241 {"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x00ff},
242 {"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
243 {"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0x0300},
244 {"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x000f},
245 {"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
246 {"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
247 {"elna2g", 0xffffff00, 0, SROM8_EXTLNAGAIN, 0x00ff},
248 {"elna5g", 0xffffff00, 0, SROM8_EXTLNAGAIN, 0xff00},
249 {"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
250 {"temps_period", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x0f00},
251 {"temps_hysteresis", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0xf000},
252 {"measpower1", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x007f},
253 {"measpower2", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_1_AND_2, 0x3f80},
254
255 {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
256 {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
257 {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
258 {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
259 {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
260 {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
261 {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
262 {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
263 {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
264 {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
265 {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
266 {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
267 {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
268 {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
269 {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
270 {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
271 {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
272 {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
273 {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
274 {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
275 {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
276 {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
277 {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
278 {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
279 {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
280 {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
281 {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
282 {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
283 {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
284 {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
285 {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
286 {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
287 {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
288 {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
289 {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
290 {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
291 {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
292 {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
293 {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
294 {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
295 {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
296 {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
297 {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
298 {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
299 {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
300 {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
301 {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
302 {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
303 {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
304 {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
305 {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
306 {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
307 {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
308 {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
309 {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
310 {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
311 {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
312 {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
313 {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
314 {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
315 {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
316 {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
317 {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
318 {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
319 {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
320 {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
321 {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
322 {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
323 {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
324 {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
325 {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
326 {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
327 {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
328 {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
329 {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
330 {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
331 {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
332 {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
333 {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
334 {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
335 {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
336 {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
337 {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
338 {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
339 {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
340 {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
341 {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
342 {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
343 {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
344 {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
345
346 /* power per rate from sromrev 9 */
347 {"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
348 {"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
349 {"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20, 0xffff},
350 {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
351 {"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL, 0xffff},
352 {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
353 {"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20, 0xffff},
354 {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
355 {"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL, 0xffff},
356 {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
357 {"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20, 0xffff},
358 {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
359 {"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL, 0xffff},
360 {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
361 {"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20, 0xffff},
362 {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
363 {"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL, 0xffff},
364 {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
365 {"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
366 {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
367 {"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
368 {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
369 {"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
370 {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
371 {"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
372 {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
373 {"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL, 0xffff},
374 {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
375 {"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
376 {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
377 {"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
378 {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
379 {"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL, 0xffff},
380 {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
381 {"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
382 {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
383 {"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
384 {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
385 {"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL, 0xffff},
386 {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
387 {"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
388 {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
389 {"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
390 {"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
391 {"pcieingress_war", 0xffffff00, 0, SROM8_PCIEINGRESS_WAR, 0xf},
392 {"rxgainerr2ga0", 0xffffff00, 0, SROM8_RXGAINERR_2G, 0x003f},
393 {"rxgainerr2ga1", 0xffffff00, 0, SROM8_RXGAINERR_2G, 0x07c0},
394 {"rxgainerr2ga2", 0xffffff00, 0, SROM8_RXGAINERR_2G, 0xf800},
395 {"rxgainerr5gla0", 0xffffff00, 0, SROM8_RXGAINERR_5GL, 0x003f},
396 {"rxgainerr5gla1", 0xffffff00, 0, SROM8_RXGAINERR_5GL, 0x07c0},
397 {"rxgainerr5gla2", 0xffffff00, 0, SROM8_RXGAINERR_5GL, 0xf800},
398 {"rxgainerr5gma0", 0xffffff00, 0, SROM8_RXGAINERR_5GM, 0x003f},
399 {"rxgainerr5gma1", 0xffffff00, 0, SROM8_RXGAINERR_5GM, 0x07c0},
400 {"rxgainerr5gma2", 0xffffff00, 0, SROM8_RXGAINERR_5GM, 0xf800},
401 {"rxgainerr5gha0", 0xffffff00, 0, SROM8_RXGAINERR_5GH, 0x003f},
402 {"rxgainerr5gha1", 0xffffff00, 0, SROM8_RXGAINERR_5GH, 0x07c0},
403 {"rxgainerr5gha2", 0xffffff00, 0, SROM8_RXGAINERR_5GH, 0xf800},
404 {"rxgainerr5gua0", 0xffffff00, 0, SROM8_RXGAINERR_5GU, 0x003f},
405 {"rxgainerr5gua1", 0xffffff00, 0, SROM8_RXGAINERR_5GU, 0x07c0},
406 {"rxgainerr5gua2", 0xffffff00, 0, SROM8_RXGAINERR_5GU, 0xf800},
407 {"sar2g", 0xfffffe00, 0, SROM9_SAR, 0x00ff},
408 {"sar5g", 0xfffffe00, 0, SROM9_SAR, 0xff00},
409 {"noiselvl2ga0", 0xffffff00, 0, SROM8_NOISELVL_2G, 0x001f},
410 {"noiselvl2ga1", 0xffffff00, 0, SROM8_NOISELVL_2G, 0x03e0},
411 {"noiselvl2ga2", 0xffffff00, 0, SROM8_NOISELVL_2G, 0x7c00},
412 {"noiselvl5gla0", 0xffffff00, 0, SROM8_NOISELVL_5GL, 0x001f},
413 {"noiselvl5gla1", 0xffffff00, 0, SROM8_NOISELVL_5GL, 0x03e0},
414 {"noiselvl5gla2", 0xffffff00, 0, SROM8_NOISELVL_5GL, 0x7c00},
415 {"noiselvl5gma0", 0xffffff00, 0, SROM8_NOISELVL_5GM, 0x001f},
416 {"noiselvl5gma1", 0xffffff00, 0, SROM8_NOISELVL_5GM, 0x03e0},
417 {"noiselvl5gma2", 0xffffff00, 0, SROM8_NOISELVL_5GM, 0x7c00},
418 {"noiselvl5gha0", 0xffffff00, 0, SROM8_NOISELVL_5GH, 0x001f},
419 {"noiselvl5gha1", 0xffffff00, 0, SROM8_NOISELVL_5GH, 0x03e0},
420 {"noiselvl5gha2", 0xffffff00, 0, SROM8_NOISELVL_5GH, 0x7c00},
421 {"noiselvl5gua0", 0xffffff00, 0, SROM8_NOISELVL_5GU, 0x001f},
422 {"noiselvl5gua1", 0xffffff00, 0, SROM8_NOISELVL_5GU, 0x03e0},
423 {"noiselvl5gua2", 0xffffff00, 0, SROM8_NOISELVL_5GU, 0x7c00},
424 {"subband5gver", 0xffffff00, 0, SROM8_SUBBAND_PPR, 0x7},
425 {NULL, 0, 0, 0, 0}
426 };
427
428 static const sromvar_t perpath_pci_sromvars[] = {
429 {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
430 {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
431 {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
432 {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
433 {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
434 {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
435 {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
436 {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
437 {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
438 {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
439 {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
440 {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
441 {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
442 {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
443 {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
444 {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
445 {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
446 {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
447 {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
448 {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
449 {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
450 {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
451 {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
452 {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
453 {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
454 {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
455 {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
456 {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
457 {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
458 {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
459 {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
460 {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
461 {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
462 {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
463 {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
464 {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
465 {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
466 {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
467 {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
468 {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
469 {NULL, 0, 0, 0, 0}
470 };
471
472 #if !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N) && defined(PHY_TYPE_LP))
473 #define PHY_TYPE_HT 7 /* HT-Phy value */
474 #define PHY_TYPE_N 4 /* N-Phy value */
475 #define PHY_TYPE_LP 5 /* LP-Phy value */
476 #endif /* !(defined(PHY_TYPE_HT) && defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) */
477 #if !defined(PHY_TYPE_NULL)
478 #define PHY_TYPE_NULL 0xf /* Invalid Phy value */
479 #endif /* !defined(PHY_TYPE_NULL) */
480
481 typedef struct {
482 uint16 phy_type;
483 uint16 bandrange;
484 uint16 chain;
485 const char *vars;
486 } pavars_t;
487
488 static const pavars_t pavars[] = {
489 /* HTPHY */
490 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
491 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
492 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_2G, 2, "pa2gw0a2 pa2gw1a2 pa2gw2a2"},
493 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GL, 0, "pa5glw0a0 pa5glw1a0 pa5glw2a0"},
494 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GL, 1, "pa5glw0a1 pa5glw1a1 pa5glw2a1"},
495 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GL, 2, "pa5glw0a2 pa5glw1a2 pa5glw2a2"},
496 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GM, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
497 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GM, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
498 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GM, 2, "pa5gw0a2 pa5gw1a2 pa5gw2a2"},
499 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
500 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
501 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH, 2, "pa5ghw0a2 pa5ghw1a2 pa5ghw2a2"},
502 /* HTPHY PPR_SUBBAND */
503 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLL_5BAND, 0, "pa5gllw0a0 pa5gllw1a0 pa5gllw2a0"},
504 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLL_5BAND, 1, "pa5gllw0a1 pa5gllw1a1 pa5gllw2a1"},
505 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLL_5BAND, 2, "pa5gllw0a2 pa5gllw1a2 pa5gllw2a2"},
506 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLH_5BAND, 0, "pa5glhw0a0 pa5glhw1a0 pa5glhw2a0"},
507 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLH_5BAND, 1, "pa5glhw0a1 pa5glhw1a1 pa5glhw2a1"},
508 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GLH_5BAND, 2, "pa5glhw0a2 pa5glhw1a2 pa5glhw2a2"},
509 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GML_5BAND, 0, "pa5gmlw0a0 pa5gmlw1a0 pa5gmlw2a0"},
510 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GML_5BAND, 1, "pa5gmlw0a1 pa5gmlw1a1 pa5gmlw2a1"},
511 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GML_5BAND, 2, "pa5gmlw0a2 pa5gmlw1a2 pa5gmlw2a2"},
512 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GMH_5BAND, 0, "pa5gmhw0a0 pa5gmhw1a0 pa5gmhw2a0"},
513 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GMH_5BAND, 1, "pa5gmhw0a1 pa5gmhw1a1 pa5gmhw2a1"},
514 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GMH_5BAND, 2, "pa5gmhw0a2 pa5gmhw1a2 pa5gmhw2a2"},
515 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH_5BAND, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
516 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH_5BAND, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
517 {PHY_TYPE_HT, WL_CHAN_FREQ_RANGE_5GH_5BAND, 2, "pa5ghw0a2 pa5ghw1a2 pa5ghw2a2"},
518 /* NPHY */
519 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
520 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
521 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 0, "pa5glw0a0 pa5glw1a0 pa5glw2a0"},
522 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 1, "pa5glw0a1 pa5glw1a1 pa5glw2a1"},
523 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
524 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
525 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
526 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
527 /* NPHY PPR_SUBBAND */
528 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GLL_5BAND, 0, "pa5gllw0a0 pa5gllw1a0 pa5gllw2a0"},
529 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GLL_5BAND, 1, "pa5gllw0a1 pa5gllw1a1 pa5gllw2a1"},
530 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GLH_5BAND, 0, "pa5glhw0a0 pa5glhw1a0 pa5glhw2a0"},
531 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GLH_5BAND, 1, "pa5glhw0a1 pa5glhw1a1 pa5glhw2a1"},
532 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GML_5BAND, 0, "pa5gmlw0a0 pa5gmlw1a0 pa5gmlw2a0"},
533 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GML_5BAND, 1, "pa5gmlw0a1 pa5gmlw1a1 pa5gmlw2a1"},
534 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GMH_5BAND, 0, "pa5gmhw0a0 pa5gmhw1a0 pa5gmhw2a0"},
535 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GMH_5BAND, 1, "pa5gmhw0a1 pa5gmhw1a1 pa5gmhw2a1"},
536 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH_5BAND, 0, "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
537 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH_5BAND, 1, "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
538 /* LPPHY */
539 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_2G, 0, "pa0b0 pa0b1 pa0b2"},
540 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GL, 0, "pa1lob0 pa1lob1 pa1lob2"},
541 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GM, 0, "pa1b0 pa1b1 pa1b2"},
542 {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GH, 0, "pa1hib0 pa1hib1 pa1hib2"},
543 {PHY_TYPE_NULL, 0, 0, ""}
544 };
545
546 typedef struct {
547 uint16 phy_type;
548 uint16 bandrange;
549 const char *vars;
550 } povars_t;
551
552 static const povars_t povars[] = {
553 /* NPHY */
554 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 "
555 "mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"},
556 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 "
557 "mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"},
558 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 "
559 "mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"},
560 {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 "
561 "mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"},
562 {PHY_TYPE_NULL, 0, ""}
563 };
564
565 typedef struct {
566 uint8 tag; /* Broadcom subtag name */
567 uint8 len; /* Length field of the tuple, note that it includes the
568 * subtag name (1 byte): 1 + tuple content length
569 */
570 const char *params;
571 } cis_tuple_t;
572
573 #define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */
574 #define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */
575 #define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */
576 #define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */
577
578 static const cis_tuple_t cis_hnbuvars[] = {
579 {OTP_RAW1, 0, ""}, /* special case */
580 {OTP_VERS_1, 0, "smanf sproductname"}, /* special case (non BRCM tuple) */
581 {OTP_MANFID, 4, "2manfid 2prodid"}, /* special case (non BRCM tuple) */
582 {HNBU_SROMREV, 2, "1sromrev"},
583 /* NOTE: subdevid is also written to boardtype.
584 * Need to write HNBU_BOARDTYPE to change it if it is different.
585 */
586 {HNBU_CHIPID, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"},
587 {HNBU_BOARDREV, 3, "2boardrev"},
588 {HNBU_PAPARMS, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"},
589 {HNBU_AA, 3, "1aa2g 1aa5g"},
590 {HNBU_AA, 3, "1aa0 1aa1"}, /* backward compatibility */
591 {HNBU_AG, 5, "1ag0 1ag1 1ag2 1ag3"},
592 {HNBU_BOARDFLAGS, 9, "4boardflags 4boardflags2"},
593 {HNBU_LEDS, 5, "1ledbh0 1ledbh1 1ledbh2 1ledbh3"},
594 {HNBU_CCODE, 4, "2ccode 1cctl"},
595 {HNBU_CCKPO, 3, "2cckpo"},
596 {HNBU_OFDMPO, 5, "4ofdmpo"},
597 {HNBU_RDLID, 3, "2rdlid"},
598 {HNBU_RSSISMBXA2G, 3, "0rssismf2g 0rssismc2g 0rssisav2g 0bxa2g"}, /* special case */
599 {HNBU_RSSISMBXA5G, 3, "0rssismf5g 0rssismc5g 0rssisav5g 0bxa5g"}, /* special case */
600 {HNBU_XTALFREQ, 5, "4xtalfreq"},
601 {HNBU_TRI2G, 2, "1tri2g"},
602 {HNBU_TRI5G, 4, "1tri5gl 1tri5g 1tri5gh"},
603 {HNBU_RXPO2G, 2, "1rxpo2g"},
604 {HNBU_RXPO5G, 2, "1rxpo5g"},
605 {HNBU_BOARDNUM, 3, "2boardnum"},
606 {HNBU_MACADDR, 7, "6macaddr"}, /* special case */
607 {HNBU_RDLSN, 3, "2rdlsn"},
608 {HNBU_BOARDTYPE, 3, "2boardtype"},
609 {HNBU_LEDDC, 3, "2leddc"},
610 {HNBU_RDLRNDIS, 2, "1rdlndis"},
611 {HNBU_CHAINSWITCH, 5, "1txchain 1rxchain 2antswitch"},
612 {HNBU_REGREV, 2, "1regrev"},
613 {HNBU_FEM, 5, "0antswctl2g, 0triso2g, 0pdetrange2g, 0extpagain2g, 0tssipos2g"
614 "0antswctl5g, 0triso5g, 0pdetrange5g, 0extpagain5g, 0tssipos5g"
615 }, /* special case */
616 {HNBU_PAPARMS_C0, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 "
617 "2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 "
618 "2pa5gw1a0 2pa5gw2a0 2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 "
619 "2pa5ghw1a0 2pa5ghw2a0"},
620 {HNBU_PAPARMS_C1, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 "
621 "2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 "
622 "2pa5gw1a1 2pa5gw2a1 2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 "
623 "2pa5ghw1a1 2pa5ghw2a1"},
624 {HNBU_PO_CCKOFDM, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo "
625 "4ofdm5ghpo"},
626 {HNBU_PO_MCS2G, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 "
627 "2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"},
628 {HNBU_PO_MCS5GM, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 "
629 "2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"},
630 {HNBU_PO_MCS5GLH, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 "
631 "2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 "
632 "2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 "
633 "2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"},
634 {HNBU_CCKFILTTYPE, 2, "1cckdigfilttype"},
635 {HNBU_PO_CDD, 3, "2cddpo"},
636 {HNBU_PO_STBC, 3, "2stbcpo"},
637 {HNBU_PO_40M, 3, "2bw40po"},
638 {HNBU_PO_40MDUP, 3, "2bwduppo"},
639 {HNBU_RDLRWU, 2, "1rdlrwu"},
640 {HNBU_WPS, 3, "1wpsgpio 1wpsled"},
641 {HNBU_USBFS, 2, "1usbfs"},
642 {HNBU_CUSTOM1, 5, "4customvar1"},
643 {OTP_RAW, 0, ""}, /* special case */
644 {HNBU_OFDMPO5G, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"},
645 {HNBU_USBEPNUM, 3, "2usbepnum"},
646 {HNBU_CCKBW202GPO, 5, "2cckbw202gpo 2cckbw20ul2gpo"},
647 {HNBU_LEGOFDMBW202GPO, 9, "4legofdmbw202gpo 4legofdmbw20ul2gp"},
648 {HNBU_LEGOFDMBW205GPO, 25, "4legofdmbw205glpo 4legofdmbw20ul5glpo 4legofdmbw205gmpo "
649 "4legofdmbw20ul5gmpo 4legofdmbw205ghpo 4legofdmbw20ul5ghpo"},
650 {HNBU_MCS2GPO, 13, "4mcsbw202gpo 4mcsbw20ul2gpo 4mcsbw402gpo"},
651 {HNBU_MCS5GLPO, 13, "4mcsbw205glpo 4mcsbw20ul5glpo 4mcsbw405glpo"},
652 {HNBU_MCS5GMPO, 13, "4mcsbw205gmpo 4mcsbw20ul5gmpo 4mcsbw405gmpo"},
653 {HNBU_MCS5GHPO, 13, "4mcsbw205ghpo 4mcsbw20ul5ghpo 4mcsbw405ghpo"},
654 {HNBU_MCS32PO, 3, "2mcs32po"},
655 {HNBU_LEG40DUPPO, 3, "2legofdm40duppo"},
656 {HNBU_TEMPTHRESH, 3, "1tempthresh 1periodhyst"},
657 {HNBU_UUID, 17, "16uuid"},
658 {0xFF, 0, ""}
659 };
660
661 #endif /* _bcmsrom_tbl_h_ */
Tomato firmware and modifications.